Lalit Sharma
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0cbad747a1
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Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
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2021-03-04 01:10:47 -08:00 |
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Lalit Sharma
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817729ac86
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Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
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2021-03-01 22:31:15 -08:00 |
tangxifan
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e34380a654
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Merge branch 'master' into default_net_type
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2021-03-01 08:38:58 -07:00 |
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Lalit Sharma
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ea4aee8cb2
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For time-being yosys script running in no_adder mode.
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2021-02-28 22:07:23 -08:00 |
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tangxifan
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b90a17543d
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[Test] Add new test case to test default nettype in different verilog syntax
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2021-02-28 16:16:45 -07:00 |
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tangxifan
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9f4d05da67
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[Test] Bug fix for new test case
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2021-02-28 16:11:30 -07:00 |
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tangxifan
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18a7041424
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[Test] Add default net type test for explicit port mapping
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2021-02-28 12:31:32 -07:00 |
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tangxifan
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ff29cc3dff
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[Test] Move tests to a test group
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2021-02-28 12:23:35 -07:00 |
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tangxifan
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9cb1ca42fe
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[Test] Deploy default net type option to test case
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2021-02-28 12:20:43 -07:00 |
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tangxifan
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0d82e4939c
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[Test] Use unified quicklogic synthesis script and enable end-of-flow tests
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2021-02-26 09:35:40 -07:00 |
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tangxifan
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870d3a0e27
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Merge branch 'master' into dev
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2021-02-26 09:28:42 -07:00 |
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Lalit Sharma
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1082d3c677
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Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
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2021-02-25 23:39:07 -08:00 |
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Lalit Sharma
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1e48d4f6dc
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Modifying custom yosys script file name
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2021-02-25 22:21:39 -08:00 |
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tangxifan
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a62786986b
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[Test] Turn off verification in adder lut test temporarily
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2021-02-23 19:03:25 -07:00 |
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tangxifan
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53df7f69e7
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[Test] Bug fix in the test case using lut adder
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2021-02-23 16:59:46 -07:00 |
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tangxifan
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db71cc8a16
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[Test] Add LUT adder test using quicklogic synthesis script
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2021-02-23 16:50:58 -07:00 |
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tangxifan
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19f6b221b1
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[Test] Rework comments on runtime
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2021-02-22 15:25:57 -07:00 |
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tangxifan
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4803b0ce42
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[Test] Add test case for sdc controller
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2021-02-22 15:02:14 -07:00 |
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tangxifan
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2e2b1cb6e7
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[Test] Use hetergenenous FPGA architecture in quicklogic tests
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2021-02-22 13:41:04 -07:00 |
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tangxifan
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bc30f62c5a
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[Test] Add test for sdc controller
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2021-02-22 12:41:53 -07:00 |
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tangxifan
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60dc194d8f
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[Test] Bug fix in the 5clock test case
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2021-02-22 11:46:23 -07:00 |
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tangxifan
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71e0026a50
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[Test] Add new test for 5-clock counter to quicklogic tests
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2021-02-22 11:32:17 -07:00 |
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tangxifan
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bc8aa0ebc6
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[Test] Remove routing test from quicklogic's flow test
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2021-02-22 10:22:47 -07:00 |
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tangxifan
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9b6b2068ee
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[Test] Move MCNC test to benchmark sweep test group
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2021-02-22 10:18:34 -07:00 |
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tangxifan
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c1f4a434e4
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[Doc] Update README for the regression test tasks
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2021-02-22 10:17:02 -07:00 |
Lalit Narain Sharma
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be5e0cdea9
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Merge pull request #241 from lnis-uofu/add_quicklogic_tests
Adding quicklogic tests and updating the corresponding conf file to r…
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2021-02-22 09:50:26 +05:30 |
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Lalit Sharma
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576e6753f6
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Removing 2 more tests which are variant of and design
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2021-02-19 09:11:19 -08:00 |
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Lalit Sharma
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6de0954ca5
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Uncommenting all benchmarks except 2 that requires multiple clocks
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2021-02-19 08:40:26 -08:00 |
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tangxifan
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e19fc15fec
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[Test] bug fix in test case
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2021-02-18 19:37:45 -07:00 |
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tangxifan
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2e88b035ed
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[Test] Add wire LUT repacker test case
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2021-02-18 19:37:44 -07:00 |
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Lalit Sharma
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69cdc11ea5
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Uncommenting the tests that are running fine
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2021-02-18 04:17:12 -08:00 |
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tangxifan
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d85d6e964e
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Merge pull request #227 from watcag/master
Standard-cell flow
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2021-02-17 10:11:34 -07:00 |
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Lalit Sharma
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44a979288b
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Adding quicklogic tests and updating the corresponding conf file to run them
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2021-02-16 23:08:38 -08:00 |
Tarachand Pagarani
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426b6449d8
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change the test to turn off power analysis
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2021-02-15 02:45:38 -08:00 |
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tangxifan
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3ae501a5ea
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[Test] Update test case to use dedicated eblif file
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2021-02-09 15:51:57 -07:00 |
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tangxifan
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2b51b36dd6
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[Test] Now use the super LUT arch in the test case
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2021-02-09 15:27:44 -07:00 |
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tangxifan
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56284059de
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[Test] Add a test case for a super LUT
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2021-02-09 15:25:32 -07:00 |
Nachiket Kapre
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6bb2e29f17
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default to ns for time unit -- synopsys dc whines
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2021-02-09 17:04:52 -05:00 |
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Nachiket Kapre
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87c69460df
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what is going on
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2021-02-09 11:33:08 -05:00 |
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Nachiket Kapre
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cc74c6268a
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trying fix chan width
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2021-02-09 11:28:19 -05:00 |
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Nachiket Kapre
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b14b5f975d
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adding sweep for W
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2021-02-09 08:48:25 -05:00 |
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Nachiket Kapre
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d040ba569c
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merge for consideration;
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2021-02-08 21:29:34 -05:00 |
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Nachiket Kapre
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94f858fcde
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merge for consideration;
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2021-02-08 21:27:01 -05:00 |
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tangxifan
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8853370c60
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[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
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2021-02-04 20:20:10 -07:00 |
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tangxifan
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31441c0b64
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[Test] Deploy adder_8 to soft adder test
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2021-02-03 09:26:38 -07:00 |
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tangxifan
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8e36ed1ab6
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[Test] Update task configuration to use and2 eblif
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2021-02-02 15:01:15 -07:00 |
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tangxifan
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5e2847bc41
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[Test] Update test case to use eblif file
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2021-02-02 09:33:41 -07:00 |
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tangxifan
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9ff5e7926b
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[Test] Update test case to use the adder benchmark
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2021-02-02 09:24:39 -07:00 |
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tangxifan
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04594cb7ab
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[Test] Adapt bitstream annotatin file to parser's requirement
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2021-02-01 17:38:36 -07:00 |
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tangxifan
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280c9620aa
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[Test] Add an example bitstream annotation file
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2021-02-01 16:01:21 -07:00 |