tangxifan
|
542571ce89
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[test] code format
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2024-08-09 18:20:27 -07:00 |
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tangxifan
|
e6c508f081
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[test] add a new arch to validate that clock network tap supports subtiles
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2024-08-09 16:51:34 -07:00 |
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tangxifan
|
b6b038a73d
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[test] add a new arch to test y- entry point of clock network
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2024-07-30 12:40:41 -07:00 |
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tangxifan
|
77304164f4
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[test] rework pin loc for k4_frac_N4_tileable_fracff_40nm to save route W
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2024-07-10 10:13:41 -07:00 |
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tangxifan
|
a16b3df063
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[test] update arch to allow clock access on CLB inputs
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2024-07-09 20:59:44 -07:00 |
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tangxifan
|
03c1c6f917
|
[test] code format
|
2024-07-08 18:35:23 -07:00 |
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tangxifan
|
c7d6c3ab61
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[arch] now all the outputs of I/O can only on 1 side
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2024-07-08 18:34:13 -07:00 |
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tangxifan
|
ad053cddca
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[test] code format
|
2024-07-08 18:02:30 -07:00 |
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tangxifan
|
b50acacfba
|
[test] fixed some bug in pin loc; Outputs are not recommend on the fringe I/O tiles
|
2024-07-08 15:09:31 -07:00 |
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tangxifan
|
ff56139a53
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[test] debugging
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2024-07-07 23:07:51 -07:00 |
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tangxifan
|
b0851a6299
|
[test] debugging
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2024-07-07 23:05:37 -07:00 |
|
tangxifan
|
686cd761b7
|
[test] debugging
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2024-07-07 22:48:21 -07:00 |
|
tangxifan
|
57a378ae59
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[test] typo
|
2024-07-07 22:35:14 -07:00 |
|
tangxifan
|
f784e58383
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[test] typo
|
2024-07-07 22:33:45 -07:00 |
|
tangxifan
|
1a5e2392fc
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[test] add a new testcase to validate clock network when perimeter cb is on
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2024-07-07 22:32:13 -07:00 |
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tangxifan
|
439de61fd0
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[test] fixed a bug on ecb support
|
2024-07-07 14:00:11 -07:00 |
|
tangxifan
|
201b2555e5
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[test] code format
|
2024-07-06 12:15:08 -07:00 |
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tangxifan
|
43ca3ec747
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[test] make arch pin loc for spread for perimeter cb validation
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2024-07-06 12:11:31 -07:00 |
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tangxifan
|
fe73e03c69
|
[test] changing arch
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2024-07-04 21:31:43 -07:00 |
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tangxifan
|
4064c29d49
|
[test] updating arch for perimeter cb
|
2024-07-04 21:23:15 -07:00 |
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tangxifan
|
5865aebf93
|
[test] add new arch
|
2024-07-04 21:12:26 -07:00 |
|
tangxifan
|
a78fddc3cb
|
[test] add a new testcase to validate perimeter cb
|
2024-07-03 19:59:24 -07:00 |
|
tangxifan
|
1e7cca8ceb
|
[arch] code format
|
2024-07-02 11:52:30 -07:00 |
|
tangxifan
|
bc2f02866d
|
[test] update testcase for 2-clk on programmable clock network
|
2024-06-29 17:17:05 -07:00 |
|
tangxifan
|
c99178f350
|
[test] fixed a bug on pin locations
|
2024-06-25 12:34:52 -07:00 |
|
tangxifan
|
c2e759fa70
|
[arch] fixed some bugs
|
2024-06-21 18:42:29 -07:00 |
|
tangxifan
|
852b01aaff
|
[test] rework
|
2024-05-20 17:20:04 -07:00 |
|
tangxifan
|
a9a5fbee34
|
[test] add fully connected feedback connections to directlist
|
2024-05-20 17:02:20 -07:00 |
|
tangxifan
|
6146d0be9f
|
[arch] Move clb I to right side as left side is not supported yet
|
2024-05-20 13:43:04 -07:00 |
|
tangxifan
|
65dd342c60
|
[arch] typo
|
2024-05-20 12:11:22 -07:00 |
|
tangxifan
|
c795dd2f1a
|
[arch] adding a new arch where feedback loops are modelled by direct connections
|
2024-05-20 12:00:39 -07:00 |
|
tangxifan
|
3615bdceeb
|
[test] avoid no-fanin errors for hetero arch
|
2024-05-06 15:32:27 -07:00 |
|
tangxifan
|
dff03e7993
|
[test] enable missing options in the arch used by benchmark sweeping tests
|
2023-11-14 09:45:02 -08:00 |
|
tangxifan
|
0b473e3454
|
[test] fixed the bug in single-mode lut testcase
|
2023-11-14 09:35:26 -08:00 |
|
tangxifan
|
d108284105
|
[test] update arch to keep golden outputs
|
2023-11-14 09:31:07 -08:00 |
|
tangxifan
|
913434b70d
|
[test] fixed the bug that golden netlists are modified
|
2023-11-14 09:28:57 -08:00 |
|
tangxifan
|
59d086a27f
|
[test] try to keep the golden inputs
|
2023-11-14 09:25:45 -08:00 |
|
tangxifan
|
1b8748abb4
|
[core] update vtr
|
2023-11-13 14:21:34 -08:00 |
|
tangxifan
|
d78f18d235
|
[test] add new testcase
|
2023-11-13 14:11:34 -08:00 |
|
tangxifan
|
56cedf6c8b
|
[test] added a new test case to validate the support on different wire segment distribution on X and Y
|
2023-08-22 11:20:14 -07:00 |
|
tangxifan
|
1b132fd667
|
[test] add a new testcase to validate the support on different routing channel width on X and Y
|
2023-08-22 11:06:12 -07:00 |
|
tangxifan
|
e4c5265b68
|
[test] arch syntax
|
2023-08-18 21:40:56 -07:00 |
|
tangxifan
|
5ac8919ce0
|
[test] add a new testcase to validate subtile with tile annotations
|
2023-08-18 21:37:15 -07:00 |
|
tangxifan
|
f69520d0c3
|
[arch] format
|
2023-08-18 11:15:25 -07:00 |
|
tangxifan
|
170a49c34f
|
[test] fix a bug in arch file
|
2023-08-18 11:15:05 -07:00 |
|
tangxifan
|
e82e4f487e
|
[test] add a new test to validate io subtile support
|
2023-08-18 11:13:34 -07:00 |
|
tangxifan
|
4afd48d930
|
[test] format
|
2023-08-17 15:33:09 -07:00 |
|
tangxifan
|
463897f78e
|
[test] fixed a bug in arch
|
2023-08-17 15:28:59 -07:00 |
|
tangxifan
|
3ac3eb4624
|
[test] adding more flavor to the L shape
|
2023-08-17 15:08:27 -07:00 |
|
tangxifan
|
253d5fa26c
|
[core] a new test to validate the L shape in homo geneous fpga
|
2023-08-11 13:05:46 -07:00 |