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[test] code format

This commit is contained in:
tangxifan 2024-08-09 18:20:27 -07:00
parent 4def678b11
commit 542571ce89
1 changed files with 6 additions and 6 deletions
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12
openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_IoSubtile_40nm.xml
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@ -49,7 +49,7 @@
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="left"/>
<loc side="top"/>
<loc side="right">fpga_input[0:5].clk[0:0]</loc>
<loc side="bottom">fpga_input[0:5].inpad[0:0]</loc>
@ -85,8 +85,8 @@
<pinlocations pattern="custom">
<loc side="left">fpga_input[0:2].inpad[0:0] fpga_input[0:2].clk[0:0]</loc>
<loc side="right"/>
<loc side="top"></loc>
<loc side="bottom"></loc>
<loc side="top"/>
<loc side="bottom"/>
</pinlocations>
</sub_tile>
<sub_tile name="fpga_output" capacity="3">
@ -120,7 +120,7 @@
<loc side="right">fpga_input[0:3].clk[0:0]</loc>
<loc side="bottom"/>
<loc side="top">fpga_input[0:3].inpad[0:0]</loc>
<loc side="left"></loc>
<loc side="left"/>
</pinlocations>
</sub_tile>
<sub_tile name="fpga_output" capacity="4">
@ -153,8 +153,8 @@
<pinlocations pattern="custom">
<loc side="right">fpga_input[0:3].inpad[0:0] fpga_input[0:3].clk[0:0]</loc>
<loc side="left"/>
<loc side="top"></loc>
<loc side="bottom"></loc>
<loc side="top"/>
<loc side="bottom"/>
</pinlocations>
</sub_tile>
<sub_tile name="fpga_output" capacity="4">