tangxifan
|
4f80b1a28a
|
[core] skip adding opin when it does not drive any inputs inside a gsb
|
2024-08-10 23:19:06 -07:00 |
tangxifan
|
542571ce89
|
[test] code format
|
2024-08-09 18:20:27 -07:00 |
tangxifan
|
4def678b11
|
[core] code format
|
2024-08-09 18:20:18 -07:00 |
tangxifan
|
e7ab7a61f1
|
[doc] update to use tile name and index when defining clock taps
|
2024-08-09 18:09:12 -07:00 |
tangxifan
|
1af1306444
|
[core] fixed a bug where pin index for subtile is wrongly calculated for clock network taps
|
2024-08-09 18:02:49 -07:00 |
tangxifan
|
f1ab44a212
|
[core] fixed a bug
|
2024-08-09 17:10:58 -07:00 |
tangxifan
|
c6246ae905
|
[test] typo
|
2024-08-09 17:10:51 -07:00 |
tangxifan
|
a05bfb55dd
|
[test] typo
|
2024-08-09 17:05:48 -07:00 |
tangxifan
|
38f1bdba4e
|
[test] add a new test case
|
2024-08-09 17:04:10 -07:00 |
tangxifan
|
602ab72002
|
[test] add associated openfpga arch
|
2024-08-09 17:01:23 -07:00 |
tangxifan
|
e6c508f081
|
[test] add a new arch to validate that clock network tap supports subtiles
|
2024-08-09 16:51:34 -07:00 |
tangxifan
|
e4d7192e50
|
[core] fixed a bug where subtile was used for clock network tap name
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2024-08-09 16:16:05 -07:00 |
tangxifan
|
a4091efc79
|
Merge pull request #1786 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-08-08 10:02:51 -07:00 |
github-actions[bot]
|
dc680c85a7
|
Updated Patch Count
|
2024-08-08 17:00:24 +00:00 |
tangxifan
|
c400e2f92c
|
Merge pull request #1785 from lnis-uofu/dependabot/submodules/yosys-77b2ae2
Bump yosys from `669f8b1` to `77b2ae2`
|
2024-08-08 10:00:03 -07:00 |
dependabot[bot]
|
5cffc18ba7
|
Bump yosys from `669f8b1` to `77b2ae2`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `669f8b1` to `77b2ae2`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](669f8b18f0...77b2ae2e39 )
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-08-08 06:18:11 +00:00 |
tangxifan
|
7c3830f743
|
Merge pull request #1784 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-08-07 10:31:28 -07:00 |
github-actions[bot]
|
2dfbb4fc28
|
Updated Patch Count
|
2024-08-07 17:19:10 +00:00 |
tangxifan
|
bdf71282c8
|
Merge pull request #1783 from lnis-uofu/dependabot/submodules/yosys-669f8b1
Bump yosys from `d2b5788` to `669f8b1`
|
2024-08-07 10:18:47 -07:00 |
dependabot[bot]
|
c8839b0304
|
Bump yosys from `d2b5788` to `669f8b1`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `d2b5788` to `669f8b1`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](d2b5788674...669f8b18f0 )
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-08-07 06:04:30 +00:00 |
tangxifan
|
b04252c2f3
|
Merge pull request #1782 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-08-06 22:41:39 -07:00 |
github-actions[bot]
|
d4487e9fec
|
Updated Patch Count
|
2024-08-07 05:39:32 +00:00 |
tangxifan
|
1e6e0442ee
|
Merge pull request #1781 from lnis-uofu/xt_rpt_ref
Rework the option ``constant_undriven_wire``
|
2024-08-06 22:39:12 -07:00 |
tangxifan
|
1026df4890
|
[test] add new tests to validate the options for undriven inputs in verilog netlists
|
2024-08-06 20:58:00 -07:00 |
tangxifan
|
1d5acea7e0
|
[core] typo
|
2024-08-06 20:17:15 -07:00 |
tangxifan
|
1225679aac
|
[core] code format
|
2024-08-06 17:35:44 -07:00 |
tangxifan
|
85c9bdc6f9
|
[doc] add new format
|
2024-08-06 17:28:03 -07:00 |
tangxifan
|
0dba4082d1
|
[core] syntax
|
2024-08-06 17:20:34 -07:00 |
tangxifan
|
ac2337d24b
|
[core] rework the option 'constant_undriven_inputs'
|
2024-08-06 16:50:49 -07:00 |
tangxifan
|
41160bb2c3
|
Merge pull request #1779 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-08-06 14:26:27 -07:00 |
github-actions[bot]
|
96783f31c3
|
Updated Patch Count
|
2024-08-06 19:55:50 +00:00 |
tangxifan
|
f456fef23d
|
Merge pull request #1778 from lnis-uofu/dependabot/submodules/yosys-d2b5788
Bump yosys from `c788484` to `d2b5788`
|
2024-08-06 12:55:27 -07:00 |
dependabot[bot]
|
5a70503317
|
Bump yosys from `c788484` to `d2b5788`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `c788484` to `d2b5788`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](c788484679...d2b5788674 )
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-08-06 06:31:32 +00:00 |
tangxifan
|
10b5dc5e6b
|
Merge pull request #1777 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-08-03 15:08:13 -07:00 |
github-actions[bot]
|
a0cb78f6ae
|
Updated Patch Count
|
2024-08-03 22:04:50 +00:00 |
tangxifan
|
a7920b16a9
|
Merge pull request #1776 from lnis-uofu/xt_doc
[doc] format to resolve latexpdf build errors; now local build passes
|
2024-08-03 15:04:09 -07:00 |
tangxifan
|
c11a2c7381
|
[doc] format to resolve latexpdf build errors; now local build passes
|
2024-08-03 15:03:14 -07:00 |
tangxifan
|
328c3873cc
|
Merge pull request #1775 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-08-03 14:58:52 -07:00 |
github-actions[bot]
|
92b0df57a9
|
Updated Patch Count
|
2024-08-03 21:35:23 +00:00 |
tangxifan
|
d6f26863e8
|
Merge pull request #1774 from lnis-uofu/xt_doc
Update .readthedocs.yml
|
2024-08-03 14:35:05 -07:00 |
tangxifan
|
c85bf97c06
|
Update .readthedocs.yml
|
2024-08-03 00:26:24 -07:00 |
tangxifan
|
23f43459bd
|
Merge pull request #1773 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-08-02 21:23:35 -07:00 |
github-actions[bot]
|
94c6b6322a
|
Updated Patch Count
|
2024-08-03 04:00:29 +00:00 |
tangxifan
|
0edd5529c3
|
Merge pull request #1772 from lnis-uofu/xt_fkey
[core] fixed a bug where pb pin fixup does not support perimeter cb
|
2024-08-02 21:00:06 -07:00 |
tangxifan
|
8a07564d80
|
Merge branch 'master' into xt_fkey
|
2024-08-02 19:11:49 -07:00 |
tangxifan
|
57adf97fd4
|
[test] fixed some bugs in clock arch
|
2024-08-02 18:34:59 -07:00 |
tangxifan
|
2e6b311d04
|
[core] add more details to debug messages
|
2024-08-02 18:33:43 -07:00 |
tangxifan
|
91c4336a4a
|
[test] add a new testcase to validate 3-layer clock architecture
|
2024-08-02 18:18:49 -07:00 |
tangxifan
|
eeaa3373c6
|
[core] code format
|
2024-08-02 17:48:47 -07:00 |
tangxifan
|
82cf7bbb8c
|
[core] Add verbose mode on find_node() for clock rr graph
|
2024-08-02 17:47:41 -07:00 |