Changes the jtag_interface->register_callbacks field to a list of
commands to be registered. Changes callback to invocation of
register_commands() with that command registration list. Removes all
JTAG interface driver register_command callback functions, which the
previous commits had converted into identical calls.
Use register_commands() with command registration array.
---
This module was broken by previous changes, but no one has complained.
Are there still users for this modules?
Use the new command registration chaining capabilities to eliminate
the foo_register_commands helper, folding its remaining command
handler setup into the hello_command_handlers registration array.
Adds the ability to chain registration structures. Modules can define a
command with the 'chain' and 'num_chain' fields defined in their
registration table, and the register_commands() function will initialize
these commands. If the registration record creates a new command, then
the chained commands are created under it; otherwise, they are created
in the same context as the other commands (i.e. the parent argument).
Use register_commands() to register low-level command handlers,
adding a builtin_command_handlers declaration that is easy to understand.
Splits help and usage information into their appropriate fields.
Adds the usage command, to display usage information for commands.
The output for this command will remain erronenously empty until
commands are updated to use these new coventions.
The register_commands API takes multiple commands in one call, allowing
modules to declare and pass a much simpler (and more explicit) array of
command_registration records.
Add a structure to encapsulate command registration information, rather
than passing them all as parameters. Enables further API changes that
require additional required or optional parameters.
Updates the register_command API and COMMAND_REGISTER macro to use it,
along with their documentation.
Provides a migration path for the widely used register_command API,
which needs to be updated to provide new functionality.
This macro allows the API to change without having to update all of its
callers at the same time.
There was a lot of needless handshaking overhead in the current
Cortex-A8 DCC/ITR operations, since the status read by each step
was discarded rather than letting the next step know it.
This shrinks the handshaking by: (a) passing status along from
previous steps, avoiding re-fetching; which enables the big win
(b) relying on a useful invariant: that the DSCR_INSTR_COMP bit
is set after every call to a DPM method.
A "reg sp_usr" call previously took 17 flushes; now it takes just 9.
This visibly speeds common operations like entry to debug state and
stepping, as well as "arm reg" and so on.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This replaces two versions of register access functions. One
was commented out, and seemed to have uncertain intent. The
other was fairly new, and helped motivate the DPM framework
once I observed that the ARM11 was doing the very same ops.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This implements the DPM interface for Cortex-A8 cores. It
also adds a synchronization operation to the DPM framework,
which is needed by the Cortex-A8 after CPSR writes.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Make various functions static, add some comments, report
vector catch as a flavor of DBG_REASON_BREAKPOINT, get
rid of needless/undesirable ARMV4_5_CORE_REG_MODE, etc.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The previous implementation was unnecessarily complex. Get rid of the loops,
let vsnprintf() tell us directly how much storage we need and allocate that. A
second pass writes the actual string. Also add a va_end() that was missing.
This should be much faster for large strings and less wasteful for small ones.
A quirk that has been retained is that some callers patch in a newline at the
end of the returned string and depend on alloc_vprintf to allocate at least
one byte extra.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Signed-off-by: Zachary T Welch <zw@superlucidity.net>
Rewrite rlink_init routine to use jtag_usb_open helper. Eliminates
some spurious calls to exit().
Wraps a tremendously long line of comment to fit 80 columns too.
Begins to consolidate code used by several USB JTAG interfaces.
This first patch provides the required build system changes and
a common jtag_usb_open routine, which will replace the guts for
probing the busses and devices for possible VID/PID matches.
The following patches convert each driver to use it.
This finishes the basic switchover to the new register code,
for everything except the debug registers. (And maybe we
shouldn't have a cache for *those* which works this way...)
The context save/restore code now uses the new code, but
it's in a slightly different sequence. That should be fine
since the R0/PC/CPSR stuff is all that really matters (and
if we can update those, we can update the rest).
Now there's no longer a way any code can be confused about
which copy of "r1" (etc) to use.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
As with single stepping, the previous stuff was needed because
the ARM11 code wasn't using the standard ARM base type and
register access ... but now those mechanisms work, so we can
switch out that special-purpose glue, in favor of the more
thoroughly tested/capable "standard" code.
Fixes a bug in the resume() implementation: it wasn't handling
two of its arguments correctly, preventing the "flash erase_check"
algorithm from working. (This code needs a *subsequent* update
for correct register handling, though... removing the confusion
about which "r2", for example, to use.)
This should resolve some "FIXME" comments too, for Thumb and
processor mode support. It also gets rid of a nasty exit()
call; servers should only have *clean* shutdown paths.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The previous stuff was needed because the ARM11 code wasn't using
the standard ARM base type and register access ... but now those
mechanisms work, so we can switch out that special-purpose glue.
This should resolve all the "FIXME -- handle Thumb single stepping"
comments too, and properly handle the processor's mode. (Modulo
the issue that this code doesn't yet handle two-byte breakpoints.)
Clarify the comments about the the hardware single stepping. When
we eventually share breakpoint code with Cortex-A8, we can just make
that be the default on cores which support it. We may still want an
override command, not just to facilitate testing but to cope with
"instruction address mismatch" not quite being true single-step.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This provides "standard" ARM register support -- with twenty or
more shadow registers on top of what this code now handles, but
properly associated with the various core modes -- parallel to
the current register code. That is, the current code is stilil
managing the "current" registers; the new code shadows them.
You can see all the registers with "arm reg", modify the shadows
like "r8_fiq" or "sp_abt" with "reg", and see them get properly
written back when you step. (Just don't do that with any of the
registers managed by the "old" code ...)
It also switches to using more standard code, relying on those
standard registers, in two places: (a) the poll status display,
which now shows core state (ARM/Thumb/...) and mode (Supervisor,
IRQ, etc); and (b) GDB register access.
So it's not a full migration, there are warts -- every place that
touches the old register cache is a potential bug -- but it's a
small more-or-less-comprehensible step that's even somewhat useful.
Later patches complete the migration.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This was a private mechanism to snapshot registers before leaving
debug state, and then on reentry to optionally display what changed.
It was coupled to the private register cache, which won't be sticking
around in that form for much longer. Remove (instead of teaching
it how to handle *all* the registers).
(The idea is interesting, but we ought to be able to implement
this in a generic way. Ideally through Tcl scripts that can
automatically be invoked following debug entry...)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This is a very thin layer over some of the current ARM11
debug TAP utilities. The layer isn't yet hooked up.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
First version of interface for sharing code between ARMv6 and ARMv7a
debug modules ... now the architecture includes debug support. (Not
the same as for the trimmed-down v7m or v6m though!) This is a first
version of an interface that will let the ARM11 and Cortex-A8 support
share code, features, and bugfixes. Based on existing code from both
of those cores.
The ARM v7-AR architecture specification calls this commonality the
"Debug Programmer's Model (DPM)", which seemed to be an appropriate
acronym -- a TLA even! -- for use in our code. Made it so. :)
The initial scope of this just supports register access, and is geared
towards supporting top level "struct arm" mechanisms. Later, things
like breakpoint and watchpoint support should be included.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Add $HOME/.openocd as the first default script search directory, allowing
the user to override the standard scripts.
Update the user guide with information on where OpenOCD expects to find
configuration files and scripts. Also fixed some minor formatting issues.
Add entry to NEWS as well.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
For now there's no point in saving this stuff after examine()
checks it out as OK. Ditto exporting symbols that aren't
used outside of the module which defines them. In fact, those
two things needlessly complicate the code...
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Make this code look more like the rest of the OpenOCD code.
- Use calloc() directly, not NEW() ... and fix some potential
memory leaks while we're at it.
- Remove FNC_INFO ... it's a NOP that just clutters things,
and it's trivial for developers to add tracing as needed.
- Replace FNC_INFO_NOTIMPLEMENTED with LOG_WARNING calls;
ditto. And stop having those call sites wrongly succeed!
- Waste less space with the CHECK_RETVAL() macro.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This will allow data to be allocated in read only
memory instead of on the stack. Speeds things up
and reduces stack usage.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
buf_set_u32() operated on an uninitialized stack
variable with non-byte boundaries, which led to
warnings about reading uninitialized stack.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Start using the arm_reg_current() call. This shrinks and speeds
the affected code. It can also prevent some coredumps coming from
invalid CPSR values ... the ARMV4_5_CORE_REG_MODE() macro returns
bogus registers if e.g. "Secure Monitor" mode isn't supported by
the current CPU.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
We don't need to use size_t in these places; so it's easy
to be rid of the need for this #ifdef and its MS-derived
portability problems.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
With -O3 when inlining aggressively the total stack usage will
be the sum of many fn's, which can easily get out of hand.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Have arm_set_cpsr() handle the two core state flags, updating
the CPU state. This eliminates code in various debug_entry()
paths, and marginally improves handling of the J bit.
Catch and comment a few holes in the handling of the J bit on
ARM926ejs cores ... it's unlikely our users will care about
Jazelle mode, but we can at least warn of Impending Doom. If
anyone does use it, these breadcrumbs may help them to find
the right path through the code.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Define arm_reg_current() ... returning handle to a given register,
and encapsulating the current mode's register shadowing. It's got
one current use, for reporting the current register set to GDB.
This will let later patches clean up much ARMV4_5_CORE_REG_MODE()
nastiness, saving a bit of code.
Define and use arm_set_cpsr() ... initially it updates the cached
CPSR and sets up state used by arm_reg_current(), plus any SPSR
handle. (Later: can also set up for T and J bits.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Stash a pointer to the CPSR in the "struct arm", to help get rid
of the (common) references to its index in the register cache.
This removes almost all references to CPSR offsets outside of the
toplevel ARM code ... except a pair related to the current ARM11
"simulator" logic (which should be removable soonish).
This is a net minor code shrink of a few hundred bytes of object
code, and also makes the code more readable.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Minor cleanup of ARM11 register handling: remove disabled
register hooks. This should all be handled by shared code,
and this stuff is just clutter.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Add this to ease debugging why the standard scripts aren't
found on the default script search path in some build/install
enviroments. Especially on Windows it's not straight forward
where openocd actually looks for the scripts.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Implementations need to access the register struct they modify;
make it easier and less error-prone to identify the instance.
(This removes over 10% of the ARMV4_5_CORE_REG_MODE nastiness...)
Plus some minor fixes noted when making these updates: ARM7/ARM9
accessor methods should be static; don't leave CPSR wrongly marked
"dirty"; note significant XScale omissions in register handling;
and have armv4_5_build_reg_cache() record its result.
Rename "struct armv4_5_core_reg" as "struct arm_reg"; it's used
for more than those older architecture generations.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Remove two commands that were documented as "debug commands"
and where "you probably don't want to use this". We never
intended to support them, and at least one problem report
boiled down to using this when it shouldn't have been used.
Update the docs on the existing register commands to talk a
bit more about register access and cache behavior. (Those
debug commands existed largely to *bypass* the cache.) And
fix some minor doc goofs that snuck in with recent changes,
renaming "armv4_5" as "arm" and "arm9tdmi" as "arm9".
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Rewrite means for scripts to register help text for commands. These
cause the new commands to be stored in the command heirarchy, with
built-in commands; however, they will never be invoked there because
they do not receive a command handler. The same trick is used for
the Jim commands.
Remove the old helpers that were used to register commands.
For the startup.tcl code to use built-in commands, the context must be
associated with the interpreter temporarily. This will be required to
add help text.
Rewrites 'help' command in C, using new 'cmd_help' for display. Adds the
built-in 'help' COMMAND_HANDLER to provide better output than the
TCL-based script command (e.g. heirarchical listing of commands).
The help string is stored in the command structure, though it conitnues
to be pushed into the Jim environment. The current idiomatic usage
suggests the addition of a usage field as well, to provide two levels
of detail for users to consume (i.e. terse usage list, or verbose help).
Creates a helper function, cmd_help, which displays the help string
for a single command. Presently, it is called from the loop in help.
The routine has been extended to allow indentation of command groups,
so an improved help command can improve the display of information.
Refactors the command registration to use helpers to simplify the code.
The unregistration routines were made more flexible by allowing them
to operate on a single command, such that one can remove all of a
commands children in one step (perhaps before adding back a 'config'
subcommand that allows getting the others back). Eliminates a bit
of duplicated code and adds full API documentation for these routines.
The previous version never wrote dirty registers
for non-current CPU modes ... fix that.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
We *should* be able to read and write registers in any core mode,
instead of being stuck with whatever mode the core was when we
entered debug state. This patch makes them work.
Note that the current restore_context() only handles the current
mode; writing to other-mode registers is a NOP without a followup
patch fixing that. Also, that SPSR access needed some bugfixes;
it was confused with CPSR.
Secure monitor mode also seems dubious; there's probably more to
be done before that's sufficiently understood by the debugger.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Create a generic register_cache_invalidate(), and use it to
replace three all-but-identical core-specific routines:
- armv4_5_invalidate_core_regs()
- armv7m_invalidate_core_regs
- mips32_invalidate_core_regs() too.
Make cache->num_regs be unsigned, avoiding various errors.
Net code shrink and simplification.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Move bulk of for-loop to a new static command helper function.
Adds handle_nand_list_drivers command handler, registered as
'nand drivers'.
Improves command help text and error reporting.
Move variables to point of first use, reducing their scope.
Add driver_name temporary to help arguments be changed later.
Eliminates the useless 'found' variable, changing the code to terminate
the loop immediate and return its success.
After adding support for referencing banks by name, renames
the COMMAND_HELPERs appropriately:
flash_command_get_bank_by_num -> flash_command_get_bank
nand_command_get_device_by_num -> flash_command_get_device
Add get_flash_bank_by_name (and get_nand_device_by_name) helpers
to retrieves struct flash_bank * (struct nand_device *) given a
driver name and an (optional) driver-specific bank index.
These are used to extend flash_command_get_bank_by_num (and
nand_command_get_device_by_num) to allow all flash (nand) commands to
reference defined banks by name, not just by number.
To avoid some code duplication, add the flash/common.[ch] files to hold
functionality common to both types driver. The first two methods are
helpers for the above routines to find a bank specified by a "name" or
"name.index" string. get_flash_name_index() finds the '.index' portion,
while flash_driver_name_matches() performs the string portion matching.
Just pre-allocate memory for the cached register value.
Shrinks heap overhead; increases locality-of-reference.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Combine register names with other per-register data into a
single template structure. This saves space, and makes it
easier to change how registers get handled (by shrinking
the number of places that care about cache indices).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The examine() method has some conceptual breakage. Cope
with it by manually splitting out the run-once parts from
the after-each-reset parts ... this gets rid of memory
leaks and speeds up resets after the first one.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
We don't want an ARMv7-specific core state enumeration just to
add ThumbEE state. Update the generic stuff to handle that,
and replace the V7-specific bits with it.
For Cortex-A8: on debug entry, check both the T and J bits
instead of just the T bit. When the J bit is set, set the
right state and warn appropriately.
(And while we're at it, move the generic arm struct to the front
of the v7a structure, for somewhat better code generation.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The only way ARMv7-A modes differ from ARMv4/ARMv5 flavors
is that v7-A is allowed to include "Secure monitor" support.
That's now handled by our standard top-level ARM code ... so
phase out the stuff that's specific to ARMv7-A.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Removing the fast command eliminates the fast_and_dangerous global,
which was used only by arm7_9_common as an initializer. The command
is not called in the tree; instead, more explicit commands are used.
The jim_global_long function was not used anywhere in the tree.
Adds the foo/bar commands to provide more working examples of command
argument parsing, including the new handle_command_parse_bool helper.
Updates hello command help text to provide useful information.
This patch changes the behavior of all boolean parsing callers to
accept any one of "true/enable/on/yes/1" or "false/disable/off/no/0".
Since one particular pair will be most appropriate in any given
situation, the specific macros should continue to be used in
order to display the most informative error messages possible.
Rewrite arm11_handle_bool to provide a generic on/off command helper.
Refactors COMMAND_PARSE_BOOL to use new command_parse_bool helper,
which gets reused by the new command_parse_bool_any helper.
This later helper is called by the new command helper function to
accepts any on/off, enable/disable, true/false, yes/no, or 0/1 parameter.
Updates all command parsing of simple "enable" and "disable" arguments.
A few case in the tree use a tri-state or extended arguments, which
cannot use this simple macro.
Simlifies the xscale icache/dcache command handler logic.
Adds several macros similar to COMMAND_PARSE_NUMBER, but for parsing
boolean command arguments. Two flavors are provided to provide
drop-in compatibility with existing code, allow for the elimination
of a lot of code bloat while improving the error checking and reporting.
COMMAND_PARSE_ON_OFF parses "on"/"off" command parameters.
COMMAND_PARSE_ENABLE parses "enable"/"disable" command parameters.
Both print the error and return an error out of the calling function.
Change the layout to show the "Secure Monitor" registers too,
when they're present.
Instead of lining registers for each of six (or seven) modes up
in adjacent vertical columns, display each mode's registers (or
shadows) in a single block, avoiding duplicate value displays.
This also lets us shrink the line length to fits in standard 80
character lines ... six or seven 18-character columns can't fit.
Relabel "r13" as "sp", so it's more meaningful.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
When we read the CPSR on debug entry, update the CPSR cache in all
cases, not just when the current processor state is User or System.
Plus minor cleanup of how the (too-many) other registers' cache
entries get updated.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
If the core doesn't provide an optimized version of this
method, provide one without core-specific optimizations.
Use this to make Cortex-A8 support the "arm reg" command.
Related: make the two register access methods properly static,
have the "set" log a "not halted" error too, and make sure
that the "valid" flag is set on successful reads.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
ARMv7-A doesn't need to duplicate all the standard ARM code
for register handling.
- Switch Cortex-A8 to use the standard register code
- Remove duplicated infrastructure from ARMv7-A
- Have ARMv7-A arch_state() show CPSR, like other ARMs
Add comments to show where the Cortex-A8 isn't actually doing
the right thing for register reads/writes, unless core happens
to be in the right mode to start with. (Looks like maybe there
may be generic confusion between saved/current PSR values in all
the ARM code ...)
Make related ARMv7-A and Cortex-A8 symbols properly static.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Teach the "armv4_5" register code to understand about the
secure monitor mode:
- Add the other three shadowed registers to the arrays
- Support another internal mode number (sigh) in mappings
- Catch malloc/calloc failures building that register cache
This should kick in for Cortex-A8 and ARM1176.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
It's used to flag cores with the "TrustZone" extension,
and is used in subsequent patches to set up support for
the registers shadowed by its new secure monitor mode.
The ARM1176 and Cortex-A8 both support this new mode.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The previous changes to move the startup TCL code resulted in segfaults
during startup. This seemingly innocuous patch fixes the problem.
I would explain why changing from 'foo[]' to '*foo' caused this issue,
but the difference seems superficial. For now, this hot fix will do,
but this issue might bear further scrutiny.
Moves definitions for each layer into their own file, eliminating
layering violations in the built-in TCL code. Updates src/Makefile.am
rules to include all files in the final startup.tcl input file, and
others Makefile.am rules to distribute the new files in our packages.
The recent migration broke them, the fixes broken them in a new way,
but this should restore them to working order. Eliminates the
temporary variable, as the CMD_NAME macro can once again be use
in routines that increment CMD_ARGV without nasty side-effects.
Also, this is on the path to increasing the word size for
bit vectors from 8 to something wider(32? natural host machine
width?)
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Add a new is_arm_mode() predicate, and use it to replace almost
all calls to current armv4_5_mode_to_number().
Eventually those internal mode numbers should vanish... along
with their siblings in the armv7a.c file.
Remove a handful of superfluous checks ... e.g. the mode number
was just initialized, or (debug entry methods) already validated.
Move one of the macros using internal mode numbers into the only
file which uses that macro. Make the tables manipulated with
those numbers be read-only and, where possible, static so they're
not confused with part of the generic ARM interface.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Add and use arm_mode_name() to map from PSR bits to user
meaningful names. It uses a new table which, later, can
be used to hold other mode-coupled data.
Add definitions for the "Secure Monitor" mode, as seen on
some ARM11 cores (like ARM1176) and on Cortex-A8. The
previous mode name scheme didn't understand that mode.
Remove the old mechanism ... there were two copies, caused
by Cortex-A8 needing to add "Secure Monitor" mode support.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
All ARM cores need to provide obsolete FPA registers in their
GDB register dumps. (Even though cores with floating point
support now generally use some version of VFP...)
Clean up that support a bit by sharing the same dummy registers,
and removing the duplicate copies. Eventually we shouldn't need
to export those dummies.
(This makes the ARMv7-M support include the armv4_5 header, and
cleans up related #includes, but doesn't yet use anything from
there except those dummies.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Adds the command_invocation structure to encapsulate parameters for
all COMMAND_HANDLER routines. Rather than passing several arguments
to each successive subroutine, a single pointer may be passed around.
Changes the CMD_* macros to reference the new fields.
Updates run_command to create an instance and pass it to the handler.
Add additional macros to allow command handling to be migrated easily:
CMD_CTX, CMD_ARGC, and CMD_ARGV. Updates CMD_NAME to use CMD_ARGV.
In addition to making the remaining patches of this series cleaner,
this introduces easily sed-able symbols that could allow us to retire
these once the command handler infrastructure matures (i.e. pre-1.0).
No need to indirect from registered integers to pointers.
Just stash the pointers directly in the register struct,
and don't even bother registering.
This is a small code shrink, speeds register access just
a smidgeon, and gets rid of another rude exit() path.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The code is now much more explicit. It flushes every
N writes. For now flush every time, but tinkering with
the bridge FIFO size and how often we flush clearly
points in the direction of the Avalon write FIFO full
being the culprit.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Shifting by more than 32 is undefined for 32 bit integers according
to the C standard. Robust solution is conditional code.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
And move the rest of the vector_catch stuff into the C file;
it's not part of the module interface.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Also, switch integrity check over to the correct magic number,
and remove duplicate v4/v5 #define.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Have ARM11 register the "standard" ARM commands. For now, only
disassembly really works.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Rename the "armv4_5" command prefix to straight "arm" so it makes
more sense for newer cores. Add a simple compatibility script.
Make sure all the commands give the same "not an ARM" diagnostic
message (and fail properly) when called against non-ARM targets.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Fix bug noted by Øyvind: terminate the IR length autoscan when
the IR is too long, or otherwise broken.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Use size_t instead of uint32_t when specifying file sizes. Update all
consumers up through the layers to use size_t when required. These
changes should be safe, but the higher-levels will need to be updated
further to receive the intended benefits (i.e. large file support).
Add error checking for fileio_read and file_write. Previously, all
errors were being silently ignored, so this change might cause some
problems for some people in some cases. However, it gives us the chance
to handle any errors that do occur at higher-levels, rather than burying
our heads in the sand.
Uses unsigned type to pass line numbers.
Use uint64_t to pass sleep routines their milliseconds. Updates sleep
routines to use this type and improve whitespace.
Tweak "standard" ARM disassembler diagnostics to fail if the target
is not "an ARM" (vs. not "an ARMV4/5"), so it makes more sense for
cores inheriting this as the "generic" disassembler.
Also, to use the Thumb2 entry instead of the original Thumb entry.
This makes it work better for both newer cores (which support those
added instructions) and for BL and BLX instructions on older cores.
(Those instructions are 32-bits, which requires curious state-aware
code to go through a 16-bit decode interface...)
Plus minor cleanups, notably to have fewer exit paths and to make
sure they all return failure codes.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
They're really too big to inline, at least for code that's
not in any performance-critical loops.
Also move the associated string table to the rodata section.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The "improve inline binarybuffer helpers" mis-handled bytes
with the high bit set; treat them as unsigned, not signed.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Don't include it in more headers than necessary; just
use it in the few files that actually need it.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The ARRAY_SIZE macro was defined in several target files, so move it
to types.h.
This patch also removes two other identical macros: DIM (from jtag.h)
and asizeof (from arm11.h).
Eliminate redundant check that gets covered by using unsigned type.
Created to eliminate noise from subsequent patches, but this kind of
conversion will be beneficial in similar ways throughout the tree.
The container_of macro is useful as a general solution. It belongs
in types.h, rather than target.h where it was introduced. Requires
the offsetof macro, which comes from <stddef.h> (moved as well).
Add the 'nand verify' command to perform a dump and fake-write
simultaneously, checking the read bits against those generated by the
write process. Appropriate user documentation for this command has
been added to the user guide as well.
The algorithm presently makes a relatively naive comparison. Some chips
that use ECC may not verify correctly using this implementation, but the
new documentation provides details about this limitation.
In some cases, the FILEIO_NONE access mode may be useful as a parameter
to indicate that file access should be disabled. High-level routines can
use it to skip file access calls, as 'fileio_open' will fail presently
if called to open a file using this mode.
This patch eliminates duplicated code in the the NAND 'dump' and 'write'
by using the new static helper functions.
These changes also fix a possible memory leak in nand dump command, in
the case that the dump file failed to open.
Overall, the changes should be functionally equivalent, but the
resulting code will be easier to improve and extend further.
This patch provides helpers APIs that will eliminate duplicated code in
the the NAND 'dump' and 'write' commands by factoring their common code
into static helper functions. These helpers may be useful for creating
new commands, as shown in the final patch to 'verify' flash from a file.
Several previously unreported error conditions now generate messages and
propogate the return codes, such as when the file fails to open and bad
arguments are given. These changes will fix a possible memory leak in
nand dump command, in the case that the dump file failed to open.
Overall, the changes should be functionally equivalent, but the
resulting code will be easier to improve and extend consistently.
Rewrite buf_cmp to use memcpy for bulk of comparison. Add static
helper to perform comparison of trailing byte, which uses another
static helper to perform a maksed comparison. The masked comparison
helper is used by the buf_cmp_mask to simplify its loop.
Improve types to use void *, unsigned, and return bool.
Don't include "target.h" from more headers than necessary. This
avoids needless interdependencies and duplicated include paths.
Don't needlessly include it in source files, either.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Same deal: "register.h" got needlessly included all over the
place because of being in a few widely included headers.
So take it out of the header files which included it, and put
it in files which use it ... reduce needless interdependencies.
Also, don't need that extra "types.h" inclusion.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Lots of files still include it, often through needless
duplicate inclusion of "log.h"; sigh.
This cleans up the inclusion graph a bunch, so there are
fewer inclusion paths, but it doesn't change much otherwise.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Most files in the tree seem to have ended up including this,
and *quite* needlessly ... only code implementing or using
downloadable algorithms actually needs these declarations.
So take it out of the header files which included it, and put
it in files which use it ... reduce needless interdependencies.
Also: "algorithm.h" doesn't need to include "types.h" again;
it already comes from a different header.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Most files in the tree seem to have ended up including this,
and *quite* needlessly ... only code implementing or using
breakpoints actually needs these declarations.
So take it out of the header files which included it, and put
it in files which use it ... reduce needless interdependencies.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Now the ARM11 cores can use the renamed arm_checksum_memory()
and arm_blank_check_memory() routines ... do so.
Sanity checked with "flash erase_check" of both NOR banks on an
OMAP2420 ... the algorithm code dumped four lines of of "poll"
status after each of almost 520 blocks (yes, *very* annoying) but
gave plausible results after producing that spam.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Three changes: remove ARM11_HANDLER() in favor of normal structure
initialization syntax; fix goofy indentation in that structure; and
don't needlessly export arm11_register_commands(), it's only called
through that method table.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The arm7_9_checksum_memory() and arm7_9_blank_check_memory()
routines are not actually specific to the ARM7 and ARM9 core
generations ... they can work for any core which can run
algorithms using basic ARM (not Thumb) instructions.
Rename them; move the declarations to a more generic site;
likewise move the code (and tidy it a bit in the process).
NOTE: the blank_check() method falsely returned a success
status (0) on one error path, when the algorithm failed.
Fixed this bug.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Previously this flag was stored in "target_type", so that for example
if there were two ARM7TDMI targets in a scan chain, both would claim
to have been examined although only the first one actually had its
examine() method called.
Move this state to where it should have been in the first place, and
hide a method that didn't need exposure ... the flag is write-once.
Provide some doxygen. The examine() method is confusing, since it
isn't separating one-time setup from the after-each-reset stuff. And
the ARM7/ARM9 version is, somewhat undesirably, not leaving the debug
state alone after reset ... probably more of an issue for trace setup
than for watchpoints and breakpoints.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Removes unused arm_jtag_buf_* helpers from arm_jtag.[ch]. These could
reappear if patches are provided to conver the tree to use them, but
this code should not be in the master tree until that series is ready.
Purge an unused routine from the tree and remove a layering violation.
If this code is needed, it should reappear somwhere in src/jtag/,
where struct scan_field gets defined.
It's completely unused; the obnoxious "DANGER!!!" comments
don't even explain what it was doing (shorthand SVN magic).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This fixes an issue due to the new command handler syntax caused by the mw handler playing with the args pointer before
using the CMD_NAME macro. Fix is to move this call above the lines changing args.
Create src/openocd.h to hold declarations previously made internally
by src/main.c and src/server/server.c. This ensures all functions
are verified to be in-sync at compile time (rather than at link),
making it easier to track down bugs.
Changed some printf format strings..
[dbrownell@users.sourceforge.net: shrink lines, fix indents]
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Kick in ETM (and ETB) support for ARM11. Tested on OMAP 2420,
so update that configuration. (That's an ARM1136ejs, ETB,
OpenGL ES1.1, C55x DSP, etc.)
Also update the other ARM11 ETM + ETB targets in the tree
to set up these modules. (Not tested.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
These aren't desirable, given "standard" ETM support.
Also remove the now-unused arm11_find_target().
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
No point in having two identical examine methods for the
ARM7TDMI and ARM9TDMI drivers; move, rename, shrink, share.
Add a bit of doxygen; stop needlessly exporting a method.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Return NULL from etm_build_reg_cache() not ERROR_OK; and share
code on that fault path.
Let ETM code handle any tracking of its cache -- not callers.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This will enable reusing many common ARM utilities, in
particular the ETM and ETB support. The ARM11 support
can still be much simplified after this patch, though.
Note: none of those common utilities kick in yet...
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
We have too many different registers, and too many version and
context dependent interpretations, for this type of bitfield
management to be scalable.
(Anyone who really wants bitfield interpretation *can* do that
in Tcl code...)
There are ... quite a few copies of the same ARM dummy registers.
There should eventually be one copy; this many is craziness.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Remove the last external user of arm7_9_get_arch_pointers(), and
that annoying downcast utility. Add an is_arm7_9() predicate.
Stop returning specious success codes on various failure paths
in the ARM7/ARM9 commands which used that downcast utility.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The hello module provides the 'hello' command, printing a greetings
to the command console. It can grow to serve as pedagogical example
of services that OpenOCD developers should use: a runnable style guide.
The number of command arguments will always be 0 or more, so use
the right type in handlers. This has a cascading effect up through
the layers, but the new COMMAND_HANDLER macros prevented total chaos.
By using CALL_COMMAND_HANDLER, parameters can be reordered, added, or
even removed in inherited signatures, without requiring revisiting
all of the various call sites.
The FLASH_BANK_COMMAND_HANDLER provides an extended command handler
using the __COMMAND_HANDLER macro, whereby changing that macro is
sufficient to update flash handlers with the new signature. It also
enforces uniform style and scope when implementing this handler.
This patch adds new typedefs for command handler callback functions.
Users of this type signature were updated to use these new types.
It uses the new __COMMAND_HANDLER macro to prevent duplication.
The COMMAND_HANDLER and COMMAND_HELPER macros allow commands to be
defined in a manner that decouples them from the exact order and type of
their parameters. Once converted, incremental changes to the command
handler type can be addressed in incremental patches that do not need to
touch the entire tree.
These macros' implementation, __COMMAND_HANDLER, is used to define the
new command_handler_t type, and additional patches will use it to derive
new macros to define extended command types (e.g. flash, nand, pld).
The CALL_COMMAND_HANDLER provides a means of calling helpers or nested
handlers from withing a command handler.
This patch uses C99 varadic macro expansion. Please report compilers
that cannot handle this code.
The "remove (forward) declarations" patch goofed indentation on the
"cortexa8_target" struct; fix.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
To be more informative (and consistent with flash and pld trees), change
'device' parameter name to 'nand' in NAND source files. This change
eliminates confusing 'device->device->' instance from the code, and
it simplifies the forthcoming command handler patches.
ARM11 and newer cores include updated ETM modules. Recognize
their version codes and some key config differences. Sanity
checked on an OMAP2, with an ETM11RV r0p1 (ETMv3.1).
This still handles only scan chain 6, with at most 128 registers.
Newer cores (mostly, Cortex) will need to use the DAP instead.
Note that the newer ETM modules don't quite fit the quirky config
model of the older ones ... having more port widths is easy, but
the modes aren't the same. That still needs to change.
Fix a curious bug ... how did the register cache NOT get saved??
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Add the khz and speed_div functions to the parport interface driver.
Add the parport_toggling_time function that tells the parport driver
how long (in nanoseconds) it takes for the hardware to toggle TCK.
[dbrownell@users.sourceforge.net: tweak doc for clarity, mention
multimeter, and whitespace fixes]
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Now that nothing uses the old ETM handle any more, remove it.
Add minimal header tweaks, letting non-ARM7 and non-ARM9 cores
access ETM facilities.
Now ARM11 could support standard ETM (and ETB) access as soon as
it derives from "struct arm" ... its scanchain 6 is used access
the ETM, just like ARM7 and ARM9.
The Cortex parts (both M3 and A8) will need modified access methods
(via ETM init parameters), so they use the DAP. Our first A8 target
(OMAP3) needs that for both ETM and ETB, but the M3 ETM isn't very
useful without SWO trace support (it's painfully stripped down), so
that support won't be worth adding for a while.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Make ETM itself use the new toplevel ETM handle, instead
of the to-be-removed lower level one. As of this patch,
nothing should be using the old ARM7/ARM9-specific handle.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Make both useful ETM port drivers (etb, etm_dummy) use the new
toplevel ETM handle, instead of the to-be-removed lower level one.
Do the same for the "oocd-trace" prototype too; and fix its
error reporting paths: return failure codes, don't exit(), etc
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Make ARM7 and ARM9 cores use the new toplevel ETM handle to
trigger ETM setup, not the to-be-removed lower level one.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Rename "struct armv4_5_common_s" as "struct arm". It needs
a bit more work to be properly generic, and to move out of
this header, but it's the best start we have on that today.
Add and initialize an optional ETM pointer, since that will
be the first thing that gets generalized.
The intent being: all ARMs should eventually derive from
this "struct arm", so they can reuse the current ETM logic.
(And later, more.) Currently the ARM cores that *don't* so
derive are only ARMv7-M (and thus Cortex-M3) and ARM11.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Eliminate duplicate code for linking commands into a list.
Adds a check to ensure the command does not already exist;
if it does, return that one instead of creating a duplicate.
Add help for commands regardless of whether a handler is involved.
With this, all sorts of new commands can be found in 'help' text.
Hopefully, all of them have been documented....
Sadly, the lsort function appears to handle nested lists poorly, such
that sub-commands do not group with their parents.
The command_name function returns a malloced string for a given
command and its parents. This can be used to display a message
to the user, but it is used internally to handle registration
and syntax errors. This helps permit arbitrary command nesting.
Add 'const' keyword to 'char *' parameters to allow command handlers to
pass constant string arguments. These changes allow the 'args' command
handler to be changed to 'const' in a subsequent patch.
Subsequent patches expect all command handlers to use a uniform
parameter naming scheme. In the entire tree, these two files used
standard 'argv' instead of our non-standard 'args'. This patch opts
to reduces the noise required to unify the command handlers, using
dominant 'args' form.
A future patch may be used to convert us back to the standard argv, but
that requires coordination with all developers to minimize disruptions.
Separates various groups of files to be built in logical succession.
In each layer, the core module (target.c, nand.c, etc.) is built _after_
their helper modules (e.g. image.c, nand_ecc.c) but _before_ any of
their drivers (e.g. arm966e.c, mx3_nand.c).
This allows problems introduced at the bottom of the stack to result
in build failures as soon as possible, as the helpers and core should
wrap portions of them.
Various cleanups of ETM related code.
- Saner error return paths
- Simplify arm7_9 init ... no need for extra zeroing!
- Shrink some lines
- Tweak some diagnostics
- Use shorter name for ETM struct type.
- Don't exit()
and similar. The diagnostics look forward to having
this ETM code work with more than just ARM7/ARM9.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The "ARM720 uses the new inheritance/nesting scheme" patch
wrongly scrubbed a calloc() from arm720t_target_create().
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Start switching MMU handling over to a more sensible scheme.
Having an mmu() method enables MMU-aware behaviors. Not having
one kicks in simpler ones, with no distinction between virtual
and physical addresses.
Currently only a handful of targets have methods to read/write
physical memory: just arm720, arm920, and arm926. They should
all initialize OK now, but the arm*20 parts don't do the "extra"
stuff arm926 does (which should arguably be target-generic).
Also simplify how target_init() loops over all targets by making
it be a normal "for" loop, instead of scattering its three parts
to the four winds.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
First cut of these commands. Øyvind tinkered a bit with
the number parsing to bring it up to speed + rebased it.
Ready for testing.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
- improve some names -- a "default" prefix is not descriptive
- add doxygen @todo entries for some issues
- avr8 isn't ever going to need those MMU hooks
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Contrary to my previous assessment, some opportunities to remove forward
declarations were overlooked. Remove them by moving the definitions
of the command registration and interface structure to the end of files.
Remove useless forward declarations.
Moves command registrations to end of files.
Moves flash structure definitions to end of files.
Signed-off-by: Zachary T Welch <zw@superlucidity.net>
Remove useless forward declarations.
Moves command registrations to end of files.
Moves flash structure definitions to end of files.
Signed-off-by: Zachary T Welch <zw@superlucidity.net>
Remove useless forward declarations.
Moves command registrations to end of files.
Moves flash structure definitions to end of files.
Signed-off-by: Zachary T Welch <zw@superlucidity.net>
Remove useless forward declarations.
Moves command registration to end of file.
Moves flash structure definitions to end of files.
Changes a few references to global flash structure to local refs.
Signed-off-by: Zachary T Welch <zw@superlucidity.net>
Remove useless forward declarations.
Moves command registrations to end of files.
Moves flash structure definitions to end of files.
Signed-off-by: Zachary T Welch <zw@superlucidity.net>
Remove useless forward declarations.
Moves command registration to end of files.
Moves flash structure definition to end of files.
Signed-off-by: Zachary T Welch <zw@superlucidity.net>
Remove useless forward declarations.
Moves command registration to end of file.
Moves flash structure definition to end of file.
Signed-off-by: Zachary T Welch <zw@superlucidity.net>
This patch introduced a bug preventing flash writes from working
on Cortex-M3 targets like the STM32. Moreover, it's the wrong
approach for handling no-MMU targets.
The right way to handle no-MMU targets is to provide accessors
for physical addresses, and use them everywhere; and any code
which tries to work with virtual-to-physical mappings should use
a identity mapping (which can be defaulted).
And ... we can tell if a target has an MMU by seeing if it's
got an mmu() method. No such methood means no MMU.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
It's been about a year since these were deprecated and, in most
cases, removed. There's no point in carrying that documentation,
or backwards compatibility for "jtag_device" and "jtag_speed",
around forever. (Or a few remnants of obsolete code...)
Removed a few obsolete uses of "jtag_speed":
- The Calao stuff hasn't worked since July 2008. (Those Atmel
targets need to work with a 32KHz core clock after reset until
board-specific init-reset code sets up the PLL and enables a
faster JTAg clock.)
- Parport speed controls don't actually work (tops out at about
1 MHz on typical HW).
- In general, speed controls need to live in board.cfg files (or
sometimes target.cfg files), not interface.cfg ...
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Removes 'extern' keywords from function prototypes in the flash headers.
Wraps long lines to fit into 80 columns.
Adds multiple inclusion protection for s3c2xx_nand.h.
Removes the 'extern' keyword from function declarations.
Wraps long prototypes to fit into 80 columns.
Fixes documentation for jtag_tap_s::{,has}idcode fields.
The "$ocd_HOSTOS" variable was wrongly documented. Fix its
documentation, and its value on Linux.
Shrink a few of the too-long lines.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Add comments (Doxygen and normal), remove unused code,
shrink some overlong lines. Get rid of a forward decl.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This patch changes the duration_* API in several ways. First, it
updates the API to use better names. Second, string formatting has
been removed from the API (with its associated malloc). Finally, a
new function added to convert the time into seconds, which can be
used (or formatted) by the caller. This eliminates hidden calls to
malloc that require associated calls to free().
This patch also removes the useless extern keyword from prototypes,
and it eliminates the duration_t typedef (use 'struct duration').
These API also allows proper error checking, as it is possible for
gettimeofday to fail in certain circumstances.
The consumers have all been chased to use this new API as well, as
there were relatively few cases doing this type of measurement.
In most cases, the code performs additional checks for errors, but
the calling code looks much cleaner in every case.
Reduces confusion about location of associated routines and
reduces clutter in the arm11 header.
Removes extra whitespace around the lines touched by these changes.
Make several functions be static. Shrink some of the overlong
lines. Use pure tab indents in some places that mixed in spaces.
This gives a minor object code shrink (about 2% on amd64).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Resolve serious bug inserted by the "target: require working
area for physical/virtual addresses to be specified" patch.
It forced use of (invalid) virtual addresses when the MMU
was disabled, and vice versa.
Observed to break at least Cortex-M3, ARM926, ARM7TDMI whenever
work areas are used, such as during bulk writes to flash, DDR2,
SRAM, and so on.
Also, fix overlong lines and whitespace goofs.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Move various embedded target structs to the beginnings of
their containers ... pretty much the way C++ or Obj-C
would for single inheritance.
This shrinks code that accesses those embedded structs by
letting common offsets use smaller instructions. Sample
before/after sizes (on amd64):
17181 312 0 17493 4455 arm920t.o
16810 312 0 17122 42e2 arm920t.o
Where the "after" is the smaller number, with this patch
over the ones leveraging that embedding knowledge.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Remove most remaining uses of target->arch_info from ARM
infrastructure, where it hasn't already been updated.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Use target_to_armv7a() etc, replacing needless pointer traversals.
Stop using X->arch_info scheme in most ARMv7-A and Cortex-A8 code.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Use target_to_arm7_9(), replacing needless pointer traversals.
Also: remove now-useless contents of arm7tdmi struct; it's
almost ready to be removed.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Use target_to_arm720(), replacing needless pointer traversals
and simplifying a bunch of nasty code. Stop setting arch_info
for arm720 type parts, it's not used any longer.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Use target_to_xscale(), replacing needless pointer traversals
and simplifying a bunch of code.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Replace needless pointer traversals and simplify. Also remove most
remaining contents from arm9tdmi struct; it's almost removable.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Use target_to_arm926(), replacing needless pointer traversals
and simplifying a bunch of code.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Use target_to_arm920(), replacing needless pointer traversals
and simplifying. Stop setting arm9tdmi->arch_info for arm920
type parts, it's not used any longer.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Use new target_to_cm3() and target_to_armv7m() inlines,
instead of a series of x->arch_info conversions. Remove
arch_info, since nothing uses it.
Also fix an omission: the Cortex-M3 commands didn't verify
that they were operating on that kind of target. Add comment
about the ARMv7M version of that omission.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Provide a cleaner way to handle single inheritance of targets
in C, using the same model Linux does: structs containing other
structs, un-nested via calls to a "container_of()" macro that
are packaged in typesafe inline functions.
Targets already use this containment idiom, but make it much
more complicated because they un-nest using embedded "void *"
pointers ... in chains of up to five per target, which is all
pure needless complication. (Example: arm92x core, arm9tdmi,
arm7_9, armv4_5 ... on top of the base "target" class.)
Applying this scheme consistently simplifies things, and gets
rid of many error-prone untyped pointers. It won't change any
part of the type model though -- it just simplifies things.
(And facilitates more cleanup later on.)
Rule of thumb: where there's an X->arch_info void* pointer,
access to that pointer can and should be removed. It may be
convenient to set up pointers to some of the embedded structs;
and shrink their current "*_common" names (annoyingly long).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The forward decls are just code clutter; remove them, by moving
their references after definitions. This is another file which
never needed even one internal forward declaration.
Also shrink a few overly-long lines with function declarations
or definitions; get rid of arm7tdmi_register_commands(), it's
not needed (just delegated); minor whitespace declutter.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Unneeded exports cause confusion about the module interfaces.
Make all functions static. Add a short header comment.
The forward decls are just code clutter; remove them, by moving
their references after definitions. This is another file which
never needed even one internal forward declaration.
Remove unneeded indirection for the write_memory() method. Make
a table static, remove a can't-happen case with nasty exit().
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Unneeded exports cause confusion about the module interfaces.
Make most functions static.
The forward decls are just code clutter; remove them, by moving
their references after definitions. This is another file which
never needed even one internal forward declaration.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The forward decls are just code clutter; remove them, by moving
their references after definitions. This is another file which
never needed even one internal forward declaration.
Also shrink a few overly-long lines with function declarations
or definitions.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Unneeded exports cause confusion about the module interfaces.
Make most functions static.
The forward decls are just code clutter; remove them, by moving
their references after definitions. This is another file which
never needed even one internal forward declaration.
Also remove needless arm966e_init_target(), in favor of the
arm9tdmi routine to which it delegates its work.
This saved over 100 bytes of code on x86_32.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
An init_target() wrapper isn't needed, and target_create()
can shrink a bit. Add a header comment and some doxygen.
Remove arm926ejs_catch_broken_irscan() which has been a NOP
for quite a few months now, and in any case duplicates logic
in the JTAG core to validate IR capture data. But force the
capture mask to 0x0f, so those tests are most effective.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Unneeded exports cause confusion about the module interfaces.
Make most functions static. Add a short header comment.
The forward decls are just code clutter; remove them, by moving
their references after definitions. This is another file which
never needed even one internal forward declaration.
This saved almost 900 bytes of code on x86_32; it seems the
compiler can leverage its knowledge that these functions are
not called from the outside world...
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This eliminates redundant code for parsing and retreiving the bank
specified from a script command argument. This patch was written to
replace existing functionality; however, the parsing logic can be
updated later to allow flash commands to accept bank names as well as
their numbers.
This helper eliminates significant amount of redundant code in command
handler functions throughout the system. It wraps the lower-level
parse_* macros to implement a policy for reporting parse errors to the
active command context (cmd_ctx). If errors do occur, this macro causes
the calling function to abort with the proper return code.
The arm920t has a concept of read modify write cycles
that may have to be represented in the mrcmcr interface
eventually.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Fail watchpoint_add() if it's the same address but the
parameters are different ... don't just assume having
the same address means the same watchpoint! (Note that
overlapping watchpoints aren't detected...)
Handle unrecognized return codes more sanely; don't exit()!
And describe command params right.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Expose most DWT registers via Tcl; there are a few more, but
those are mostly for profiling along with the ITM. Having
this set available enables operations which aren't possible
with just the standard watchpoint operations.
The cycle counter may be interesting. Turn it on after reset
by setting the LSB of the dwt_ctrl register, and it counts
CPU clocks. You can program the comparator 0 watchpoint to
trigger on a given cycle count, rather than a data address.
Likewise, comparator 1 may be able to match data values given
address matches from one or two other comparators. (Not all
hardware supports this capability though; try it. That is
something the standard watchpoint methods should eventually
handle, for the single address case.)
Minor cleanup: remove needless functional indirection for
exposing the v7m architctural registers.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
There's no reason to read which interrupts are enabled from
the NVIC; that state isn't used. Plus, it's highly dynamic
since firmware can change it at any time; remove the support
for those state records.
Remove duplicate definition of DWT_CTRL address; shrink a line.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Fix the watchpoint error checks, and do them in add(), not later
in set() when it's mostly too late. Support the full range of
watchpoint sizes (1 to 32K bytes each), and check alignments.
Minor cleanup of DWT access: shrink lines, use "+" for address
calculations, comment a few issues. Add debug message reporting
DWT capabilities, matching the message for FBP, and some minor
code and spec review comments.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Add Doxygen for the exported ARMv7-M interfaces.
Make the non-exported stuff static. Remove functions and
data which are now observably unused.
Add comment about a small speedup that the run_algorithm()
logic could use. Shrink a few too-long lines.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
improve default target->read/write_phys_memory, produce
more sensible error messages if the mmu interface
functions have not been implemented yet vs. will
not be implemented(e.g. cortex m3).
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
The quit entry point was not being invoked. Just a source
of confusion at this point. XScale ran 100x reset upon
quit, but that code made no sense, wasn't commented
and never invoke.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Previous patch somehow made GCC lose some of its cookies;
work around, zero-init that struct.
Clean up code from the previous patch.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
To support breakpoints, flush data cache line and invalidate
instruction cache when 4 and 2 byte words are written.
The previous code was trying to write directly to the physical
memory, which was buggy and had a number of other situations
that were not handled.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Fixed bug: if virtual address for working memory was not specified
and MMU was enabled, then address 0 would be used.
Require working address to be specified for both MMU enabled
and disabled case.
For some completely inexplicable reason this fixes the regression
in svn 2646 for flash write in arm926ejs target. The logs showed
that MMU was disabled in the case below:
https://lists.berlios.de/pipermail/openocd-development/2009-November/011882.html
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This change is necessary to debug AT91SAM9260 on my PC with a
FT2232H dongle.
Signed-off-by: Dimitar Dimitrov <dinuxbg@gmail.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Just use the array of names we're given, ignoring indices.
The "reserved means don't use" patch missed that change.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
I'm suspecting this code can never have worked, since the
original commit (svn #335) in early 2008.
Fix is just copy/paste from another (working) function.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Implement XSVF support for detailed state path transitions,
by collecting sequences of XSTATE transitions into paths
and then calling pathmove().
It seems that the Xilinx tools want to force state-by-state
transitions instead of relying on the standardized SVF paths.
Like maybe there are XSVF tools not implementing SVF paths,
which are all that we support using svf_statemove().
So from IRPAUSE, instead of just issuing "XSTATE DRPAUSE"
they will issue XSTATES for each intermediate state: first
IREXIT2, then IRUPDATE, DRSELECT, DRCAPTURE, DREXIT1, and
finally DRPAUSE. This works now.
Handling of paths that go *through* reset is a trifle dodgey,
but it should be safe.
Tested-by: Wookey <wookey@wookware.org>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Unneeded exports cause confusion about the module interfaces.
Make most functions static, and fix some line-too-long issues.
Delete some now-obviously-unused code.
The forward decls are just code clutter; move their references
later, after the normal declarations. (Or vice versa.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Unneeded exports cause confusion about the module interfaces.
Only the Feroceon code builds on this, so only routines it
reuses should be public.. Make most remaining functions
static, and fix some of the line-too-long issues.
The forward decls are just code clutter; move their references
later, after the normal declarations. Turns out we don't need
even one forward declaration in this file.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The Hex parser uses a fixed number of sections. When the
number of sections in the file is greater than that, the
stack get corrupted and a CHECKSUM ERROR is detected
which is very confusing.
This checks the number of sections read, and increases
IMAGE_MAX_SECTIONS so it works on my file.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Only type 1 branch instruction has a condition code, not type 2.
Currently they're both tagged with ARM_B which doesn't allow for the
distinction.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
A Thumb BLX instruction is branching to ARM code, and therefore the
first 2 bits of the target address must be cleared.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This patch includes partial support for these new JTAG adapters.
More complete support will require updates to the libftdi code,
for EEPROM access.
[dbrownell@users.sourceforge.net: fix whitespace, linelen, etc ]
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Currently, OpenOCD is always caching the PC value without the T bit.
This means that assignment to the PC register must clear that bit and set
the processor state to Thumb when it is set. And when the PC register
value is transferred to another register or stored into memory then
the T bit must be restored.
Discussion: It is arguable if OpenOCd should have preserved the original
PC value which would have greatly simplified this code. The processor
state could then be obtained simply by getting at bit 0 of the PC. This
however would require special handling elsewhere instead since the T bit
is not always relevant (like when PC is used with ALU insns or as an index
with some addressing modes). It is unclear which way would be simpler in
the end.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Whenever an unconditional branch with the H bits set to 0b10 is met, the
offset must be combined with the offset from the following opcode and not
ignored like it is now.
A comment in evaluate_b_bl_blx_thumb() suggests that the Thumb2 decoder
would be a simpler solution. That might be true when single-stepping of
Thumb2 code is implemented. But for now this appears to be the simplest
solution to fix Thumb1 support.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Calling it first with every opcodes and then testing if the opcode
was indeed a branch instruction is wasteful and rather strange.
If ever thumb_pass_branch_condition() has side effects (say, like
printing a debugging traces) then the result would be garbage for most
Thumb instructions which have no condition code.
While at it, let's make the nearby code more readable by reducing some of
the redundant brace noise and reworking the error handling construct.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Make the "dap info" output more comprehensible:
- Don't show CIDs unless they're incorrect (only four bits matter)
- For CoreSight parts, interpret the part type
- Interpret the part number
- Show all five PID bytes together
- Other minor cleanups
Also some whitespace fixes, and shrink a few overlong source lines.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Ignore leading '0' characters on hex strings. For example a bit
pattern consisting of 6 bits could be written as 3f, 03f or 003f and
so on.
Signed-off-by: Michael Roth <mroth@nessie.de>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This patch adds basic autoprobing support for the JTAG scan chains
which cooperate. To use, you can invoke OpenOCD with just:
- interface spec: "-f interface/...cfg"
- possibly with "-c 'reset_config ...'" for SRST/TRST
- possibly with "-c 'jtag_khz ...'" for the JTAG clock
Then set up config files matching the reported TAPs. It doesn't
declare targets ... just TAPs. So facilities above the JTAG and
SVF/XSVF levels won't be available without a real config; this is
almost purely a way to generate diagnostics.
Autoprobe was successful with most boards I tested, except ones
incorporating C55x DSPs (which don't cooperate with this scheme
for IR length autodetection). Here's what one multi-TAP chip
reported, with the "Warn:" prefixes removed:
clock speed 500 kHz
There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
AUTO auto0.tap - use "... -irlen 4"
AUTO auto1.tap - use "... -irlen 4"
AUTO auto2.tap - use "... -irlen 6"
no gdb ports allocated as no target has been specified
The patch tweaks IR setup a bit, so we can represent TAPs with
undeclared IR length.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Stop allocating three bytes per IR bit, and cope somewhat better
with IR lengths over 32 bits.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Remove needless debug handler state.
- "handler_installed" became wrong as soon as the second TRST+SRST
reset was issued ... so the handler was never reloaded after the
reset removed it from the mini-icache.
This fixes the bug where subsequent resets fail on PXA255 (if the
first one even worked, which is uncommon). Other XScale chips
would have problems too; PXA270 seems to have, IXP425 maybe not.
- "handler_running" was never tested; it's pointless.
Plus a related bugfix: invalidate OpenOCD's ARM register cache on reset.
It was no more valid than the XScale's mini-icache. (Though ... such
invalidations might be better done in "SRST asserted" callbacks.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Bit 5 shouldn't be used. Remove all support for modifying it.
Matches the exception vector table, of course ... more than one
bootloader uses that non-vector to help distinguish valid boot
images from random garbage in flash.
Some cosmetic cleanup, and switch to a single table mapping
between state names and symbols (vs two routines which only
share that state with difficulty).
Get rid of TAP_NUM_STATES, and some related knowledge about
how TAP numbers are assigned. Later on, this will help us
get rid of more such hardwired knowlege.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
- Use the name mappings all the other code uses:
+ name-to-state ... needed to add one special case
+ state-to-name
- Improve various diagnostics:
+ don't complain about a "valid" state when the issue
is actually that it must be "stable"
+ say which command was affected
- Misc:
+ make more private data and code be static
+ use public DIM() not private dimof()
+ shorten the affected lines
Re the mappings, this means we're more generous in inputs we
accept, since case won't matter. Also our output diagnostics
will be a smidgeon more informative, saying "RUN/IDLE" not
just "IDLE" (emphasizing that there can be side effects).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The wrong variable (pc instead of r0) was used. Furthermore, someone
did cover this error by stupidly silencing the compiler warning that
occurred before a dummy void reference to r0 was added to the code.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
When dumping over 100 registers (as on most ARM9 + ETM cores),
aid readability by splitting them into logical groups.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The register names are perversely not documented as zero-indexed,
so rename them to match that convention. Also switch to lowercase
suffixes and infix numbering, matching ETB and EmbeddedICE usage.
Update docs to be a bit more accurate, especially regarding what
the "trigger" event can cause; and to split the issues into a few
more paragraphs, for clarity.
Make "configure" helptext point out that "oocd_trace" is prototype
hardware, not anything "real".
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
XSVF improvements:
- Layer parts of XSVF directly over SVF, calling svf_add_statemove()
instead of expecting jtag_add_statemove() to conform to the SVF/XSVF
requirements (which it doesn't).
This should improve XSTATE handling a lot; it removes most users of
jtag_add_statemove(), and the comments about how it should really do
what svf_add_statemove() does.
- Update XSTATE logic to be a closer match to the XSVF spec. The main
open issue here is (still) that this implementation doesn't know how
to build and submit paths from single-state transitions ... but now
it will report that error case.
- Update the User's Guide to mention the two utility scripts for
working with XSVF, and to mention the five extension opcodes.
Handling of state transition paths is, overall, still a mess. I think
they should all be specified as paths not unlike SVF uses, and compiled
to the bitstrings later ... so that we can actually make sense of the
paths. (And see the extra clocks, detours through RUN, etc.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Don't add extra TCK in current state; exit from RESET had four extras.
Only IDLE --> IDLE needs such an extra clock. (At least one TCK must
be issued.)
Allow entry to RESET; SVF allows it, so must we (despite those entries
being commented out of the statemove table).
When entering RESET, always use TLR ... we might end up with extra clocks
in reset that way, which is harmless, but we'll never end up in any other
state than RESET, which is useful paranoia.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
As decided a while back, this isn't a transition we want to chance.
Whenever someone wants to got to RESET, force it.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
SVF: comment the predefined/default paths; make them static const
SVF, XSVF: whitespace fixes, mostly so copyrights display sanely
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
After reading a bit further, it appears that ws2_32 (Windows Sockets 2)
is included in all versions of Windows and backwards compatible with
wsock32, at least according to
http://msdn.microsoft.com/en-us/library/ms740673%28VS.85%29.aspx.
Only Win95 seems to require a manual installation; is not a big deal.
So I think we can drop this whole business of detecting 64 bit MinGW and
just use -lws2_32 for all MinGW platforms.
Compilation on cygwin, using gcc v3 with option -mno-cygwin,
currently produces a large number of the following warnings:
warning: `gnu_printf' is an unrecognized format function type
These have been introduced with the recent MinGW GNU C99 printf
compliance patch, as gnu_printf was only introduced with gcc v4.4
and is not recognized with earlier versions.
The attached fix adds gcc version detection to the previous patch
to avoid the problem.
Passing "--std=gun99" is unfortunately not sufficient to make current
MinGW compilers conform with respect to checking printf format strings.
(The C runtime seems not to have problems.)
Fix by using a "gnu_printf" format specifier not "printf".
Use JIM_WIDE_MODIFIER for the sscanf format, and apply it for MINGW32 as
well as other Windows environments. (Microsoft doesn't conform to the
C99 standard, and uses "%I64d" not "%lld" for "long long".)
NB: __MINGW32__ should work on both w32 and w64,.
Generate a C struct with the data, and use that, instead of an
assembly language file. The assembly language causes issues on
Darwin and MS-Windows, which don't necessarily use GNU AS; or
if they do, don't necessarily use its ELF syntax.
It's also better in two other ways: fewer global symbols; and
the init-time size check gets optimized away at compile time.
(Unless it fails, in which case bigger chunks of the file vanish.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Based on some patches from <redirect.slash.nil@gmail.com>
for preliminary Win64 compilation. More such updates are
needed, but they need work. Compile tested on 64 and 32 bit
Linuxes, and Cygwin.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This makes the documentation a closer match to "help" output:
- "pathmove" somehow was not documented in the User's Guide
- "jtag_nsrst_assert_width" and "jtag_ntrst_assert_width"
are new; both needed descriptions.
- Removed two undocumented and fairly useless script mechanisms:
* production/production_info/production_test ... using it,
requires replacing everything; so having it adds no value.
* cpu ... way out of date; hopeless to keep that current
Note that anyone using that "production" stuff already defines
their own procedures, and can keep using them with no change.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The LE check is obviously buggy (as easily triggered during some
testing), but I didn't audit the rest of the cases.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Cleanup comments and layout/whitespace in the TMS tables.
Table contents stayed the same (ignoring whitespace).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Resolve a "FIX" comment; yes that was superfluous given that the
JTAG core does that check by default. It was also buggy since it
wrote to a stack frame that went away before the write happened!!
Other fixes: remove pointless malloc(); zero-init scan_field_t
values wherever they appear; whitespace scrub; spelling fix.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Load the XScale debug handler from the read-only data section
instead of from a separate file that can get lost or garbaged.
This eliminates installation and versioning issues, and also
speeds up reset handling a bit.
Plus some minor bits of cleanup related to loading that handler:
comments about just what this handler does, and check fault codes
while writing it into the mini-icache.
The only behavioral changes should be cleaner failure modes after
errors during handler loading, and being a bit faster.
NOTE: presumes GNU assembly syntax, with ".incbin"; and ELF,
because of the syntax of the ".size" directive.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Streamline/shrink some needless JTAG stuff:
- Use #defines for the JTAG instructions; they can't ever change
- Remove an unused (!) shadow of tap->ir_length
- Stop using a copy of target->tap
- Don't bother saving the variant after sanity checking ir_length
Also, make target_create() work as on other targets: build the
register cache later, making init_target() no longer be a NOP.
Handle malloc failure; remove a comment that was obsoleted by the
not-so-new target syntax.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Remove unused and deprecated (in the arch spec) mode for loading
code into the *main* icache (vs the "mini" icache). Disable some
extremely noisy (and rarely useful) low-level debug messages
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Declare almost everything as static.
Move stuff to remove most forward references.
Remove most forward declarations.
Warn if the unimplemented register functions get called.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Just fill out the rest of the cache line with NOPs; don't change
the record of how much data we consumed. Otherwise the count of
how much data is left can roll over from positive to negative
("VERY positive") and skip the loop termination of zero.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Add a header comment referencing useful XScale specs.
Make most data static, and the tables readonly.
Scrub extra blank lines.
Return fault codes from one routine.
Remove a needless NOP methood.
(BUGFIX) When we update R0, mark R0 as dirty/valid ... not R15/PC!
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
We added two overridable procedures; document them, and the
two jtag arp_* operations they necessarily expose.
Update the comment about the jtag_init_reset() routine; it's
been obsolete for as long as it's had SRST support.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This abstracts the "jtag arp_init-reset" call into a method
called from OpenOCD startup and reset processing.
Platforms which have different requirements for how such hard
resets must be performed can now override "init_reset" instead
of needing to rebuild custom hacked versions of the server.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Observed:
openocd: core.c:318: jtag_checks: Assertion `jtag_trst == 0' failed.
The issue was that nothing disabled background polling during calls
from the TCL shell to "jtag_reset 1 1". Fix by moving the existing
poll-disable mechanism to the JTAG layer where it belongs, and then
augmenting it to always pay attention to TRST and SRST.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Among other things this causes startup errors to kick in the
fallback "reset harder" logic during server startup. Comments
are also updated a bit, explaining what the various error paths
signify (in at least my observation).
There's one class of validation error that we can still plausibly
ignore: when wrong IDCODE values are observed.
This change seems to have helped make an OMAP5912 behave much
more reliably. There's still some post-reset flakiness, but
it's unrelated to scan verification.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Also, talk about "mainline" not "trunk".
The release.txt and release.sh files need more updates.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2825 b42882b7-edfa-0310-969c-e2dbd0fdcd60
At least some FT2232 based adapters don't necessarily come up
in the expected state, with SRST and TRST disabled. Since
other adapters could suffer the same problem, let's avoid
needing to patch every driver and just force *all* adapters
to initialize those values properly at server startup.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2824 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Instead of just assuming all IDCODE-deprived TAPs violate the
JTAG spec (they don't!), just require TAPs with such problems
to be declared with proper ircapture/irmask values. Example,
with mask and value of zero.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2823 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- revert to previous default: don't talk JTAG during SRST
- add "srst_nogates" flag, the converse of "srst_gates_jtag"
- with no args, display the current configuration
And update the User's Guide text with bullet lists to be a bit more clear.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2818 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- The guess-rev.sh script is now a tweaked version of "setlocalversion" as
seen in Linux, U-Boot, and various other projects. When it finds source
control support (git, hg, svn) it uses IDs from there. Else (specific
to this project) it reports itself as "-snapshot", e.g. from gitweb.
I verified this new "guess-rev.sh" script runs under Cygwin.
- Also update the generic version strings to be like "0.3.0-dev" (during
development) instead of the very long "0.3.0-in-development". These also
show up in the PDF docs. For better tracking, we might eventually change
these strings to include the version IDs too.
- Change the startup banner version strings so they include the guess-rev
output. Development and release versions with GIT will be like
Open On-Chip Debugger 0.3.0-dev-00282-g7191a4f-dirty (2009-10-05-20:57)
Open On-Chip Debugger 0.3.0 (2009-10-05-20:57)
instead of the previous SVN-specific (even when using git-svn!)
Open On-Chip Debugger 0.3.0-in-development (2009-10-05-01:39) svn:exported
Open On-Chip Debugger 0.3.0 (2009-10-05-01:39) Release
git-svn-id: svn://svn.berlios.de/openocd/trunk@2809 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Bugfix the error message so it shows the disliked value, and add
a debug message showing each TAP's IR capture value, all N bits.
This just changes diagnostics ... it still ignores the parameters
given to us at TAP declaration time.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2801 b42882b7-edfa-0310-969c-e2dbd0fdcd60
The model is that this fires after scanchain verification, when it's
safe to call "jtag tapenable $TAPNAME". So it will fire as part of
non-error paths of "init" and "reset" command processing. However it
will *NOT* trigger during "jtag_reset" processing, which skips all
scan chain verification, or after verification errors.
ALSO:
- switch DaVinci chips to use this new mechanism
- log TAP activation/deactivation, since their IDCODEs aren't verified
- unify "enum jtag_event" scripted event notifications
- remove duplicative JTAG_TAP_EVENT_POST_RESET
git-svn-id: svn://svn.berlios.de/openocd/trunk@2800 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- don't needlessly export this function
- handle "case 0" debug method-of-entry better (silent by default)
The "case 0" is a valid debug entry mode so it doesn't deserve the
warning int now gets. But it probably means that OpenOCD confused
itself somehow; or that it confused the ARM9EJS target.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2799 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- ETB
* report _actual_ hardware status, not just expected status
* add a missing diagnostic on a potential ETB setup error
* prefix any diagnostics with "ETB"
- ETM
* make "etm status" show ETM hardware status too, instead of
just traceport status (which previously was fake, sigh)
- Docs
* flesh out "etm tracemode" docs a bit
* clarify "etm status" ... previously it was traceport status
* explain "etm trigger_percent" as a *traceport* option
ETM+ETB tracing still isn't behaving, but now I can see that part of
the reason is that the ETB turns itself off almost immediately after
being enabled, and before collecting any data.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2790 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Don't issue needless JTAG resets ... only do them after
errors. Normal exit now leaves every TAP in BYPASS.
- Fix an unlikely memory leak on one fault path.
- Remove the oddball limitation that invalid capture LSBs
trigger errors only for TAPs that support IDCODE.
Re the JTAG reset: there are too many of them, and they can
(and do!) change system state. So the needless ones should
get removed. This one was especially pointless.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2777 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Commands were supposed to have been "arm11 memwrite ..."
not "memwrite ..."
- Get rid of obfuscatory macros
- Re-alphabetize
- Add docs for "arm11 vcr"
git-svn-id: svn://svn.berlios.de/openocd/trunk@2776 b42882b7-edfa-0310-969c-e2dbd0fdcd60
When the OpenOCD server starts up it records its state as TAP_RESET,
even though it could be anything. Then when it starts to examine
the scan chain, it calls jtag_add_tlr() which sees it doesn't have
any work to do, and so it does nothing. This can make the next
operations fail because they start from the wrong TAP state...
Instead of caring about the current recorded state, always enter
TAP_RESET by forcing five clocks with TMS high.
(NOTE: it seems most other JTAG adapter drivers have this same bug.)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2763 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Change the handling of the "-ircapture" and "-irmask" parameters
to be slightly more sensible, given that the JTAG spec describes
what is required, and that we already require that conformance in
one place. IR scan returns some bitstring with LSBs "01".
- First, provide and use default values that satisfy the IEEE spec.
Existing TAP configs will override the defaults, but those parms
are no longer required.
- Second, warn if any TAP gets set up to violate the JTAG spec.
It's likely a bug, but maybe not; else this should be an error.
Improve the related diagnostics to say which TAP is affected.
And associated minor fixes/cleanups to comments and diagnostics.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2758 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Ready for discussion and tiny patches that tries out this scheme.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2755 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Added gdb_sync feature that allows GDB to sync up to target state.
Issue "monitor gdb_sync" and the next stepi, will return immediately
with updated register values to GDB.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2754 b42882b7-edfa-0310-969c-e2dbd0fdcd60
make sure that when there are two or more targets, their
various pre/post event reports are correctly ordered.
Previously, only the first target always saw its "pre"
method before SRST was asserted or deasserted.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2753 b42882b7-edfa-0310-969c-e2dbd0fdcd60
only expose the registers which are actually present. They
could be missing for two basic reasons:
- This version might not support them at all; e.g. ETMv1.1
doesn't have some control/status registers. (My sample of
ARM9 boards shows all with ETMv1.3 support, FWIW.)
- The configuration on this chip may not populate as many
registers as possible; e.g. only two data value comparators
instead of eight.
Includes a bugfix in the "etm info" command: only one of the
two registers is missing on older silicon, so show the first
one before bailing.
Update ETM usage docs to explain that those registers need to be
written to configure what is traced, and that some ETM configs
are not yet handled. Also, give some examples of the kinds of
constrained trace which could be arranged.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2752 b42882b7-edfa-0310-969c-e2dbd0fdcd60
system, removes 20 non-existent registers ... but still includes
over 45 (!) ETM registers which don't even exist there ...
- Integrate the various tables to get one struct per register
- Get rid of needless per-register dynamic allocation
- Double check list of registers:
* Remove sixteen (!) non-registers for data comparators
* Remove four registers that imply newer ETM than we support
* Change some names to match current architecture specs
- Handle more register info
* some are write-only
* some are read-only
* record which versions have them, just in case
- Reorganize the registers to facilitate removing the extras
* group e.g. comparator/counter #N registers together
* add and use lookup-by-ID
git-svn-id: svn://svn.berlios.de/openocd/trunk@2751 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Add a header comment
- Line up the ETM context struct, pack it a bit
- Remove unused context_id (this doesn't support ETMv2 yet)
- Make most functions static
- Remove unused string table and other needless lines of code
- Correct "tracemode" helptext
Also provide and use an etm_reg_lookup() to find entries in the ETM
register cache. This will help cope with corrected contents of that
cache, which doesn't include entires for non-existent registers.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2750 b42882b7-edfa-0310-969c-e2dbd0fdcd60
didn't turn up earlier. Is everyone still using gcc 3.x? Or is the x86
version of gcc 4.x much more relaxed?
git-svn-id: svn://svn.berlios.de/openocd/trunk@2749 b42882b7-edfa-0310-969c-e2dbd0fdcd60
of a (NOR) flash chip: allow passing "last" as an alias
for the number of the last sector.
Improve several aspects of error checking while we're at it.
From: Johnny Halfmoon <jhalfmoon@milksnot.com>
git-svn-id: svn://svn.berlios.de/openocd/trunk@2746 b42882b7-edfa-0310-969c-e2dbd0fdcd60
garbage after the expected data (from the TAPs' BYPASS or IDCODE
registers).
NOTE that there was previously some code that looked like it was
trying to do this ... which didn't work, because it was looping
over the list of expected TAPs, and never checked *after* that
list completed! That could hide some *nasty* reset issues...
Also replace a now-obsolete scanchain length test with one that
behaves correctly; and update reporting of unexpected IDCODEs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2739 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This patch modifies an error message which, in its original state,
I find somewhat unhelpful. So a small hint was added.
Signed-off-by: Johnny Halfmoon <jhalfmoon at milksnot.com>
git-svn-id: svn://svn.berlios.de/openocd/trunk@2738 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Shrink messaging during resets, primarily by getting rid of
"nothing happened" noise that hides *useful* information.
- Improve: the "no IDCODE" message by identifying which tap only
supports BYPASS; and the TAP event strings.
Related minor code updates:
- Remove two needless tests when examining the chain: we know
we have a TAP, and that all TAPs have names.
- Clean up two loops, turning "while"s into "for"s which better
show what's actually being done.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2736 b42882b7-edfa-0310-969c-e2dbd0fdcd60
for disabling TAPs. We don't actually know how to make any
JRCs which do that yet; but when we do, this will matter.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2735 b42882b7-edfa-0310-969c-e2dbd0fdcd60
and Tcl/external):
- Reorder so *both* paths (TCK/TMS or TRST) can enable TAPs with
ICEpick ... first C code flags TAPs that got disabled, then call
any Tcl code that might want to re-enable them.
- Always call the C/internal handlers when JTAG operations can be
issued; previously that wasn't done when TRST was used.
Plus some small cleanups (whitespace, strings, better messaging
during debug and on some errors) to reset-related code.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2730 b42882b7-edfa-0310-969c-e2dbd0fdcd60
avoid a duplicate test.
Plus other cleanup in the same code: be "static", sane line lengths
for source and diagnostics, and fix misleading variable names.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2725 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Erase logic:
- command invocation
+ treat "nand erase N" (no offset/length) as "erase whole chip N"
+ catch a few more bogus parameter cases, like length == 0 (sigh)
- nand_erase() should be static
- on error
+ say which block failed, and if it was a bad block
+ don't give up after the first error; try to erase the rest
- on success, say which nand device was erased (name isn't unique)
Device list ("nand list"):
- say how many blocks there are
- split summary into two lines
- give example in the docs
Doc tweaks:
- Use @option{...} for DaVinci's supported hardware ECC options
For the record, I've observed that _sometimes_ erasing bad blocks causes
failure reports, and that manufacturer bad block markers aren't always
erasable (even when erasing their blocks doesn't trigger an error report).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2724 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- update comments to say so.
- update docs to clarify that the "arm9tdmi" command prefix
is a misnomer.
- bugfix some messages that wrongly assume only ARM9TDMI
based processors use this code.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2719 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Cleanup some the downloaded ARM target algorithm code:
- Provide more complete disassembly of the DCC bulk write code
- Make code blocks "static const", in case GCC doesn't
- Fix some tabbing/layout issues
- Make some arm7_9_common.h flags be "bool" not "int"; and compact
the layout a bit (group most bools together)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2698 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This patch adds target algorithm support for those flash devices that do not support DQ5 polling. So far they could only be programmed with host algorithm, but this was way too slow.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2682 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Infinite loop bugfix when running tap configure a second time
git-svn-id: svn://svn.berlios.de/openocd/trunk@2681 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Optionally shave time off the armv4_5 run_algorithm() code: let
them terminate using software breakpoints, avoiding roundtrips
to manage hardware ones.
Enable this by using BKPT to terminate execution instead of "branch
to here" loops. Then pass zero as the exit address, except when
running on an ARMv4 core. ARM7TDMI, ARM9TDMI, and derived cores
now set a flag saying they're ARMv4.
Use that mechanism in arm_nandwrite(), for about 3% speedup on a
DaVinci ARM926 core; not huge, but it helps. Some other algorithms
could use this too (mostly flavors of flash operation).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2680 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Provide an "armv7a disassemble" command. Current omissions include
VFP (except as coprocessor instructions), Neon, and various Thumb2
opcodes that are not available in ARMv7-M processors.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2676 b42882b7-edfa-0310-969c-e2dbd0fdcd60
lean up some loose ends with the ARM disassembler
- Add a header comment describing its current state and uses
and referencing the now-generally-available V7 arch spec
- Support some mode switch instructions:
* Thumb to Jazelle (BXJ)
* Thumb to ThumbEE (ENTERX)
* ThumbEE to Thumb (LEAVEX)
- Improve that recent warning fix (and associated whitespace goof)
- Declare the rest of the internal code and data "static". A
compiler may use this, and it helps clarify the scope of these
routines (e.g. what changes to them could affect).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2675 b42882b7-edfa-0310-969c-e2dbd0fdcd60
By enabling this bit, the processor halts when a debug event
such as breakpoint occurs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2668 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Abstract the orion_nand_fast_block_write() routine into a separate
routine -- arm_nandwrite() -- so that other ARM cores can reuse it.
Have davinci_nand do so. This faster than byte-at-a-time ops by a
factor of three (!), even given the slowish interactions to support
hardware ECC (1-bit flavor in that test) each 512 bytes; those could
be read more efficiently by on-chip code.
NOTE that until there's a generic "ARM algorithm" structure, this
can't work on newer ARMv6 (like ARM1136) or ARMv7A (like Cortex-A8)
cores, though the downloaded code itself would work just fine there.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2663 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Via code review by Steve Grubb <sgrubb@redhat.com>
Almost innocuous; this is value is checked later, this
check being wrong would make it check stack garbage.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2655 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Via code review by Steve Grubb <sgrubb@redhat.com>
Also minor fixes for the message from "fill": the byte
count is unsigned, not signed; and more importantly,
print the real number of bytes written
git-svn-id: svn://svn.berlios.de/openocd/trunk@2652 b42882b7-edfa-0310-969c-e2dbd0fdcd60
on the command line ... matching comment in add_default_dirs().
Without this it's impossible to use a private config file which
happens to have the same name as an installed one. Say, because
you're bugfixing a private copy...
git-svn-id: svn://svn.berlios.de/openocd/trunk@2649 b42882b7-edfa-0310-969c-e2dbd0fdcd60
that were added after ARMv5TE was defined:
- ARMv5J "BXJ" (for Java/Jazelle)
- ARMv6 "media" instructions (for OMAP2420, i.MX31, etc)
Compile-tested. This might not set up the simulator right for the
ARMv6 single step support; only BXJ branches though, and docs to
support Jazelle branching are non-public (still, sigh).
ARMv6 instructions known to be mis-handled by this disassembler
include: UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2
git-svn-id: svn://svn.berlios.de/openocd/trunk@2644 b42882b7-edfa-0310-969c-e2dbd0fdcd60
With DCCR we are asking the CPU to halt, we should wait until
the CPU has halted before proceeding with the operation.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2638 b42882b7-edfa-0310-969c-e2dbd0fdcd60
the ITR register but it will only be executed when the DSCR[13]
bit is set. The documentation is a bit weird as it classifies
the DSCR as read-only but the pseudo code is writing to it as
well. This is working on a beagleboard.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2634 b42882b7-edfa-0310-969c-e2dbd0fdcd60
instruction to be finished. This comes from the pseudo code
of the cortex a8 trm.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2632 b42882b7-edfa-0310-969c-e2dbd0fdcd60
"next iteration" step with the rest of the loop overhead.
Cleanup: remove spurious whitespace, and an overlong line;
only assign "tap->hasidcode" once.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2631 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Bugfixes:
* internal osc: it's *12* MHz (not 15 MHz) on _current_ chips
+ except new Tempest parts where it's 16 MHz (and calibrated!)
+ or some old Sandstorm ones, where 15 MHz was valid
* crystal config:
+ read and use the crystal config, don't assume 6 MHz
+ know when that field is 4 bits vs 5
* an RCC2 register may be overriding the original RCC
+ more clock source options
+ bigger dividers
+ fractional dividers on Tempest (NYET handled)
* there's a 30 KHz osc on newer chips (for deep sleep)
* there's a 32768 Hz osc on newer chips (for hibernation)
- Cosmetic
* say "rev A0" not "vA.0", to match vendor docs
* don't always report master clock as an "estimate":
+ give the error bound if it's approximate, like "±30%"
+ else don't say anything
* fix whitespace and caps in some messages
* these are not AT91SAM chips!!
Those clock issues might explain problems sometimes reported when
writing to Stellaris flash banks; they affect write timings.
That 12-vs-15 MHz issue is problematic; there's no consolidated doc
showing which chips (and revs!) have which internal oscillator speed.
It's clear that only older silicon had the faster-and-less-accurate
flavor. What's less clear is which chips are "old" like that.
Lightly tested, on a DustDevil part.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2626 b42882b7-edfa-0310-969c-e2dbd0fdcd60
For ARMv4/ARMv5:
- better command parameter error checking
- don't require an instruction count; default to one
- recognize thumb function addresses
- make function static
- shorten some too-long lines
For Cortex-M3:
- don't require an instruction count; default to one
With the relevant doc updates.
---
Nyet done: invoke the thumb2 disassembler on v4/v5,
to better handle branch instructions.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2624 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Unify the handling of the req_srst parameter, and rip out a
large NOP branch and its associated FIXME. (There didn't seem
to be anything that needs fixing; but that was unclear since
the constraints were scattered all over the place not unified.)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2623 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Unify the handling of the req_tlr_or_trst parameter. Basically,
JTAG TMS+TCK ops ("TLR") is always used ... unless TRST is a safe
option in this system configuration.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2622 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Track whether TRST and/or SRST actually change:
* If they're not changing, don't ask the JTAG adapter to do anything!
(JTAG TCK/TMS ops might still be used to enter TAP_RESET though.)
* Don't change their recorded values until after the adapter says it
did so ... so fault paths can't leave corrupt state.
* Detect and report jtag_execute_queue() failure mode
* Only emit messages saying what really changed; this includes adding
an omitted "deasserted TRST" message.
* Only apply delays after deasserting SRST/TRST if we *DID* deassert!
- Messages say "TLR" not "RESET", to be less confusing; there are many
kinds of reset. (Though "TLR" isn't quite ideal either, since it's
the name of the TAP state being entered by TMS+TCK or TRST; it's at
least non-ambiguous in context.)
So the main effect is to do only the work this routine was told to do;
and to have debug messaging make more sense.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2621 b42882b7-edfa-0310-969c-e2dbd0fdcd60
reset operations. Maybe they can't; or it's a "not yet" thing.
Note that the assert/deassert operations can't yet trigger for
OMAP3 because resets currently include JTAG reset in all cases,
resetting the ICEpick and thus disabling the TAP for Cortex-A8.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2620 b42882b7-edfa-0310-969c-e2dbd0fdcd60
the values that are written in the mini-IC (plus documentation updates that
describe why this is needed).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2613 b42882b7-edfa-0310-969c-e2dbd0fdcd60
nonfunctional cortex_a8 code with something that at least basically
works (for halt/step/resume, without MMU) even if it is incomplete.
(With tweaks from Øyvind, and cleanup from Dave.)
This code has mainly been developed and tested against R1606, it has
been built and tested against R2294 where it runs but step and resume
commands are broken due to regression (which should be fixed now).
This code is really written for OMAP3530. It doesn't identify debug
resources using generic DAP calls to scan the ROM table, or perform
topology detection. The OMAP3530 DAP exposes two memory access ports:
- Port #0 is connected to L3 interconnect (the main bus) with
passthrough to the L4 EMU bus ... so it will be used for most
memory accesses.
- Port #1 is connected to a dedicated debug bus (L4 EMU), with
access to L4 Wakeup, and holds the ROM table ... so it must
be used for most debug and control operations.
The are some defines to handle this in cortex_a8.c, which should be
replaced with more general code. Having access to another Cortex-A8
implementation would help get that right.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2609 b42882b7-edfa-0310-969c-e2dbd0fdcd60
and seed it with DAP access support using the current ADIv5 code.
(With tweaks and cleanup from Øyvind and Dave.)
The ARMv7-AR architecture manual is not publicly available (even
in subset form like the ARMv7-M spec), so it's hard to distinguish
between the Cortex-A8 implementation and the ARMv7-A architecture.
The register set presumably is architectural, and so it's stored
here; it's like earlier ARMs, with small additions. Ditto the
instruction set, though Thumb2 support is used (extending Thumb
support from ARMv6 with more 32-bit instructions) and there's this
ThumbEE thing too. There is a new "debug monitor" mode, not yet
fully addressed here, to support debugging in environments (like
motor control) where halting debug mode is inadvisable.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2608 b42882b7-edfa-0310-969c-e2dbd0fdcd60
The trunk is currently broken for interfaces without
the speed_div function (interface specific clock speed
value to kHz conversion). Example: parport.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2605 b42882b7-edfa-0310-969c-e2dbd0fdcd60
SVF file, making OpenOCD compatible with files generated by
Altera Quatrus II 9.0.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2600 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- warning now issued if high speed ftdi device found and openocd was built using an old driver
git-svn-id: svn://svn.berlios.de/openocd/trunk@2599 b42882b7-edfa-0310-969c-e2dbd0fdcd60
ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch
GCC will generate the table branch instructions, usually with inlined
tables that will confuse this disassembler. LDREX and STREX are not
issued by GCC without inline assembly.
This means all Thumb2 instructions implemented by Cortex-M3 can now
be disassembled. Cortex-A8 cores support more Thumb2 instructions,
but most of those aren't yet publicly documented.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2598 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- spell "address" right
- list bp/wp params as optional
And make those source lines wrap at sane margins.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2596 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- AIRCR_SYSRESETREQ is generic; use it on any system where
SRST won't fly, not just on Stellaris-based ones.
- Reformat and improve comments about the Stellaris quirk; and
xref the only public docs (an email) about the issue.
It seems that *most* Stellaris chips have this problem. Tempest
parts aren't yet in general sampling; and if rev B silicon for
earlier chips exists, it's not very visible yet.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2595 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Simplify dumping of register lists by only printing cached values
if they are marked as valid. Most of the time, they are invalid;
so printing *any* value is just misleading.
Note that for ARM7 and ARM9 most EmbeddedICE registers (except for
debug status) could be cached most of the time; and their register
cache isn't maintained properly (many accesses seem to bypass that
cache code).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2594 b42882b7-edfa-0310-969c-e2dbd0fdcd60
https://lists.berlios.de/pipermail/openocd-development/2009-August/009939.html
1. It can only be built with the FTD2XX driver. libftdi supports FT2232H/FT4232H
since version 0.16
2. A speed value of 0 is used as a RTCK request indicator. This clashes with the
valid clock division value 0 that provide the highest fixed clock frequency.
3. The ft2232_speed_div function return the maximum selectable frequency (30MHz)
when RTCK is activated. It should return 0.
4. The ft2232_khz function return ERROR_OK when RTCK is requested even for
devices lacking RTCK support. It should return ERROR_FAIL so the upper driver layers
can detect this and try to fallback to a fixed frequency.
5. FT2232H/FT4232H have a backward compatibility function that divide the clock
by 5 to get the same frequency range as FT2232D. There is no code that disable
this functionality. I can not find anything about if this is enabled or disabled by default.
I think it is safest to actively disable it.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2591 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Change jtag_rclk behaviour so it can be called before the interface init function
git-svn-id: svn://svn.berlios.de/openocd/trunk@2590 b42882b7-edfa-0310-969c-e2dbd0fdcd60
issue with this is that the core debug support uses this
mechanism, then trashes its state over reset. Users can
Work around that (for now) by re-assigning the desired
config after reset.
Also fixes "target halted due to target-not-halted" goof.
When we can't describe the reason using OpenOCD's limited
vocabulary, say "reason undefined" instead of saying it's
not halted.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2588 b42882b7-edfa-0310-969c-e2dbd0fdcd60
arrays (error prone) or assume all registers are 32-bits wide (they can
have fewer bits); don't use spaces in register names, so they can be
passed more easily to the "reg" command.
Minor updates for ARM9 vector_catch support: it's an 8-bit value. This
seems to help this core's vector_catch command work a bit better; but its
behavior wih the register cache is still goofy.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2587 b42882b7-edfa-0310-969c-e2dbd0fdcd60
display them as 32 bits unless that's their true size.
(Removes some confusion.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2586 b42882b7-edfa-0310-969c-e2dbd0fdcd60
OpenOCD was able to access only to chips attached to first EMIF
chipselect. This patch fixes chipselect management code and allows
OpenOCD to access to NAND devices attached to any EMIF CS line.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2585 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Add flash programming support for NXP LPC1700 cortex_m3 based family
git-svn-id: svn://svn.berlios.de/openocd/trunk@2579 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Warn about anyone using "jtag_speed" commands; that command is obsolete, and will someday be removed.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2578 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- revert patch from rev1507 as it was causing reset issues with arm9 cores
git-svn-id: svn://svn.berlios.de/openocd/trunk@2574 b42882b7-edfa-0310-969c-e2dbd0fdcd60
A5.3.11 Data processing (shifted register)
The usual kinds of problems; the most noteworthy were that
the "S"et flags bit was mis-handled in these instructions.
---
This is the last patch from a quickie set of tests covering all
encodings of the instructions with 32-bit opcodes. There may
be some corner cases left, plus the instructions that aren't
yet handled, but the Thumb2 disassembler is no longer just
"lightly" tested with GCC output ... the new code paths have
mostly been verified.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2568 b42882b7-edfa-0310-969c-e2dbd0fdcd60
A5.3.5 Load/store multiple
A5.3.7 Load word
There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM
fixes are just using width specs to match UAL syntax, except for two
opcode name typos. Load word had two bitmask goofs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2567 b42882b7-edfa-0310-969c-e2dbd0fdcd60
A5.3.8 Load halfword, unallocated memory hints
It's mostly the usual sort of bitmasking goofage and getting the
width specs right. In one case an older x86 GCC generated bad code
unless I structred a conditional differently (sigh).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2566 b42882b7-edfa-0310-969c-e2dbd0fdcd60
A5.3.5 Load/store multiple
A5.3.7 Load word
There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM
fixes are just using width specs to match UAL syntax, except for two
opcode name typos. Load word had two bitmask goofs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2565 b42882b7-edfa-0310-969c-e2dbd0fdcd60
ARMv7-M arch manual:
A5.3.1 Data processing (modified immediate)
A5.3.3 Data processing (plain binary immediate)
A5.3.4 Branches and miscellaneous control
and other (immediate) encodings referenced there. Several of
these just tweak the new syntax ("Unified" ARM/Thumb: UAL) but
there were a few bugs too.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2564 b42882b7-edfa-0310-969c-e2dbd0fdcd60
with testcases covering several new encodings in these sections
of the ARMv7-M arch manual:
A5.3.12 Data processing (register)
A5.3.13 Miscellaneous operations
A5.3.14 Multiply, and multiply accumulate
A5.3.15 Long multiply, long multiply accumulate, and divide
The issues were mostly in '12 and '13; some new related 16-bit
opcodes had issues too.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2563 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Dump SP on poll, and show whether it's MSP or PSP.
Thread mode can use either stack pointer, so this is
part of the state that's not yet displayed.
Shrink some lines.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2555 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Clean up treatment of registers in ARMv7-M and Cortex-M3.
- At the arch level:
* Just list registers and names; don't impose core-specific
policy about how they are accessed.
* Each register has a symbol.
* Remove the register mode field (irrelevant to debugger)
- At the core/implementation level:
* Just map the registers to their relevant access methods;
don't require the arch level to say how that should work
(cores other than Cortex-M3 could do it differently).
* Don't use undefined bits from register 20.
* Use register IDs that are part of the ARMv7-M interface.
In short, there's now a real distinction between the arch
and core layers.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Minor updates to the Thumb2 disassembly:
- Bugfixes:
* Distinguish branch from misc via "!=" not "=="
* MRS register shift is 8 bits (vs MSR being 16)
- Format tweaks:
* CPS needed tab (not space)
* add commma before some shifts
* add space after comma in LDM/STM
* use ".W" width spec on various instructions
git-svn-id: svn://svn.berlios.de/openocd/trunk@2553 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Revert parts of the previous ARMv7-M register patch.
It turns out that part of the issue is a documentation
problem for the Cortex-M3 r1 parts. So for the rest,
simpler fixes are possible (in followup patch).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2552 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- fix issue when multiple flash chips are connected, eg. x16 x 2 on 32bit mcu bus
git-svn-id: svn://svn.berlios.de/openocd/trunk@2551 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Move the dap command handler implementations to arm_adi_v5.c,
leaving just thin wrappers in armv7m.c. There should be no
change in functionality here. (From Magnus.)
Minor style cleanup: whitespace, line length, etc. Update spec
references to use docs which are currently available. (From Dave.)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2544 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Some cleanup of the ARMv7-M support:
- Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and
update the Cortex-M3 doc refs (DDI 0337C is no longer available).
- Those registers aren't actually general, and some are incorrect (per all
public docs anyway). Update comments and code accordingly.
* What the Core Debug facility exposes is *implementation-specific*
not architectural. These values aren't fully portable. They match
Cortex-M3 ... so no current implementation will make trouble, but
the next v7m implementation might.
* Four of the registers are actually not exposed that way. Before
Cortex-M3 r2p0 they are read/written through MRS/MSR instructions.
In that newest silicon, they are four bytes in one register, not
four separate registers.
- Update the CM3 code to report when that one register is available,
and not try to access it when it isn't. Also declare the register
numbers that an eventual MRS/MSR solution will need to be using.
- Stop line wrapping the exception labels.
So for parts before r2p0 OpenOCD behavior is effectively unchanged, and
still buggy; but for those newer parts a few things might now be correct.
Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include
most LM3S parts and all STM32 parts. Parts using r2p0 are available, and
include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx
parts which are now sampling.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
More instructions decoded:
A5.3.5 Load/store multiple
The preferred PUSH/POP syntax is shown when appropriate.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2539 b42882b7-edfa-0310-969c-e2dbd0fdcd60
More instructions decoded:
A5.3.14 Multiply, and multiply accumulate
A5.3.15 Long multiply, long multiply accumulate, divide
The EABI requires *adjacent* register pairs, but the long multiply
ops can use any pair of registers; interesting.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2538 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Zachary T Welch
David Brownell
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Michael Bruck
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Dimitar Dimitrov
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Redirect 'Slash' NIL
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