ARMv7A: use standard disassembler
We no longer need v7A-specific code for this. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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@ -5535,10 +5535,17 @@ that is not currently supported in OpenOCD.)
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Disassembles @var{count} instructions starting at @var{address}.
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If @var{count} is not specified, a single instruction is disassembled.
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If @option{thumb} is specified, or the low bit of the address is set,
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Thumb (16-bit) instructions are used;
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Thumb2 (mixed 16/32-bit) instructions are used;
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else ARM (32-bit) instructions are used.
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(Processors may also support the Jazelle state, but
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those instructions are not currently understood by OpenOCD.)
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Note that all Thumb instructions are Thumb2 instructions,
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so older processors (without Thumb2 support) will still
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see correct disassembly of Thumb code.
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Also, ThumbEE opcodes are the same as Thumb2,
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with a handful of exceptions.
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ThumbEE disassembly currently has no explicit support.
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@end deffn
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@deffn Command {arm reg}
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@ -5941,23 +5948,6 @@ Displays the number of extra tck for mem-ap memory bus access [0-255].
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If @var{value} is defined, first assigns that.
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@end deffn
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@subsection ARMv7-A specific commands
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@cindex ARMv7-A
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@deffn Command {armv7a disassemble} address [count [@option{thumb}]]
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@cindex disassemble
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Disassembles @var{count} instructions starting at @var{address}.
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If @var{count} is not specified, a single instruction is disassembled.
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If @option{thumb} is specified, or the low bit of the address is set,
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Thumb2 (mixed 16/32-bit) instructions are used;
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else ARM (32-bit) instructions are used.
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With a handful of exceptions, ThumbEE instructions are the same as Thumb2;
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ThumbEE disassembly currently has no explicit support.
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(Processors may also support the Jazelle state, but
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those instructions are not currently understood by OpenOCD.)
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@end deffn
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@subsection Cortex-M3 specific commands
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@cindex Cortex-M3
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@ -274,84 +274,9 @@ COMMAND_HANDLER(handle_dap_info_command)
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return dap_info_command(cmd_ctx, swjdp, apsel);
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}
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COMMAND_HANDLER(handle_armv7a_disassemble_command)
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{
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struct target *target = get_current_target(cmd_ctx);
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struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
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int thumb = 0;
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int count = 1;
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uint32_t address;
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int i;
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if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) {
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command_print(cmd_ctx, "current target isn't an ARM target");
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return ERROR_OK;
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}
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/* REVISIT: eventually support ThumbEE disassembly too;
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* some opcodes work differently.
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*/
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switch (argc) {
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case 3:
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if (strcmp(args[2], "thumb") != 0)
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goto usage;
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thumb = 1;
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/* FALL THROUGH */
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case 2:
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COMMAND_PARSE_NUMBER(int, args[1], count);
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/* FALL THROUGH */
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case 1:
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COMMAND_PARSE_NUMBER(u32, args[0], address);
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if (address & 0x01) {
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if (!thumb) {
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command_print(cmd_ctx, "Disassemble as Thumb");
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thumb = 1;
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}
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address &= ~1;
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}
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break;
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default:
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usage:
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command_print(cmd_ctx,
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"usage: armv7a disassemble <address> [<count> ['thumb']]");
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return ERROR_OK;
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}
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for (i = 0; i < count; i++) {
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struct arm_instruction cur_instruction;
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int retval;
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if (thumb) {
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retval = thumb2_opcode(target, address, &cur_instruction);
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if (retval != ERROR_OK)
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return retval;
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address += cur_instruction.instruction_size;
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} else {
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uint32_t opcode;
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retval = target_read_u32(target, address, &opcode);
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if (retval != ERROR_OK)
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return retval;
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retval = arm_evaluate_opcode(opcode, address,
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&cur_instruction);
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if (retval != ERROR_OK)
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return retval;
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address += 4;
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}
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command_print(cmd_ctx, "%s", cur_instruction.text);
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}
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return ERROR_OK;
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}
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int armv7a_register_commands(struct command_context *cmd_ctx)
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{
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struct command *arm_adi_v5_dap_cmd;
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struct command *armv7a_cmd;
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arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap",
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NULL, COMMAND_ANY,
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@ -377,13 +302,5 @@ int armv7a_register_commands(struct command_context *cmd_ctx)
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"set/get number of extra tck for mem-ap memory "
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"bus access [0-255]");
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armv7a_cmd = register_command(cmd_ctx, NULL, "armv7a",
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NULL, COMMAND_ANY,
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"ARMv7-A specific commands");
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register_command(cmd_ctx, armv7a_cmd, "disassemble",
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handle_armv7a_disassemble_command, COMMAND_EXEC,
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"disassemble instructions <address> [<count> ['thumb']]");
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return ERROR_OK;
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}
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