arm11_common_t -> struct arm11_common
Remove misleading typedef and redundant suffix from struct arm11_common.
This commit is contained in:
Zachary T Welch
parent
0eae94879d
commit
55926f576f
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@ -261,7 +261,7 @@ static reg_t arm11_gdb_dummy_fps_reg =
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};
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static int arm11_on_enter_debug_state(arm11_common_t *arm11);
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static int arm11_on_enter_debug_state(struct arm11_common *arm11);
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static int arm11_step(struct target_s *target, int current,
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uint32_t address, int handle_breakpoints);
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/* helpers */
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@ -269,8 +269,8 @@ static int arm11_build_reg_cache(target_t *target);
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static int arm11_set_reg(reg_t *reg, uint8_t *buf);
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static int arm11_get_reg(reg_t *reg);
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static void arm11_record_register_history(arm11_common_t * arm11);
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static void arm11_dump_reg_changes(arm11_common_t * arm11);
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static void arm11_record_register_history(struct arm11_common * arm11);
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static void arm11_dump_reg_changes(struct arm11_common * arm11);
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/** Check and if necessary take control of the system
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@ -280,7 +280,7 @@ static void arm11_dump_reg_changes(arm11_common_t * arm11);
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* available a pointer to a word holding the
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* DSCR can be passed. Otherwise use NULL.
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*/
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static int arm11_check_init(arm11_common_t *arm11, uint32_t *dscr)
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static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
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{
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FNC_INFO;
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@ -338,7 +338,7 @@ static int arm11_check_init(arm11_common_t *arm11, uint32_t *dscr)
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* or on other occasions that stop the processor.
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*
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*/
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static int arm11_on_enter_debug_state(arm11_common_t *arm11)
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static int arm11_on_enter_debug_state(struct arm11_common *arm11)
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{
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int retval;
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FNC_INFO;
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@ -502,7 +502,7 @@ static int arm11_on_enter_debug_state(arm11_common_t *arm11)
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return ERROR_OK;
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}
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void arm11_dump_reg_changes(arm11_common_t * arm11)
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void arm11_dump_reg_changes(struct arm11_common * arm11)
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{
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if (!(debug_level >= LOG_LVL_DEBUG))
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@ -537,7 +537,7 @@ void arm11_dump_reg_changes(arm11_common_t * arm11)
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* This is called in preparation for the RESTART function.
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*
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*/
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static int arm11_leave_debug_state(arm11_common_t *arm11)
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static int arm11_leave_debug_state(struct arm11_common *arm11)
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{
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FNC_INFO;
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int retval;
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@ -654,7 +654,7 @@ static int arm11_leave_debug_state(arm11_common_t *arm11)
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return ERROR_OK;
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}
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static void arm11_record_register_history(arm11_common_t *arm11)
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static void arm11_record_register_history(struct arm11_common *arm11)
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{
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for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
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{
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@ -673,7 +673,7 @@ static int arm11_poll(struct target_s *target)
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FNC_INFO;
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int retval;
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arm11_common_t * arm11 = target->arch_info;
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struct arm11_common * arm11 = target->arch_info;
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uint32_t dscr;
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@ -715,7 +715,7 @@ static int arm11_poll(struct target_s *target)
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/* architecture specific status reply */
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static int arm11_arch_state(struct target_s *target)
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{
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arm11_common_t * arm11 = target->arch_info;
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struct arm11_common * arm11 = target->arch_info;
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LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
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Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
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@ -739,7 +739,7 @@ static int arm11_halt(struct target_s *target)
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{
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FNC_INFO;
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arm11_common_t * arm11 = target->arch_info;
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struct arm11_common * arm11 = target->arch_info;
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LOG_DEBUG("target->state: %s",
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target_state_name(target));
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@ -808,7 +808,7 @@ static int arm11_resume(struct target_s *target, int current,
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// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
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// current, address, handle_breakpoints, debug_execution);
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arm11_common_t * arm11 = target->arch_info;
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struct arm11_common * arm11 = target->arch_info;
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LOG_DEBUG("target->state: %s",
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target_state_name(target));
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@ -944,7 +944,7 @@ static int armv4_5_to_arm11(int reg)
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static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
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{
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arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
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struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
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reg=armv4_5_to_arm11(reg);
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@ -954,7 +954,7 @@ static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
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static void arm11_sim_set_reg(struct arm_sim_interface *sim,
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int reg, uint32_t value)
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{
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arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
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struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
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reg=armv4_5_to_arm11(reg);
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@ -964,14 +964,14 @@ static void arm11_sim_set_reg(struct arm_sim_interface *sim,
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static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim,
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int pos, int bits)
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{
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arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
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struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
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return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
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}
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static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
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{
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// arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
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// struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
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/* FIX!!!! we should implement thumb for arm11 */
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return ARMV4_5_STATE_ARM;
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@ -980,7 +980,7 @@ static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
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static void arm11_sim_set_state(struct arm_sim_interface *sim,
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enum armv4_5_state mode)
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{
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// arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
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// struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
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/* FIX!!!! we should implement thumb for arm11 */
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LOG_ERROR("Not implemetned!");
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@ -989,7 +989,7 @@ static void arm11_sim_set_state(struct arm_sim_interface *sim,
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static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
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{
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//arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
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//struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
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/* FIX!!!! we should implement something that returns the current mode here!!! */
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return ARMV4_5_MODE_USR;
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@ -1027,7 +1027,7 @@ static int arm11_step(struct target_s *target, int current,
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return ERROR_TARGET_NOT_HALTED;
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}
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arm11_common_t * arm11 = target->arch_info;
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struct arm11_common * arm11 = target->arch_info;
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if (!current)
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R(PC) = address;
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@ -1174,7 +1174,7 @@ static int arm11_assert_reset(target_t *target)
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FNC_INFO;
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int retval;
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arm11_common_t * arm11 = target->arch_info;
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struct arm11_common * arm11 = target->arch_info;
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retval = arm11_check_init(arm11, NULL);
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if (retval != ERROR_OK)
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return retval;
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@ -1249,7 +1249,7 @@ static int arm11_get_gdb_reg_list(struct target_s *target,
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{
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FNC_INFO;
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arm11_common_t * arm11 = target->arch_info;
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struct arm11_common * arm11 = target->arch_info;
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*reg_list_size = ARM11_GDB_REGISTER_COUNT;
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*reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
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@ -1297,7 +1297,7 @@ static int arm11_read_memory_inner(struct target_s *target,
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LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
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arm11_common_t * arm11 = target->arch_info;
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struct arm11_common * arm11 = target->arch_info;
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retval = arm11_run_instr_data_prepare(arm11);
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if (retval != ERROR_OK)
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@ -1393,7 +1393,7 @@ static int arm11_write_memory_inner(struct target_s *target,
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LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
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arm11_common_t * arm11 = target->arch_info;
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struct arm11_common * arm11 = target->arch_info;
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retval = arm11_run_instr_data_prepare(arm11);
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if (retval != ERROR_OK)
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@ -1556,7 +1556,7 @@ static int arm11_add_breakpoint(struct target_s *target,
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{
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FNC_INFO;
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arm11_common_t * arm11 = target->arch_info;
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struct arm11_common * arm11 = target->arch_info;
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#if 0
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if (breakpoint->type == BKPT_SOFT)
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@ -1588,7 +1588,7 @@ static int arm11_remove_breakpoint(struct target_s *target,
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{
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FNC_INFO;
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arm11_common_t * arm11 = target->arch_info;
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struct arm11_common * arm11 = target->arch_info;
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arm11->free_brps++;
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@ -1619,7 +1619,7 @@ static int arm11_run_algorithm(struct target_s *target,
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uint32_t entry_point, uint32_t exit_point,
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int timeout_ms, void *arch_info)
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{
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arm11_common_t *arm11 = target->arch_info;
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struct arm11_common *arm11 = target->arch_info;
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// enum armv4_5_state core_state = arm11->core_state;
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// enum armv4_5_mode core_mode = arm11->core_mode;
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uint32_t context[16];
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@ -1783,7 +1783,7 @@ static int arm11_target_create(struct target_s *target, Jim_Interp *interp)
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{
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FNC_INFO;
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NEW(arm11_common_t, arm11, 1);
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NEW(struct arm11_common, arm11, 1);
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arm11->target = target;
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@ -1815,7 +1815,7 @@ static int arm11_examine(struct target_s *target)
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FNC_INFO;
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arm11_common_t * arm11 = target->arch_info;
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struct arm11_common * arm11 = target->arch_info;
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/* check IDCODE */
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@ -1906,7 +1906,7 @@ static int arm11_get_reg(reg_t *reg)
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/** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
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#if 0
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arm11_common_t *arm11 = target->arch_info;
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struct arm11_common *arm11 = target->arch_info;
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const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
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#endif
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@ -1919,7 +1919,7 @@ static int arm11_set_reg(reg_t *reg, uint8_t *buf)
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FNC_INFO;
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target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
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arm11_common_t *arm11 = target->arch_info;
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struct arm11_common *arm11 = target->arch_info;
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// const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
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arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
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@ -1931,7 +1931,7 @@ static int arm11_set_reg(reg_t *reg, uint8_t *buf)
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static int arm11_build_reg_cache(target_t *target)
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{
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arm11_common_t *arm11 = target->arch_info;
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struct arm11_common *arm11 = target->arch_info;
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NEW(reg_cache_t, cache, 1);
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NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
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@ -2064,7 +2064,7 @@ static const uint32_t arm11_coproc_instruction_limits[] =
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0xFFFFFFFF, /* value */
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};
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static arm11_common_t * arm11_find_target(const char * arg)
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static struct arm11_common * arm11_find_target(const char * arg)
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{
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struct jtag_tap * tap;
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target_t * t;
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@ -2099,7 +2099,7 @@ static int arm11_mrc_inner(target_t *target, int cpnum,
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return ERROR_FAIL;
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}
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arm11_common_t * arm11 = target->arch_info;
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struct arm11_common * arm11 = target->arch_info;
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uint32_t instr = 0xEE000010 |
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(cpnum << 8) |
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@ -2151,7 +2151,7 @@ static COMMAND_HELPER(arm11_handle_etm_read_write, bool read)
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return ERROR_COMMAND_SYNTAX_ERROR;
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}
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arm11_common_t * arm11 = arm11_find_target(args[0]);
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struct arm11_common * arm11 = arm11_find_target(args[0]);
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if (!arm11)
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{
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@ -78,7 +78,7 @@ enum arm11_debug_version
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ARM11_DEBUG_V7_CP14 = 0x04,
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};
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typedef struct arm11_common_s
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struct arm11_common
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{
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target_t * target; /**< Reference back to the owner */
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@ -117,7 +117,7 @@ typedef struct arm11_common_s
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// GA
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reg_cache_t *core_cache;
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} arm11_common_t;
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};
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/**
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@ -184,8 +184,8 @@ typedef struct arm11_reg_state_s
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int arm11_register_commands(struct command_context_s *cmd_ctx);
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int arm11_read_etm(arm11_common_t * arm11, uint8_t address, uint32_t *value);
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int arm11_write_etm(arm11_common_t * arm11, uint8_t address, uint32_t value);
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int arm11_read_etm(struct arm11_common * arm11, uint8_t address, uint32_t *value);
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int arm11_write_etm(struct arm11_common * arm11, uint8_t address, uint32_t value);
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@ -81,7 +81,7 @@ int arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, tap_state_t
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* <em > (data is written when the JTAG queue is executed)</em>
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* \param field target data structure that will be initialized
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*/
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void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, struct scan_field * field)
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void arm11_setup_field(struct arm11_common * arm11, int num_bits, void * out_data, void * in_data, struct scan_field * field)
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{
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field->tap = arm11->target->tap;
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field->num_bits = num_bits;
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@ -98,7 +98,7 @@ void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, vo
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*
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* \remarks This adds to the JTAG command queue but does \em not execute it.
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*/
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void arm11_add_IR(arm11_common_t * arm11, uint8_t instr, tap_state_t state)
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void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state)
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{
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struct jtag_tap *tap;
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tap = arm11->target->tap;
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@ -161,7 +161,7 @@ static void arm11_in_handler_SCAN_N(uint8_t *in_value)
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* \remarks This adds to the JTAG command queue but does \em not execute it.
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*/
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int arm11_add_debug_SCAN_N(arm11_common_t * arm11, uint8_t chain, tap_state_t state)
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int arm11_add_debug_SCAN_N(struct arm11_common * arm11, uint8_t chain, tap_state_t state)
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{
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JTAG_DEBUG("SCREG <= 0x%02x", chain);
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@ -198,7 +198,7 @@ int arm11_add_debug_SCAN_N(arm11_common_t * arm11, uint8_t chain, tap_state_t st
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*
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* \remarks This adds to the JTAG command queue but does \em not execute it.
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*/
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void arm11_add_debug_INST(arm11_common_t * arm11, uint32_t inst, uint8_t * flag, tap_state_t state)
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void arm11_add_debug_INST(struct arm11_common * arm11, uint32_t inst, uint8_t * flag, tap_state_t state)
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{
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JTAG_DEBUG("INST <= 0x%08x", inst);
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@ -220,7 +220,7 @@ void arm11_add_debug_INST(arm11_common_t * arm11, uint32_t inst, uint8_t * flag,
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*
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* \remarks This is a stand-alone function that executes the JTAG command queue.
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*/
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int arm11_read_DSCR(arm11_common_t * arm11, uint32_t *value)
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int arm11_read_DSCR(struct arm11_common * arm11, uint32_t *value)
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{
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int retval;
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retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
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@ -257,7 +257,7 @@ int arm11_read_DSCR(arm11_common_t * arm11, uint32_t *value)
|
|||
*
|
||||
* \remarks This is a stand-alone function that executes the JTAG command queue.
|
||||
*/
|
||||
int arm11_write_DSCR(arm11_common_t * arm11, uint32_t dscr)
|
||||
int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr)
|
||||
{
|
||||
int retval;
|
||||
retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
|
||||
|
|
@ -339,7 +339,7 @@ enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr)
|
|||
* \param arm11 Target state variable.
|
||||
*
|
||||
*/
|
||||
int arm11_run_instr_data_prepare(arm11_common_t * arm11)
|
||||
int arm11_run_instr_data_prepare(struct arm11_common * arm11)
|
||||
{
|
||||
return arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
|
||||
}
|
||||
|
|
@ -358,7 +358,7 @@ int arm11_run_instr_data_prepare(arm11_common_t * arm11)
|
|||
* \param arm11 Target state variable.
|
||||
*
|
||||
*/
|
||||
int arm11_run_instr_data_finish(arm11_common_t * arm11)
|
||||
int arm11_run_instr_data_finish(struct arm11_common * arm11)
|
||||
{
|
||||
return arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
|
||||
}
|
||||
|
|
@ -374,7 +374,7 @@ int arm11_run_instr_data_finish(arm11_common_t * arm11)
|
|||
* \param count Number of opcodes to execute
|
||||
*
|
||||
*/
|
||||
int arm11_run_instr_no_data(arm11_common_t * arm11, uint32_t * opcode, size_t count)
|
||||
int arm11_run_instr_no_data(struct arm11_common * arm11, uint32_t * opcode, size_t count)
|
||||
{
|
||||
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
|
||||
|
||||
|
|
@ -424,7 +424,7 @@ int arm11_run_instr_no_data(arm11_common_t * arm11, uint32_t * opcode, size_t co
|
|||
* \param opcode ARM opcode
|
||||
*
|
||||
*/
|
||||
int arm11_run_instr_no_data1(arm11_common_t * arm11, uint32_t opcode)
|
||||
int arm11_run_instr_no_data1(struct arm11_common * arm11, uint32_t opcode)
|
||||
{
|
||||
return arm11_run_instr_no_data(arm11, &opcode, 1);
|
||||
}
|
||||
|
|
@ -443,7 +443,7 @@ int arm11_run_instr_no_data1(arm11_common_t * arm11, uint32_t opcode)
|
|||
* \param count Number of data words and instruction repetitions
|
||||
*
|
||||
*/
|
||||
int arm11_run_instr_data_to_core(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count)
|
||||
int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count)
|
||||
{
|
||||
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
|
||||
|
||||
|
|
@ -570,7 +570,7 @@ static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
|
|||
* \param count Number of data words and instruction repetitions
|
||||
*
|
||||
*/
|
||||
int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count)
|
||||
int arm11_run_instr_data_to_core_noack(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count)
|
||||
{
|
||||
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
|
||||
|
||||
|
|
@ -655,7 +655,7 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, uint32_t opcode,
|
|||
* \param data Data word to be passed to the core via DTR
|
||||
*
|
||||
*/
|
||||
int arm11_run_instr_data_to_core1(arm11_common_t * arm11, uint32_t opcode, uint32_t data)
|
||||
int arm11_run_instr_data_to_core1(struct arm11_common * arm11, uint32_t opcode, uint32_t data)
|
||||
{
|
||||
return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
|
||||
}
|
||||
|
|
@ -674,7 +674,7 @@ int arm11_run_instr_data_to_core1(arm11_common_t * arm11, uint32_t opcode, uint3
|
|||
* \param count Number of data words and instruction repetitions
|
||||
*
|
||||
*/
|
||||
int arm11_run_instr_data_from_core(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count)
|
||||
int arm11_run_instr_data_from_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count)
|
||||
{
|
||||
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
|
||||
|
||||
|
|
@ -740,7 +740,7 @@ int arm11_run_instr_data_from_core(arm11_common_t * arm11, uint32_t opcode, uint
|
|||
* \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
|
||||
*
|
||||
*/
|
||||
int arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t * data)
|
||||
int arm11_run_instr_data_from_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t * data)
|
||||
{
|
||||
int retval;
|
||||
retval = arm11_run_instr_no_data1(arm11, opcode);
|
||||
|
|
@ -765,7 +765,7 @@ int arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, uint32_t opcod
|
|||
* \param data Data word that will be written to r0 before \p opcode is executed
|
||||
*
|
||||
*/
|
||||
int arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t data)
|
||||
int arm11_run_instr_data_to_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t data)
|
||||
{
|
||||
int retval;
|
||||
/* MRC p14,0,r0,c0,c5,0 */
|
||||
|
|
@ -789,7 +789,7 @@ int arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, uint32_t opcode,
|
|||
* \param count Number of instructions in the list.
|
||||
*
|
||||
*/
|
||||
int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
|
||||
int arm11_sc7_run(struct arm11_common * arm11, arm11_sc7_action_t * actions, size_t count)
|
||||
{
|
||||
int retval;
|
||||
|
||||
|
|
@ -873,7 +873,7 @@ int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t c
|
|||
* \param arm11 Target state variable.
|
||||
*
|
||||
*/
|
||||
void arm11_sc7_clear_vbw(arm11_common_t * arm11)
|
||||
void arm11_sc7_clear_vbw(struct arm11_common * arm11)
|
||||
{
|
||||
arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1];
|
||||
arm11_sc7_action_t * pos = clear_bw;
|
||||
|
|
@ -902,7 +902,7 @@ void arm11_sc7_clear_vbw(arm11_common_t * arm11)
|
|||
* \param arm11 Target state variable.
|
||||
* \param value Value to be written
|
||||
*/
|
||||
void arm11_sc7_set_vcr(arm11_common_t * arm11, uint32_t value)
|
||||
void arm11_sc7_set_vcr(struct arm11_common * arm11, uint32_t value)
|
||||
{
|
||||
arm11_sc7_action_t set_vcr;
|
||||
|
||||
|
|
@ -923,7 +923,7 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, uint32_t value)
|
|||
* \param result Pointer where to store result
|
||||
*
|
||||
*/
|
||||
int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t * result)
|
||||
int arm11_read_memory_word(struct arm11_common * arm11, uint32_t address, uint32_t * result)
|
||||
{
|
||||
int retval;
|
||||
retval = arm11_run_instr_data_prepare(arm11);
|
||||
|
|
@ -952,7 +952,7 @@ int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t *
|
|||
*
|
||||
* \remarks This is a stand-alone function that executes the JTAG command queue.
|
||||
*/
|
||||
int arm11_write_etm(arm11_common_t * arm11, uint8_t address, uint32_t value)
|
||||
int arm11_write_etm(struct arm11_common * arm11, uint8_t address, uint32_t value)
|
||||
{
|
||||
CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT));
|
||||
|
||||
|
|
@ -986,7 +986,7 @@ int arm11_write_etm(arm11_common_t * arm11, uint8_t address, uint32_t value)
|
|||
*
|
||||
* \remarks This is a stand-alone function that executes the JTAG command queue.
|
||||
*/
|
||||
int arm11_read_etm(arm11_common_t * arm11, uint8_t address, uint32_t * value)
|
||||
int arm11_read_etm(struct arm11_common * arm11, uint8_t address, uint32_t * value)
|
||||
{
|
||||
CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT));
|
||||
|
||||
|
|
|
|||
|
|
@ -5,35 +5,35 @@
|
|||
|
||||
/* ARM11 internals */
|
||||
|
||||
void arm11_setup_field(arm11_common_t *arm11, int num_bits,
|
||||
void arm11_setup_field(struct arm11_common *arm11, int num_bits,
|
||||
void *in_data, void *out_data, struct scan_field *field);
|
||||
void arm11_add_IR(arm11_common_t *arm11,
|
||||
void arm11_add_IR(struct arm11_common *arm11,
|
||||
uint8_t instr, tap_state_t state);
|
||||
int arm11_add_debug_SCAN_N(arm11_common_t *arm11,
|
||||
int arm11_add_debug_SCAN_N(struct arm11_common *arm11,
|
||||
uint8_t chain, tap_state_t state);
|
||||
void arm11_add_debug_INST(arm11_common_t *arm11,
|
||||
void arm11_add_debug_INST(struct arm11_common *arm11,
|
||||
uint32_t inst, uint8_t *flag, tap_state_t state);
|
||||
int arm11_read_DSCR(arm11_common_t *arm11, uint32_t *dscr);
|
||||
int arm11_write_DSCR(arm11_common_t *arm11, uint32_t dscr);
|
||||
int arm11_read_DSCR(struct arm11_common *arm11, uint32_t *dscr);
|
||||
int arm11_write_DSCR(struct arm11_common *arm11, uint32_t dscr);
|
||||
|
||||
enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr);
|
||||
|
||||
int arm11_run_instr_data_prepare(arm11_common_t *arm11);
|
||||
int arm11_run_instr_data_finish(arm11_common_t *arm11);
|
||||
int arm11_run_instr_no_data(arm11_common_t *arm11,
|
||||
int arm11_run_instr_data_prepare(struct arm11_common *arm11);
|
||||
int arm11_run_instr_data_finish(struct arm11_common *arm11);
|
||||
int arm11_run_instr_no_data(struct arm11_common *arm11,
|
||||
uint32_t *opcode, size_t count);
|
||||
int arm11_run_instr_no_data1(arm11_common_t *arm11, uint32_t opcode);
|
||||
int arm11_run_instr_data_to_core(arm11_common_t *arm11,
|
||||
int arm11_run_instr_no_data1(struct arm11_common *arm11, uint32_t opcode);
|
||||
int arm11_run_instr_data_to_core(struct arm11_common *arm11,
|
||||
uint32_t opcode, uint32_t *data, size_t count);
|
||||
int arm11_run_instr_data_to_core_noack(arm11_common_t *arm11,
|
||||
int arm11_run_instr_data_to_core_noack(struct arm11_common *arm11,
|
||||
uint32_t opcode, uint32_t *data, size_t count);
|
||||
int arm11_run_instr_data_to_core1(arm11_common_t *arm11,
|
||||
int arm11_run_instr_data_to_core1(struct arm11_common *arm11,
|
||||
uint32_t opcode, uint32_t data);
|
||||
int arm11_run_instr_data_from_core(arm11_common_t *arm11,
|
||||
int arm11_run_instr_data_from_core(struct arm11_common *arm11,
|
||||
uint32_t opcode, uint32_t *data, size_t count);
|
||||
int arm11_run_instr_data_from_core_via_r0(arm11_common_t *arm11,
|
||||
int arm11_run_instr_data_from_core_via_r0(struct arm11_common *arm11,
|
||||
uint32_t opcode, uint32_t *data);
|
||||
int arm11_run_instr_data_to_core_via_r0(arm11_common_t *arm11,
|
||||
int arm11_run_instr_data_to_core_via_r0(struct arm11_common *arm11,
|
||||
uint32_t opcode, uint32_t data);
|
||||
|
||||
int arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields,
|
||||
|
|
@ -56,14 +56,14 @@ typedef struct arm11_sc7_action_s
|
|||
uint32_t value;
|
||||
} arm11_sc7_action_t;
|
||||
|
||||
int arm11_sc7_run(arm11_common_t *arm11,
|
||||
int arm11_sc7_run(struct arm11_common *arm11,
|
||||
arm11_sc7_action_t *actions, size_t count);
|
||||
|
||||
/* Mid-level helper functions */
|
||||
void arm11_sc7_clear_vbw(arm11_common_t *arm11);
|
||||
void arm11_sc7_set_vcr(arm11_common_t *arm11, uint32_t value);
|
||||
void arm11_sc7_clear_vbw(struct arm11_common *arm11);
|
||||
void arm11_sc7_set_vcr(struct arm11_common *arm11, uint32_t value);
|
||||
|
||||
int arm11_read_memory_word(arm11_common_t *arm11,
|
||||
int arm11_read_memory_word(struct arm11_common *arm11,
|
||||
uint32_t address, uint32_t *result);
|
||||
|
||||
#endif // ARM11_DBGTAP_H
|
||||
|
|
|
|||
Loading…
Reference in New Issue