Delete commented out code. Add a bit of error checking.
This commit is contained in:
Øyvind Harboe
parent
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commit
1f917bdc0c
4
TODO
4
TODO
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@ -138,11 +138,9 @@ https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
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- ARM923EJS:
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- reset run/halt/step is not robust; needs testing to map out problems.
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- ARM11 improvements (MB?)
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- add support for asserting srst to reset the core.
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- Single stepping works, but should automatically
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use hardware stepping if available.
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- hunt down and add timeouts to all infinite loops, e.g. arm11_run_instr_no_data would
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lock up in infinite loop if e.g. an "mdh" command tries to read memory from invalid memory location.
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Try mdh 0x40000000 on i.MX31 PDK
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- mdb can return garbage data if read byte operation fails for
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a memory region(16 & 32 byte access modes may be supported). Is this
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a bug in the .MX31 PDK init script? Try on i.MX31 PDK:
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@ -608,6 +608,13 @@ int arm11_leave_debug_state(arm11_common_t * arm11)
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if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
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{
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/*
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The wDTR/rDTR two registers that are used to send/receive data to/from
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the core in tandem with corresponding instruction codes that are
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written into the core. The RDTR FULL/WDTR FULL flag indicates that the
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registers hold data that was written by one side (CPU or JTAG) and not
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read out by the other side.
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*/
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LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
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return ERROR_FAIL;
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}
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@ -702,9 +709,6 @@ int arm11_poll(struct target_s *target)
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arm11_common_t * arm11 = target->arch_info;
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if (arm11->trst_active)
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return ERROR_OK;
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uint32_t dscr;
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CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
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@ -784,12 +788,6 @@ int arm11_halt(struct target_s *target)
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return ERROR_OK;
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}
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if (arm11->trst_active)
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{
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arm11->halt_requested = true;
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return ERROR_OK;
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}
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arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
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CHECK_RETVAL(jtag_execute_queue());
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@ -1199,22 +1197,16 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl
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return ERROR_OK;
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}
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/* target reset control */
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int arm11_assert_reset(struct target_s *target)
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int arm11_assert_reset(target_t *target)
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{
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FNC_INFO;
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#if 0
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/* assert reset lines */
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/* resets only the DBGTAP, not the ARM */
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jtag_add_reset(1, 0);
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jtag_add_sleep(5000);
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arm11_common_t * arm11 = target->arch_info;
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arm11->trst_active = true;
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#endif
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/* FIX! we really should assert srst here, but
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* how do we reset the target into the halted state?
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*
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* Also arm11 behaves "funny" when srst is asserted
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* (as of writing the rules are not understood).
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*/
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if (target->reset_halt)
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{
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CHECK_RETVAL(target_halt(target));
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@ -1223,25 +1215,8 @@ int arm11_assert_reset(struct target_s *target)
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return ERROR_OK;
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}
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int arm11_deassert_reset(struct target_s *target)
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int arm11_deassert_reset(target_t *target)
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{
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FNC_INFO;
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#if 0
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LOG_DEBUG("target->state: %s",
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target_state_name(target));
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/* deassert reset lines */
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jtag_add_reset(0, 0);
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arm11_common_t * arm11 = target->arch_info;
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arm11->trst_active = false;
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if (arm11->halt_requested)
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return arm11_halt(target);
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#endif
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return ERROR_OK;
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}
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@ -1807,6 +1782,8 @@ int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target
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/* talk to the target and set things up */
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int arm11_examine(struct target_s *target)
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{
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int retval;
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FNC_INFO;
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arm11_common_t * arm11 = target->arch_info;
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@ -1874,7 +1851,9 @@ int arm11_examine(struct target_s *target)
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* as suggested by the spec.
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*/
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arm11_check_init(arm11, NULL);
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retval = arm11_check_init(arm11, NULL);
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if (retval != ERROR_OK)
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return retval;
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target_set_examined(target);
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@ -98,10 +98,6 @@ typedef struct arm11_common_s
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uint32_t last_dscr; /**< Last retrieved DSCR value;
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Use only for debug message generation */
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bool trst_active;
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bool halt_requested; /**< Keep track if arm11_halt() calls occured
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during reset. Otherwise do it ASAP. */
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bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
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/** \name Shadow registers to save processor state */
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