Cortex-A8: use the new inheritance/nesting scheme
Use target_to_armv7a() etc, replacing needless pointer traversals. Stop using X->arch_info scheme in most ARMv7-A and Cortex-A8 code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
parent
fec3c4763a
commit
a81df55f39
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@ -176,10 +176,7 @@ reg_t armv7a_gdb_dummy_fp_reg =
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void armv7a_show_fault_registers(target_t *target)
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{
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uint32_t dfsr, ifsr, dfar, ifar;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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armv7a->read_cp15(target, 0, 0, 5, 0, &dfsr);
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armv7a->read_cp15(target, 0, 1, 5, 0, &ifsr);
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@ -200,8 +197,8 @@ int armv7a_arch_state(struct target_s *target)
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"disabled", "enabled"
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};
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
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if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
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{
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@ -237,8 +234,7 @@ static int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc)
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{
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target_t *target = get_current_target(cmd_ctx);
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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return dap_baseaddr_command(cmd_ctx, swjdp, args, argc);
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@ -248,8 +244,7 @@ static int handle_dap_memaccess_command(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc)
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{
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target_t *target = get_current_target(cmd_ctx);
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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return dap_memaccess_command(cmd_ctx, swjdp, args, argc);
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@ -259,8 +254,7 @@ static int handle_dap_apsel_command(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc)
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{
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target_t *target = get_current_target(cmd_ctx);
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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return dap_apsel_command(cmd_ctx, swjdp, args, argc);
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@ -270,8 +264,7 @@ static int handle_dap_apid_command(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc)
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{
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target_t *target = get_current_target(cmd_ctx);
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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return dap_apid_command(cmd_ctx, swjdp, args, argc);
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@ -281,8 +274,7 @@ static int handle_dap_info_command(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc)
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{
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target_t *target = get_current_target(cmd_ctx);
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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uint32_t apsel;
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@ -305,7 +297,7 @@ handle_armv7a_disassemble_command(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc)
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{
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target_t *target = get_current_target(cmd_ctx);
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armv4_5_common_t *armv4_5 = target->arch_info;
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struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
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int thumb = 0;
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int count = 1;
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uint32_t address;
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@ -342,7 +334,7 @@ handle_armv7a_disassemble_command(struct command_context_s *cmd_ctx,
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default:
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usage:
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command_print(cmd_ctx,
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"usage: armv4_5 disassemble <address> [<count> ['thumb']]");
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"usage: armv7a disassemble <address> [<count> ['thumb']]");
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return ERROR_OK;
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}
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@ -107,7 +107,6 @@ typedef struct armv7a_common_s
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/* Cache and Memory Management Unit */
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armv4_5_mmu_common_t armv4_5_mmu;
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armv4_5_common_t armv4_5_common;
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void *arch_info;
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// int (*full_context)(struct target_s *target);
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// int (*read_core_reg)(struct target_s *target, int num, enum armv7a_mode mode);
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@ -128,9 +128,7 @@ target_type_t cortexa8_target =
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*/
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int cortex_a8_init_debug_access(target_t *target)
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{
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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int retval;
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@ -160,9 +158,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
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{
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uint32_t dscr;
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int retval;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
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@ -203,9 +199,7 @@ int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address,
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uint32_t * regfile)
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{
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int retval = ERROR_OK;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
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@ -222,9 +216,7 @@ int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP,
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uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
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{
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int retval;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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cortex_a8_exec_opcode(target, ARMV4_5_MRC(CP, op1, 0, CRn, CRm, op2));
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@ -243,10 +235,7 @@ int cortex_a8_write_cp(target_t *target, uint32_t value,
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{
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int retval;
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uint32_t dscr;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value);
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@ -310,10 +299,7 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
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int retval = ERROR_OK;
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uint8_t reg = regnum&0xFF;
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uint32_t dscr;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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if (reg > 16)
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@ -354,10 +340,7 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r
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int retval = ERROR_OK;
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uint8_t Rd = regnum&0xFF;
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uint32_t dscr;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
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@ -404,10 +387,7 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r
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int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t address, uint32_t value)
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{
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int retval;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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retval = mem_ap_write_atomic_u32(swjdp, address, value);
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@ -423,16 +403,12 @@ int cortex_a8_poll(target_t *target)
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{
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int retval = ERROR_OK;
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uint32_t dscr;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
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struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
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struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common;
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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enum target_state prev_target_state = target->state;
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uint8_t saved_apsel = dap_ap_get_select(swjdp);
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dap_ap_select(swjdp, swjdp_debugap);
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retval = mem_ap_read_atomic_u32(swjdp,
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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@ -492,12 +468,8 @@ int cortex_a8_halt(target_t *target)
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{
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int retval = ERROR_OK;
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uint32_t dscr;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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uint8_t saved_apsel = dap_ap_get_select(swjdp);
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dap_ap_select(swjdp, swjdp_debugap);
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@ -533,9 +505,8 @@ out:
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int cortex_a8_resume(struct target_s *target, int current,
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uint32_t address, int handle_breakpoints, int debug_execution)
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{
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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// breakpoint_t *breakpoint = NULL;
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@ -658,11 +629,9 @@ int cortex_a8_debug_entry(target_t *target)
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uint32_t regfile[16], pc, cpsr, dscr;
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int retval = ERROR_OK;
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working_area_t *regfile_working_area = NULL;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
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struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
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@ -785,10 +754,8 @@ int cortex_a8_debug_entry(target_t *target)
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void cortex_a8_post_debug_entry(target_t *target)
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{
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
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struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
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struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common;
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// cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
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/* examine cp15 control reg */
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@ -820,9 +787,8 @@ void cortex_a8_post_debug_entry(target_t *target)
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int cortex_a8_step(struct target_s *target, int current, uint32_t address,
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int handle_breakpoints)
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{
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
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breakpoint_t *breakpoint = NULL;
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breakpoint_t stepbreakpoint;
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@ -901,10 +867,8 @@ int cortex_a8_restore_context(target_t *target)
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{
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int i;
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uint32_t value;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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struct armv7a_common_s *armv7a = target_to_armv7a(target);
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struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
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LOG_DEBUG(" ");
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@ -939,8 +903,7 @@ int cortex_a8_load_core_reg_u32(struct target_s *target, int num,
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armv4_5_mode_t mode, uint32_t * value)
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{
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int retval;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
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if ((num <= ARM_CPSR))
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{
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@ -978,9 +941,7 @@ int cortex_a8_store_core_reg_u32(struct target_s *target, int num,
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{
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int retval;
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// uint32_t reg;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
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#ifdef ARMV7_GDB_HACKS
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/* If the LR register is being modified, make sure it will put us
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@ -1021,7 +982,8 @@ int cortex_a8_read_core_reg(struct target_s *target, int num,
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{
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uint32_t value;
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int retval;
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armv4_5_common_t *armv4_5 = target->arch_info;
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struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
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cortex_a8_dap_read_coreregister_u32(target, &value, num);
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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@ -1041,7 +1003,7 @@ int cortex_a8_write_core_reg(struct target_s *target, int num,
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enum armv4_5_mode mode, uint32_t value)
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{
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int retval;
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armv4_5_common_t *armv4_5 = target->arch_info;
|
||||
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
|
||||
|
||||
cortex_a8_dap_write_coreregister_u32(target, value, num);
|
||||
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
||||
|
|
@ -1068,12 +1030,8 @@ int cortex_a8_set_breakpoint(struct target_s *target,
|
|||
int brp_i=0;
|
||||
uint32_t control;
|
||||
uint8_t byte_addr_select = 0x0F;
|
||||
|
||||
|
||||
/* get pointers to arch-specific information */
|
||||
armv4_5_common_t *armv4_5 = target->arch_info;
|
||||
armv7a_common_t *armv7a = armv4_5->arch_info;
|
||||
cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
|
||||
struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
|
||||
struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common;
|
||||
cortex_a8_brp_t * brp_list = cortex_a8->brp_list;
|
||||
|
||||
if (breakpoint->set)
|
||||
|
|
@ -1143,10 +1101,8 @@ int cortex_a8_set_breakpoint(struct target_s *target,
|
|||
int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
|
||||
{
|
||||
int retval;
|
||||
/* get pointers to arch-specific information */
|
||||
armv4_5_common_t *armv4_5 = target->arch_info;
|
||||
armv7a_common_t *armv7a = armv4_5->arch_info;
|
||||
cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
|
||||
struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
|
||||
struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common;
|
||||
cortex_a8_brp_t * brp_list = cortex_a8->brp_list;
|
||||
|
||||
if (!breakpoint->set)
|
||||
|
|
@ -1202,10 +1158,7 @@ int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint
|
|||
|
||||
int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
|
||||
{
|
||||
/* get pointers to arch-specific information */
|
||||
armv4_5_common_t *armv4_5 = target->arch_info;
|
||||
armv7a_common_t *armv7a = armv4_5->arch_info;
|
||||
cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
|
||||
struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
|
||||
|
||||
if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1))
|
||||
{
|
||||
|
|
@ -1222,10 +1175,7 @@ int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
|
|||
|
||||
int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
|
||||
{
|
||||
/* get pointers to arch-specific information */
|
||||
armv4_5_common_t *armv4_5 = target->arch_info;
|
||||
armv7a_common_t *armv7a = armv4_5->arch_info;
|
||||
cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
|
||||
struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
|
||||
|
||||
#if 0
|
||||
/* It is perfectly possible to remove brakpoints while the taget is running */
|
||||
|
|
@ -1291,9 +1241,7 @@ int cortex_a8_deassert_reset(target_t *target)
|
|||
int cortex_a8_read_memory(struct target_s *target, uint32_t address,
|
||||
uint32_t size, uint32_t count, uint8_t *buffer)
|
||||
{
|
||||
/* get pointers to arch-specific information */
|
||||
armv4_5_common_t *armv4_5 = target->arch_info;
|
||||
armv7a_common_t *armv7a = armv4_5->arch_info;
|
||||
struct armv7a_common_s *armv7a = target_to_armv7a(target);
|
||||
swjdp_common_t *swjdp = &armv7a->swjdp_info;
|
||||
|
||||
int retval = ERROR_OK;
|
||||
|
|
@ -1328,9 +1276,7 @@ int cortex_a8_read_memory(struct target_s *target, uint32_t address,
|
|||
int cortex_a8_write_memory(struct target_s *target, uint32_t address,
|
||||
uint32_t size, uint32_t count, uint8_t *buffer)
|
||||
{
|
||||
/* get pointers to arch-specific information */
|
||||
armv4_5_common_t *armv4_5 = target->arch_info;
|
||||
armv7a_common_t *armv7a = armv4_5->arch_info;
|
||||
struct armv7a_common_s *armv7a = target_to_armv7a(target);
|
||||
swjdp_common_t *swjdp = &armv7a->swjdp_info;
|
||||
|
||||
int retval;
|
||||
|
|
@ -1416,11 +1362,9 @@ int cortex_a8_handle_target_request(void *priv)
|
|||
target_t *target = priv;
|
||||
if (!target->type->examined)
|
||||
return ERROR_OK;
|
||||
armv4_5_common_t *armv4_5 = target->arch_info;
|
||||
armv7a_common_t *armv7a = armv4_5->arch_info;
|
||||
struct armv7a_common_s *armv7a = target_to_armv7a(target);
|
||||
swjdp_common_t *swjdp = &armv7a->swjdp_info;
|
||||
|
||||
|
||||
if (!target->dbg_msg_enabled)
|
||||
return ERROR_OK;
|
||||
|
||||
|
|
@ -1457,13 +1401,9 @@ int cortex_a8_handle_target_request(void *priv)
|
|||
|
||||
int cortex_a8_examine(struct target_s *target)
|
||||
{
|
||||
/* get pointers to arch-specific information */
|
||||
armv4_5_common_t *armv4_5 = target->arch_info;
|
||||
armv7a_common_t *armv7a = armv4_5->arch_info;
|
||||
cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
|
||||
struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
|
||||
struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common;
|
||||
swjdp_common_t *swjdp = &armv7a->swjdp_info;
|
||||
|
||||
|
||||
int i;
|
||||
int retval = ERROR_OK;
|
||||
uint32_t didr, ctypr, ttypr, cpuid;
|
||||
|
|
@ -1559,8 +1499,7 @@ int cortex_a8_examine(struct target_s *target)
|
|||
void cortex_a8_build_reg_cache(target_t *target)
|
||||
{
|
||||
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
|
||||
/* get pointers to arch-specific information */
|
||||
armv4_5_common_t *armv4_5 = target->arch_info;
|
||||
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
|
||||
|
||||
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
|
||||
armv4_5->core_cache = (*cache_p);
|
||||
|
|
@ -1586,8 +1525,6 @@ int cortex_a8_init_arch_info(target_t *target,
|
|||
|
||||
/* Setup cortex_a8_common_t */
|
||||
cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
|
||||
cortex_a8->arch_info = NULL;
|
||||
armv7a->arch_info = cortex_a8;
|
||||
armv4_5->arch_info = armv7a;
|
||||
|
||||
armv4_5_init_arch_info(target, armv4_5);
|
||||
|
|
@ -1656,8 +1593,7 @@ static int cortex_a8_handle_cache_info_command(struct command_context_s *cmd_ctx
|
|||
char *cmd, char **args, int argc)
|
||||
{
|
||||
target_t *target = get_current_target(cmd_ctx);
|
||||
armv4_5_common_t *armv4_5 = target->arch_info;
|
||||
armv7a_common_t *armv7a = armv4_5->arch_info;
|
||||
struct armv7a_common_s *armv7a = target_to_armv7a(target);
|
||||
|
||||
return armv4_5_handle_cache_info_command(cmd_ctx,
|
||||
&armv7a->armv4_5_mmu.armv4_5_cache);
|
||||
|
|
|
|||
|
|
@ -134,7 +134,6 @@ typedef struct cortex_a8_common_s
|
|||
int fast_reg_read;
|
||||
|
||||
armv7a_common_t armv7a_common;
|
||||
void *arch_info;
|
||||
} cortex_a8_common_t;
|
||||
|
||||
static inline struct cortex_a8_common_s *
|
||||
|
|
|
|||
Loading…
Reference in New Issue