Start cleaning up ETM register handling. On one ARM926 ETM+ETB
system, removes 20 non-existent registers ... but still includes
over 45 (!) ETM registers which don't even exist there ...
- Integrate the various tables to get one struct per register
- Get rid of needless per-register dynamic allocation
- Double check list of registers:
* Remove sixteen (!) non-registers for data comparators
* Remove four registers that imply newer ETM than we support
* Change some names to match current architecture specs
- Handle more register info
* some are write-only
* some are read-only
* record which versions have them, just in case
- Reorganize the registers to facilitate removing the extras
* group e.g. comparator/counter #N registers together
* add and use lookup-by-ID
git-svn-id: svn://svn.berlios.de/openocd/trunk@2751 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
dbrownell
parent
a6d858ebcd
commit
d9ce8a2f60
320
src/target/etm.c
320
src/target/etm.c
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@ -50,155 +50,145 @@
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* ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
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*/
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static int etm_reg_arch_info[] =
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{
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
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0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
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0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
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0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
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0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
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0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
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0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
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0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
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0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
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0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
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0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
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0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
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0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
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0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
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#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
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enum {
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RO, /* read/only */
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WO, /* write/only */
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RW, /* read/write */
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};
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static int etm_reg_arch_size_info[] =
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{
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32, 32, 17, 8, 3, 9, 32, 16,
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17, 26, 25, 8, 17, 32, 32, 17,
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32, 32, 32, 32, 32, 32, 32, 32,
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32, 32, 32, 32, 32, 32, 32, 32,
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7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7,
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32, 32, 32, 32, 32, 32, 32, 32,
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32, 32, 32, 32, 32, 32, 32, 32,
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32, 32, 32, 32, 32, 32, 32, 32,
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32, 32, 32, 32, 32, 32, 32, 32,
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16, 16, 16, 16, 18, 18, 18, 18,
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17, 17, 17, 17, 16, 16, 16, 16,
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17, 17, 17, 17, 17, 17, 2,
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17, 17, 17, 17, 32, 32, 32, 32
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struct etm_reg_info {
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uint8_t addr;
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uint8_t size; /* low-N of 32 bits */
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uint8_t mode; /* RO, WO, RW */
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uint8_t bcd_vers; /* 1.0, 2.0, etc */
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char *name;
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};
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static char* etm_reg_list[] =
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{
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"ETM_CTRL",
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"ETM_CONFIG",
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"ETM_TRIG_EVENT",
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"ETM_MMD_CTRL",
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"ETM_STATUS",
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"ETM_SYS_CONFIG",
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"ETM_TRACE_RESOURCE_CTRL",
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"ETM_TRACE_EN_CTRL2",
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"ETM_TRACE_EN_EVENT",
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"ETM_TRACE_EN_CTRL1",
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"ETM_FIFOFULL_REGION",
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"ETM_FIFOFULL_LEVEL",
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"ETM_VIEWDATA_EVENT",
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"ETM_VIEWDATA_CTRL1",
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"ETM_VIEWDATA_CTRL2",
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"ETM_VIEWDATA_CTRL3",
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"ETM_ADDR_COMPARATOR_VALUE1",
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"ETM_ADDR_COMPARATOR_VALUE2",
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"ETM_ADDR_COMPARATOR_VALUE3",
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"ETM_ADDR_COMPARATOR_VALUE4",
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"ETM_ADDR_COMPARATOR_VALUE5",
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"ETM_ADDR_COMPARATOR_VALUE6",
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"ETM_ADDR_COMPARATOR_VALUE7",
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"ETM_ADDR_COMPARATOR_VALUE8",
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"ETM_ADDR_COMPARATOR_VALUE9",
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"ETM_ADDR_COMPARATOR_VALUE10",
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"ETM_ADDR_COMPARATOR_VALUE11",
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"ETM_ADDR_COMPARATOR_VALUE12",
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"ETM_ADDR_COMPARATOR_VALUE13",
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"ETM_ADDR_COMPARATOR_VALUE14",
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"ETM_ADDR_COMPARATOR_VALUE15",
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"ETM_ADDR_COMPARATOR_VALUE16",
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"ETM_ADDR_ACCESS_TYPE1",
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"ETM_ADDR_ACCESS_TYPE2",
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"ETM_ADDR_ACCESS_TYPE3",
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"ETM_ADDR_ACCESS_TYPE4",
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"ETM_ADDR_ACCESS_TYPE5",
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"ETM_ADDR_ACCESS_TYPE6",
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"ETM_ADDR_ACCESS_TYPE7",
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"ETM_ADDR_ACCESS_TYPE8",
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"ETM_ADDR_ACCESS_TYPE9",
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"ETM_ADDR_ACCESS_TYPE10",
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"ETM_ADDR_ACCESS_TYPE11",
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"ETM_ADDR_ACCESS_TYPE12",
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"ETM_ADDR_ACCESS_TYPE13",
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"ETM_ADDR_ACCESS_TYPE14",
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"ETM_ADDR_ACCESS_TYPE15",
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"ETM_ADDR_ACCESS_TYPE16",
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"ETM_DATA_COMPARATOR_VALUE1",
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"ETM_DATA_COMPARATOR_VALUE2",
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"ETM_DATA_COMPARATOR_VALUE3",
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"ETM_DATA_COMPARATOR_VALUE4",
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"ETM_DATA_COMPARATOR_VALUE5",
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"ETM_DATA_COMPARATOR_VALUE6",
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"ETM_DATA_COMPARATOR_VALUE7",
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"ETM_DATA_COMPARATOR_VALUE8",
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"ETM_DATA_COMPARATOR_VALUE9",
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"ETM_DATA_COMPARATOR_VALUE10",
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"ETM_DATA_COMPARATOR_VALUE11",
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"ETM_DATA_COMPARATOR_VALUE12",
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"ETM_DATA_COMPARATOR_VALUE13",
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"ETM_DATA_COMPARATOR_VALUE14",
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"ETM_DATA_COMPARATOR_VALUE15",
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"ETM_DATA_COMPARATOR_VALUE16",
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"ETM_DATA_COMPARATOR_MASK1",
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"ETM_DATA_COMPARATOR_MASK2",
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"ETM_DATA_COMPARATOR_MASK3",
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"ETM_DATA_COMPARATOR_MASK4",
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"ETM_DATA_COMPARATOR_MASK5",
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"ETM_DATA_COMPARATOR_MASK6",
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"ETM_DATA_COMPARATOR_MASK7",
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"ETM_DATA_COMPARATOR_MASK8",
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"ETM_DATA_COMPARATOR_MASK9",
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"ETM_DATA_COMPARATOR_MASK10",
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"ETM_DATA_COMPARATOR_MASK11",
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"ETM_DATA_COMPARATOR_MASK12",
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"ETM_DATA_COMPARATOR_MASK13",
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"ETM_DATA_COMPARATOR_MASK14",
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"ETM_DATA_COMPARATOR_MASK15",
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"ETM_DATA_COMPARATOR_MASK16",
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"ETM_COUNTER_INITAL_VALUE1",
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"ETM_COUNTER_INITAL_VALUE2",
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"ETM_COUNTER_INITAL_VALUE3",
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"ETM_COUNTER_INITAL_VALUE4",
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"ETM_COUNTER_ENABLE1",
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"ETM_COUNTER_ENABLE2",
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"ETM_COUNTER_ENABLE3",
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"ETM_COUNTER_ENABLE4",
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"ETM_COUNTER_RELOAD_VALUE1",
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"ETM_COUNTER_RELOAD_VALUE2",
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"ETM_COUNTER_RELOAD_VALUE3",
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"ETM_COUNTER_RELOAD_VALUE4",
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"ETM_COUNTER_VALUE1",
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"ETM_COUNTER_VALUE2",
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"ETM_COUNTER_VALUE3",
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"ETM_COUNTER_VALUE4",
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"ETM_SEQUENCER_CTRL1",
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"ETM_SEQUENCER_CTRL2",
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"ETM_SEQUENCER_CTRL3",
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"ETM_SEQUENCER_CTRL4",
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"ETM_SEQUENCER_CTRL5",
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"ETM_SEQUENCER_CTRL6",
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"ETM_SEQUENCER_STATE",
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"ETM_EXTERNAL_OUTPUT1",
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"ETM_EXTERNAL_OUTPUT2",
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"ETM_EXTERNAL_OUTPUT3",
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"ETM_EXTERNAL_OUTPUT4",
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"ETM_CONTEXTID_COMPARATOR_VALUE1",
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"ETM_CONTEXTID_COMPARATOR_VALUE2",
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"ETM_CONTEXTID_COMPARATOR_VALUE3",
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"ETM_CONTEXTID_COMPARATOR_MASK"
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/*
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* Registers 0..0x7f are JTAG-addressable using scanchain 6.
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* Newer versions of ETM make some W/O registers R/W, and
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* provide definitions for some previously-unused bits.
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*/
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static const struct etm_reg_info reg[] = {
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/* ETM Trace Registers */
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{ ETM_CTRL, 32, RW, 0x10, "ETM_CTRL", },
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{ ETM_CONFIG, 32, RO, 0x10, "ETM_CONFIG", },
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{ ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_TRIG_EVENT", },
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{ ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_ASIC_CTRL", },
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{ ETM_STATUS, 3, RO, 0x11, "ETM_STATUS", },
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{ ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_SYS_CONFIG", },
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/* TraceEnable configuration */
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{ ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_TRACE_RESOURCE_CTRL", },
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{ ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_TRACE_EN_CTRL2", },
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{ ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_TRACE_EN_EVENT", },
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{ ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_TRACE_EN_CTRL1", },
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/* FIFOFULL configuration */
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{ ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_FIFOFULL_REGION", },
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{ ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_FIFOFULL_LEVEL", },
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/* ViewData configuration (data trace) */
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{ ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_VIEWDATA_EVENT", },
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{ ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_VIEWDATA_CTRL1", },
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{ ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_VIEWDATA_CTRL2", },
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{ ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_VIEWDATA_CTRL3", },
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/* Address comparator register pairs */
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#define ADDR_COMPARATOR(i) \
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{ ETM_ADDR_COMPARATOR_VALUE + (i), 32, WO, 0x10, \
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"ETM_ADDR_COMPARATOR_VALUE" #i, }, \
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{ ETM_ADDR_ACCESS_TYPE + (i), 7, WO, 0x10, \
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"ETM_ADDR_ACCESS_TYPE" #i, }
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ADDR_COMPARATOR(0),
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ADDR_COMPARATOR(1),
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ADDR_COMPARATOR(2),
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ADDR_COMPARATOR(3),
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ADDR_COMPARATOR(4),
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ADDR_COMPARATOR(5),
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ADDR_COMPARATOR(6),
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ADDR_COMPARATOR(7),
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ADDR_COMPARATOR(8),
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ADDR_COMPARATOR(9),
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ADDR_COMPARATOR(10),
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ADDR_COMPARATOR(11),
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ADDR_COMPARATOR(12),
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ADDR_COMPARATOR(13),
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ADDR_COMPARATOR(14),
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ADDR_COMPARATOR(15),
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#undef ADDR_COMPARATOR
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/* Data Value Comparators (NOTE: odd addresses are reserved) */
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#define DATA_COMPARATOR(i) \
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{ ETM_DATA_COMPARATOR_VALUE + 2*(i), 32, WO, 0x10, \
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"ETM_DATA_COMPARATOR_VALUE" #i, }, \
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{ ETM_DATA_COMPARATOR_MASK + 2*(i), 32, WO, 0x10, \
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"ETM_DATA_COMPARATOR_MASK" #i, }
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DATA_COMPARATOR(0),
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DATA_COMPARATOR(1),
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DATA_COMPARATOR(2),
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DATA_COMPARATOR(3),
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DATA_COMPARATOR(4),
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DATA_COMPARATOR(5),
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DATA_COMPARATOR(6),
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DATA_COMPARATOR(7),
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#undef DATA_COMPARATOR
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/* Counters */
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#define COUNTER(i) \
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{ ETM_COUNTER_RELOAD_VALUE + (i), 16, WO, 0x10, \
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"ETM_COUNTER_RELOAD_VALUE" #i, }, \
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{ ETM_COUNTER_ENABLE + (i), 18, WO, 0x10, \
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"ETM_COUNTER_ENABLE" #i, }, \
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{ ETM_COUNTER_RELOAD_EVENT + (i), 17, WO, 0x10, \
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"ETM_COUNTER_RELOAD_EVENT" #i, }, \
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{ ETM_COUNTER_VALUE + (i), 16, RO, 0x10, \
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"ETM_COUNTER_VALUE" #i, }
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COUNTER(0),
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COUNTER(1),
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COUNTER(2),
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COUNTER(3),
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#undef COUNTER
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/* Sequencers */
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#define SEQ(i) \
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{ ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
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"ETM_SEQUENCER_EVENT" #i, }
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SEQ(0), /* 1->2 */
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SEQ(1), /* 2->1 */
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SEQ(2), /* 2->3 */
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SEQ(3), /* 3->1 */
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SEQ(4), /* 3->2 */
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SEQ(5), /* 1->3 */
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#undef SEQ
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/* 0x66 reserved */
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{ ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_SEQUENCER_STATE", },
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#define OUT(i) \
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{ ETM_EXTERNAL_OUTPUT + (i), 17, WO, 0x10, \
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"ETM_EXTERNAL_OUTPUT" #i, }
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OUT(0),
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OUT(1),
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OUT(2),
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OUT(3),
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#undef OUT
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#if 0
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/* registers from 0x6c..0x7f were added after ETMv1.3 */
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/* Context ID Comparators */
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{ 0x6c, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
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{ 0x6d, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
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{ 0x6e, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
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{ 0x6f, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_MASK", }
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{ 0x78, 12, WO, 0x20, "ETM_SYNC_FREQ", },
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{ 0x79, 32, RO, 0x20, "ETM_ID", },
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#endif
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};
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static int etm_reg_arch_type = -1;
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@ -224,7 +214,7 @@ static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
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for (i = 0; i < cache->num_regs; i++) {
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struct etm_reg_s *reg = cache->reg_list[i].arch_info;
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if (reg->addr == (int) id)
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if (reg->reg_info->addr == id)
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return &cache->reg_list[i];
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}
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@ -240,7 +230,7 @@ reg_cache_t *etm_build_reg_cache(target_t *target,
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reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
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reg_t *reg_list = NULL;
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etm_reg_t *arch_info = NULL;
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int num_regs = sizeof(etm_reg_arch_info)/sizeof(int);
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int num_regs = ARRAY_SIZE(reg);
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int i;
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/* register a register arch-type for etm registers only once */
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@ -260,13 +250,15 @@ reg_cache_t *etm_build_reg_cache(target_t *target,
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/* set up registers */
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for (i = 0; i < num_regs; i++)
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{
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reg_list[i].name = etm_reg_list[i];
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reg_list[i].size = 32;
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reg_list[i].value = calloc(1, 4);
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const struct etm_reg_info *r = reg + i;
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reg_list[i].name = r->name;
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reg_list[i].size = r->size;
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reg_list[i].value = &arch_info[i].value;
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reg_list[i].arch_info = &arch_info[i];
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reg_list[i].arch_type = etm_reg_arch_type;
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reg_list[i].size = etm_reg_arch_size_info[i];
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arch_info[i].addr = etm_reg_arch_info[i];
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arch_info[i].reg_info = r;
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arch_info[i].jtag_info = jtag_info;
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}
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@ -278,10 +270,6 @@ reg_cache_t *etm_build_reg_cache(target_t *target,
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if (!etb)
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{
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LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
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for (i = 0; i < num_regs; i++)
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{
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free(reg_list[i].value);
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}
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free(reg_cache);
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free(arch_info);
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return ERROR_OK;
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@ -368,10 +356,16 @@ static int etm_read_reg_w_check(reg_t *reg,
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uint8_t* check_value, uint8_t* check_mask)
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{
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etm_reg_t *etm_reg = reg->arch_info;
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uint8_t reg_addr = etm_reg->addr & 0x7f;
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const struct etm_reg_info *r = etm_reg->reg_info;
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uint8_t reg_addr = r->addr & 0x7f;
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scan_field_t fields[3];
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LOG_DEBUG("%i", etm_reg->addr);
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if (etm_reg->reg_info->mode == WO) {
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LOG_ERROR("BUG: can't read write-only register %s", r->name);
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return ERROR_INVALID_ARGUMENTS;
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}
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LOG_DEBUG("%s (%u)", r->name, reg_addr);
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jtag_set_end_state(TAP_IDLE);
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arm_jtag_scann(etm_reg->jtag_info, 0x6);
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@ -448,10 +442,16 @@ static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
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static int etm_write_reg(reg_t *reg, uint32_t value)
|
||||
{
|
||||
etm_reg_t *etm_reg = reg->arch_info;
|
||||
uint8_t reg_addr = etm_reg->addr & 0x7f;
|
||||
const struct etm_reg_info *r = etm_reg->reg_info;
|
||||
uint8_t reg_addr = r->addr & 0x7f;
|
||||
scan_field_t fields[3];
|
||||
|
||||
LOG_DEBUG("%i: 0x%8.8" PRIx32 "", etm_reg->addr, value);
|
||||
if (etm_reg->reg_info->mode == RO) {
|
||||
LOG_ERROR("BUG: can't write read--only register %s", r->name);
|
||||
return ERROR_INVALID_ARGUMENTS;
|
||||
}
|
||||
|
||||
LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
|
||||
|
||||
jtag_set_end_state(TAP_IDLE);
|
||||
arm_jtag_scann(etm_reg->jtag_info, 0x6);
|
||||
|
|
|
|||
|
|
@ -29,43 +29,52 @@
|
|||
|
||||
struct image_s;
|
||||
|
||||
/* ETM registers (V1.3 protocol) */
|
||||
/* ETM registers (JTAG protocol) */
|
||||
enum
|
||||
{
|
||||
ETM_CTRL = 0x00,
|
||||
ETM_CONFIG = 0x01,
|
||||
ETM_TRIG_EVENT = 0x02,
|
||||
ETM_MMD_CTRL = 0x03,
|
||||
ETM_ASIC_CTRL = 0x03,
|
||||
ETM_STATUS = 0x04,
|
||||
ETM_SYS_CONFIG = 0x05,
|
||||
ETM_TRACE_RESOURCE_CTRL = 0x06,
|
||||
ETM_TRACE_EN_CTRL2 = 0x07,
|
||||
ETM_TRACE_EN_EVENT = 0x08,
|
||||
ETM_TRACE_EN_CTRL1 = 0x09,
|
||||
/* optional FIFOFULL */
|
||||
ETM_FIFOFULL_REGION = 0x0a,
|
||||
ETM_FIFOFULL_LEVEL = 0x0b,
|
||||
/* viewdata support */
|
||||
ETM_VIEWDATA_EVENT = 0x0c,
|
||||
ETM_VIEWDATA_CTRL1 = 0x0d,
|
||||
ETM_VIEWDATA_CTRL2 = 0x0e,
|
||||
ETM_VIEWDATA_CTRL2 = 0x0e, /* optional */
|
||||
ETM_VIEWDATA_CTRL3 = 0x0f,
|
||||
/* N pairs of ADDR_{COMPARATOR,ACCESS} registers */
|
||||
ETM_ADDR_COMPARATOR_VALUE = 0x10,
|
||||
ETM_ADDR_ACCESS_TYPE = 0x20,
|
||||
/* N pairs of DATA_COMPARATOR_{VALUE,MASK} registers */
|
||||
ETM_DATA_COMPARATOR_VALUE = 0x30,
|
||||
ETM_DATA_COMPARATOR_MASK = 0x40,
|
||||
ETM_COUNTER_INITAL_VALUE = 0x50,
|
||||
/* N quads of COUNTER_{RELOAD_{VALUE,EVENT},ENABLE,VALUE} registers */
|
||||
ETM_COUNTER_RELOAD_VALUE = 0x50,
|
||||
ETM_COUNTER_ENABLE = 0x54,
|
||||
ETM_COUNTER_RELOAD_VALUE = 0x58,
|
||||
ETM_COUNTER_RELOAD_EVENT = 0x58,
|
||||
ETM_COUNTER_VALUE = 0x5c,
|
||||
ETM_SEQUENCER_CTRL = 0x60,
|
||||
/* 6 sequencer event transitions */
|
||||
ETM_SEQUENCER_EVENT = 0x60,
|
||||
ETM_SEQUENCER_STATE = 0x67,
|
||||
/* N triggered outputs */
|
||||
ETM_EXTERNAL_OUTPUT = 0x68,
|
||||
/* N task contexts */
|
||||
ETM_CONTEXTID_COMPARATOR_VALUE = 0x6c,
|
||||
ETM_CONTEXTID_COMPARATOR_MASK = 0x6f,
|
||||
};
|
||||
|
||||
typedef struct etm_reg_s
|
||||
{
|
||||
int addr;
|
||||
uint32_t value;
|
||||
const struct etm_reg_info *reg_info;
|
||||
arm_jtag_t *jtag_info;
|
||||
} etm_reg_t;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue