Commit Graph

4047 Commits

Author SHA1 Message Date
Tomas Vanek d7558e2ed6 target/armv7m: fix static analyzer warning
Despite of assert(is_packed) clang static analyser complains on use
of the uninitialized offset variable.

Cross compiling with latest x86_64-w64-mingw32-gcc hits warnings
	src/target/armv7m.c: In function ‘armv7m_read_core_reg’:
	src/target/armv7m.c:337:54: error: ‘reg32_id’ may be used
	    uninitialized in this function [-Werror=maybe-uninitialized]

It happens because mingw32 defines assert() without the attribute
"noreturn", whatever NDEBUG is defined or not.

Replace assert(is_packed) by if (is_packed) conditional and call
assert(false) in the else branch.

Change-Id: Id3c7dcccb65106e28be200b9a4d2b642f4d31019
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/6256
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Andrzej Sierżęga <asier70@gmail.com>
2021-05-18 09:03:28 +01:00
Tim Newsome 10957400c0
Merge pull request #605 from riscv/rtos_riscv
Remove enable_rtos_riscv command.
2021-05-17 12:08:19 -07:00
Antonio Borneo 9bdd1daec3 riscv: replace macro DIM() with ARRAY_SIZE()
OpenOCD already defines the macro ARRAY_SIZE, while riscv code
uses a local macro DIM.

Prefer using the macro ARRAY_SIZE() instead of DIM().
Not all the riscv code has been upstreamed, yes; this patch only
covers the code already upstreamed.

Change-Id: I89a58a6d91916d85c53ba5e4091b558271f8d618
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-16 13:57:11 +02:00
Antonio Borneo 6f5259db05 riscv: prefer ARRAY_SIZE() to DIM()
OpenOCD already defines the macro ARRAY_SIZE, while riscv code
uses a local macro DIM.

Prefer using the macro ARRAY_SIZE() instead of DIM().
Not all the riscv code has been upstreamed, yes; this patch only
covers the code not upstreamed.

Change-Id: Ie3e411280f76bc798f1d51c2574cfec148ee0d0d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-16 13:53:10 +02:00
Antonio Borneo 0944e12232 riscv: drop unused variable
The array newly_halted[] is assigned but its value is never used.
Drop it!

Change-Id: I678812a31c45a3ec03716e3eee6a30b8e8947926
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-16 13:40:55 +02:00
Tarek BOCHKATI d624da96a9 target/armv7m.h: [style] replace tab with space between variable type and name
Change-Id: I9740c25857295a2a655d3046322a3f23f0ee7f78
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6230
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-15 20:56:10 +01:00
Tim Newsome f31c130286 Remote enable_rtos_riscv command.
I'd missed this when that functionality was removed.

Change-Id: If5b697d9dbac517a077d9c1826c747fc95b19f1f
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-05-14 16:32:30 -07:00
Tim Newsome 8fcc19d70b Keep alive when accessing registers.
With the bitbang performance decrease and talking to slower targets
(daisy chain spike) we more often don't meet the expected keepalive time
for gdb. This addresses the cases I ran into.

Change-Id: Ie69c2c602c3be9c156e508fdfa6d0178f104e1d8
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-05-12 11:44:32 -07:00
Tarek BOCHKATI 5d9de1c400 cortex_m: add armv8m special registers
Change-Id: I1942f375a5f4282ad1fe4a2ff3b8f3cbc64d8f7f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6016
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-05-11 06:30:29 +01:00
Marc Schink 40dd1e5284 target/riscv: Change 'authdata_read' output
Use a constant output length and remove the line break to make the
authentication data easier to parse.

Change-Id: Iebbf1f171947ef89b0f360a2cb286a4ea15c6ba5
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6199
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
2021-05-08 09:49:52 +01:00
Marc Schink 167adaf841 target/stm8: Make 'stm8_command_handlers' static
Change-Id: I5237a8f2a1ecba9383672e37bd56f8ccd17598b6
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6200
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-08 09:49:32 +01:00
Antonio Borneo 82b6a41117 startup.tcl: prepare for jimtcl 0.81 'expr' syntax change
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

Modify the script startup.tcl compiled-in OpenOCD binary to comply
with the new jimtcl.

Change-Id: I520dcafacadaa289a815035f93f250447ca66ea0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6158
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-05-08 09:48:36 +01:00
Antonio Borneo 223b79ebe2 telnet/auto-complete: hide deprecated and internal commands
For both:
- TCL proc that redirect deprecated commands to the new commands,
- TCL proc used internally and not supposed to be exposed to user,
add their name to the list of commands that should be hide by the
telnet auto-complete.

Change-Id: I05237c6a79334b7d2b151dfb129fb57b2f40bba6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6195
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-05-08 09:48:15 +01:00
Tarek BOCHKATI 8ecc2888cf cortex_m: use unsigned int for FPB and DWT quantifiers
related quantifiers are:
 - fp_num_lit
 - fp_num_code
 - dwt_num_comp
 - dwt_comp_available

Change-Id: I07dec2d4aa21bc0e580be0d9fd0a6809f876c2a8
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6185
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-05-04 23:13:20 +01:00
Tim Newsome 38eea2367c Add keep_alive() to system bus read loop.
Without it the repeat read test wasn't passing any longer. This is
because 7dd323b26d reduced the remote
bitbang performance. I've notified the mailing list about this.

Change-Id: Ie71592792202423aec89fa889b9e3d2a60a3c25f
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-05-03 14:56:34 -07:00
Tim Newsome 927c4db298 Merge branch 'master' into from_upstream
I may have broken memory sampling with this merge.

Conflicts:
	doc/openocd.texi
	src/helper/command.c
	src/jtag/drivers/ftdi.c
	src/rtos/FreeRTOS.c

Change-Id: I2b7e09b2d3b244db546c5212532e6b48fb66dca4
2021-05-03 11:04:15 -07:00
Tarek BOCHKATI a115b589a7 cortex_m: implement hit_watchpoint function
this change aims to provide a better gdb debugging experience,
by making gdb understand what's really happening.

before this change when hitting a watchpoint
 - openocd reports "T05" to gdb
 - gdb displays: Program received signal SIGTRAP, Trace/breakpoint trap.

after the change
 - openocd reports "T05watch:20000000;" to gdb
 - gdb displays:
   Hardware watchpoint 1: *0x20000000

   Old value = 16000000
   New value = 170000000
   ...

Change-Id: Iac3a85eadd86663617889001dd04513a4211ced9
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6181
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-05-02 22:42:29 +01:00
Tim Newsome 87c90393fe Cleanup of config/includes.
Remove a use of AH_BOTTOM from configure.ac. This macro is used by
autoheader to add '#include' of some include file to the end of
config.h.in and then to config.h. OpenOCD can be built with a custom
config.h, so it's preferable to move these '#include' statement directly
in the C files that need them dropping this unneeded dependency.

It also causes problems when I want to use the gnulib library (which
comes with its own Makefile, and does not have the same include path as
the top-level Makefile).

So this change touches a lot of files, but is actually really simple. It
does not affect functionality at all.

Change-Id: I52c70bf15eb2edc1dd10e0fde23b2bcd4caec000
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/6171
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-01 14:35:09 +01:00
Christian Hoff 565129119f target/image: report error if ELF file contains no loadable sections
The existing code asserted in that case, which is not correct. This
would allow the user to crash OpenOCD with a bad ELF file, which is
not what we want. A proper error should be reported in that case and
OpenOCD should not crash.

Change-Id: Ied5a6a6fd4ee0fd163f3fe850d304a121ecbe33a
Signed-off-by: Christian Hoff <christian.hoff@advantest.com>
Reviewed-on: http://openocd.zylin.com/6172
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-01 13:36:28 +01:00
Florian Meister 9206bd243b target/image: allow loading of 64-bit ELF files
Change-Id: I9b88edacf5ffcc3c1caeab8c426693de0d92a695
Signed-off-by: Florian Meister <florian.meister@advantest.com>
Signed-off-by: Christian Hoff <christian.hoff@advantest.com>
Reviewed-on: http://openocd.zylin.com/5204
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Ooi, Cinly <cinly.ooi@intel.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-05-01 13:36:15 +01:00
Tarek BOCHKATI ef0da79448 cortex_m: mark FPU register as non-existent instead of playing with num_regs
Change-Id: Iac7c5bfbb95c8d9a8c6d65104d138692a44eca78
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6015
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-04-30 08:23:29 +01:00
Tomas Vanek ef0aa38c10 target/armv7m: change FPv4_SP and FPv5_SP/DP identifiers to uppercase
Change-Id: Ia421a973e5fb4767715c9f95c91745f8ca1de1da
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/6177
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-04-30 08:20:54 +01:00
Tomas Vanek ab337d05f4 target/arm_adi_v5: move DP register definitions to one block
DP and MEM-AP definitions were mixed.

Change-Id: I2f691b2274c01e9090c1e5160c6903d3207e35c2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/6138
Tested-by: jenkins
2021-04-25 23:08:49 +01:00
Tomas Vanek 4455469847 target/adi_v5_swd: remove double space from swd_cmd() parameters
Change-Id: I6b68868947010512c4de76e5d37142f067e27b06
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/6137
Tested-by: jenkins
2021-04-25 23:08:41 +01:00
Tomas Vanek 45eff3a806 target/arm_adi_v5: add JTAG_TO_DORMANT sequence
Change-Id: Ie9e32e42a84cf88bf779e691a67c114eef1bb457
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/6136
Tested-by: jenkins
2021-04-25 23:08:19 +01:00
Antonio Borneo 3cacfd86ab smp: move command deprecation to startup.tcl
Commit 246782229f ("smp: replace commands smp_on/smp_off with
"smp [on|off]"") deprecates some multi-word comments, when openocd
was unable to properly handle mixes of multi-word commands and tcl
procedures having a common initial word.
This limitation is over, so move in startup.tcl the multi-word
commands deprecation, making it easy to remove them after a grace
period.

Change-Id: Icb550d1fa7559b95692d2a1244880da6c90ec0b2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5677
Tested-by: jenkins
2021-04-25 23:03:28 +01:00
Antonio Borneo e216186fab helper/command: register full-name commands in jim
While still keeping the tree of struct command, stop registering
commands in jim by the root "word" only.

Register the full-name of the command and pass as private data the
struct command of the command itself.

Still use the tree of struct command to un-register the commands.

Some "native" commands (.jim_handler) share the same handler, then
the handler checks the command name to run the right code.
Now argv[0] returns the full-name of the command, so check the
name by looking in the struct command passed as private data.

Change-Id: I5623c61cceee8a75f5d5a551ef3fbf5a303af6be
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5671
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-04-18 15:34:10 +01:00
Antonio Borneo 41c95aa4ea helper/command: pass command prefix to command registration
Replace the "struct command *parent" parameter with a string that
contains the command prefix.
This abstracts the openocd code from the knowledge of the tree of
struct command.
This also makes unused the function command_find_in_context(), so
remove it.

Change-Id: I598d60719cfdc1811ee6f6edfff8a116f82c7ed6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5668
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-04-18 15:33:30 +01:00
Antonio Borneo 4289389937 helper/command: override target only on target prefixed cmds
In current code the current target is overridden whenever
jim_handler_data is not NULL. This happens not only with target
prefixed commands, but also with cti, dap and swo/tpiu prefixed
commands.
While this is not causing any run-time issue, by now, the
behaviour is tricky and makes the code cryptic.

Add a specific field to struct command for the target override so
the content of jim_handler_data can be restricted to command
specific data only (today only cti, dap and swo/tpiu).

Extend the API register_commands() to specify the presence of
either the command data or the override target.

The new API makes obsolete calling command_set_handler_data() to
set jim_handler_data, so remove it.

Change-Id: Icc323faf754b0546a72208f90abd9e68ff2ef52f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5667
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-04-18 15:33:23 +01:00
Antonio Borneo 7cd679a2de helper/command: get current target from dedicated API
Now that target override is uniformly implemented for all types of
commands, there is no need for target-prefixed "native" commands
(.jim_handler) to sneakily extract the overridden target from the
struct command.

Modify the commands to use the standard API get_current_target().

Change-Id: I732a09c3261e56524edd5217634fa409eb97a8c6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5666
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-04-18 15:33:15 +01:00
Antonio Borneo a510c8e23c helper/command: always pass struct command as jim private data
While registering a new command, jim accepts a pointer to command's
private data that will be accessible during the command execution.

Today openocd is not consistent and passes different private data
depending on the command, and then even overwrites it:
- "simple" commands (.handler) are registered with their own
  struct command pointer as command private data;
- "native" commands (.jim_handler) at root level are registered
  with NULL command private data;
- "native" commands (.jim_handler) not at root level are
  registered with the struct command pointer of their root command
  as command private data but, when executed, the command private
  data is overwritten by the value in field jim_handler_data taken
  from their struct command.

Uniform the usage of command private data by always set it to the
struct command pointer while registering the new commands.
Note: for multi-word commands only the root command is registered,
so command private data will be set to the struct command of the
root command. This will change later in this series when the full-
name of the command will be registered.

Don't overwrite the command private data, but let the commands that
needs jim_handler_data to get it directly through struct command.

For sake of uniformity, let function command_set_handler_data() to
set the field jim_handler_data also for "group" commands, even if
such value will not be used.

Now Jim_CmdPrivData() always returns a struct command pointer, so
wrap it in the inline function jim_to_command() to gain compile
time check on the returned type.
While there, uniform the code to use the macro Jim_CmdPrivData()
to access the command's private data pointer.

Change-Id: Idba16242ba1f6769341b4030a49cdf35a5278695
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5664
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-04-18 15:32:57 +01:00
Cheng-Shiun Tsai a9904ba22c Aarch64:Switch to EL1 from EL0 before manipulate MMU
If current core is in EL0, it cannot use 'msr sctlr_el1, x0'

Change-Id: I04e60e39e4c84f9d9de7cc87a8e438f5d2737dc3
Signed-off-by: Cheng-Shiun Tsai <cheng.shiun.tsai@gmail.com>
Reviewed-on: http://openocd.zylin.com/6051
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2021-04-18 15:32:24 +01:00
Tim Newsome 7420382a4d Merge branch 'master' into from_upstream
Conflicts:
	.github/workflows/snapshot.yml
	NEWS
	configure.ac
	contrib/loaders/checksum/riscv_crc.c
	jimtcl
	src/helper/time_support.h
	src/jtag/drivers/arm-jtag-ew.c
	src/rtos/FreeRTOS.c
	src/target/image.c
	src/target/riscv/riscv.c

Change-Id: I043624ba540d4672fc123dddb2066bcb9c6b5a05
2021-04-13 11:26:25 -07:00
Antonio Borneo 0f06d94336 mem_ap: allow GDB connections
The target mem_ap is a convenient way to access buses, memory and
peripherals behind an ARM AP.
The current implementation provides only access through OpenOCD
commands, because GDB remote protocol has to interact with a CPU
and has to operate on CPU states and registers.
Using GDB to access the memory is welcome, because GDB can resolve
the symbol's address from an ELF file and can nicely display the
content of complex struct and data types.

Extend mem_ap target with the bare minimal support for a remote
GDB connection, by emulating a fake basic ARM core. It means that
only a GDB that has support for ARM can be used (either 'aarch64',
'arm' or 'multiarch' GDB). This is not seen as a big limitation,
because the mem_ap target is mainly used on ARM based devices.

Add a minimalist register description for the fake CPU.
Fill the field 'debug_reason' as expected by GDB server.
Call the target halted event to reply to GDB halt requests.

For backward compatibility, don't open the GDB port by default. If
needed, it has to be specified at 'target create' or 'configure'
with the flag '-gdb-port'.

Change-Id: I5a1b7adb749746516f5d4ffc6193c47b70132364
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6034
Tested-by: jenkins
2021-04-11 21:34:30 +01:00
Liming Sun 651b861d5d target/aarch64: Add watchpoint support
There are some breakpoint/watchpoint related code in armv8_dpm.c,
but seems not working for aarch64. Target aarch64 has its own
breakpoint implementation in aarch64.c. This commit follows the
same logic to add watchpoint support for target aarch64.

This commit also increases the size of stop_reason[] in function
gdb_signal_reply() since the old size is too small to fit in a
64-bit address, such as ffff8000115e6980.

Change-Id: I907dc0e648130e36b434220f570c37d0e8eb5ce1
Signed-off-by: Liming Sun <lsun@mellanox.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-on: http://openocd.zylin.com/4761
Tested-by: jenkins
Reviewed-by: Liming Sun <limings@nvidia.com>
Reviewed-by: Kevin Burke <kevinb@os.amperecomputing.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-04-11 21:28:01 +01:00
Ernie Edgar 28724d996a
Update version check error message from 0.14 to 1.0. (#588) 2021-04-02 11:51:01 -07:00
Evgeniy Didin eca4f964b4 target/arc: refactor ARC register numbers defines
For Zephyr rtos support it is necessary to define general register
numbers for architecture. There were some already in arc.h file.
Let's define ARC registers numbers as a set instead of separate defines.

Change-Id: I63742b8608f9556c2ec9bd2661a0fd9cf88e9b74
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/6105
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-19 22:01:00 +00:00
Rene Kita 6db49eb885 build: remove warnings with gcc 11
This removes some warnings which prevent a successful build with -Werror
which is enabled by default. I'm using gcc 11, so maybe others are not
getting this warnings yet.

In src/flash/nor/numicro.c the debug messages were misleadingly indented.
In src/target/arm920t.c the array size where smaller than expected from
the receiving function.

Change-Id: I66f5c6a63beb9f9416e73b726299297476c884d8
Signed-off-by: Rene Kita <git@rkta.de>
Reviewed-on: http://openocd.zylin.com/6104
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-19 22:00:34 +00:00
Tarek BOCHKATI 84af95bb54 aarch64: handle semihosting in aarch32 state
Change-Id: I0e868d617db126a2b258e27b11979b75b5bb72f5
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5860
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-19 21:59:48 +00:00
Tim Newsome 41147e6fcd Implement CRC32 algorithm for RISC-V.
Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: Id437f78e74e3d837ff203f84c4eeb996bfad9a01
Reviewed-on: http://openocd.zylin.com/6076
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2021-03-19 21:58:17 +00:00
Christian Hoff 6c0151623c aarch64: add support for "reset halt"
Support halting the CPU directly after a reset. If halt is
requested, the CPU stops directly at the reset vector, before
any code is executed.

This functionality was implemented using the Reset Catch
debug event.

Change-Id: If90d54c088442340376f0b588ba10267ea8e7327
Signed-off-by: Christian Hoff <christian.hoff@advantest.com>
Reviewed-on: http://openocd.zylin.com/5947
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-03-19 21:57:43 +00:00
Antonio Borneo 25218e8935 jtag: remove minidriver code and minidriver-dummy
With zy1000 removed, there is no other implementation that uses
the minidriver, apart from the test/example minidriver-dummy.
While the idea of the minidriver is probably still valid (that is
to intercept jtag primitives before serialization), there is no
current use case, no guarantee it is really working, and the way
it was implemented (by macros and #if conditionals) is really hard
to maintain and test.

Let's let it rip in git history, from where it could eventually be
taken back in a more modern implementation.
The entry points of minidriver API are still in the code with the
original names.

Change-Id: I882e32cb26cf5842f9cba14e3badaf8948e3760d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6091
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-03-19 21:56:06 +00:00
Antonio Borneo 26a57b06cf oocd_trace: drop the code, deprecated in v0.10.0
The code for oocd_trace has been marked as deprecated in release
v0.10.0, 4 years ago.

Time to drop it!

Change-Id: I989f8345dee4ff2369bcf5e2e2ace86bbd5aa6a5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6088
Tested-by: jenkins
2021-03-19 21:55:15 +00:00
Antonio Borneo 113f949ac1 target: remove handling of target's deprecated_name
We do not have anymore any deprecated target name.
Drop the code to handle deprecated target names and the placehold
in struct target_type.

This patch is separated from the patch that drops the remaining
deprecated target names to be ready to revert this if there is any
need in the future.

Change-Id: I96fca7ffa39d8292f81e79f115ea45c4a30035d7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6087
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-03-19 21:55:02 +00:00
Antonio Borneo 64b486e74f target: remove target names already deprecated in v0.8.0
Some target name were marked as deprecated in release v0.7.0 and
v0.8.0, almost 7 years ago, and replaced with more 'actual' names.
We can reasonably expect that in these 7 years any user of OpenOCD
has already migrated to v0.8.0 or to some newer release, thus has
already updated any local/personal script to get rid of the
deprecated message.

Drop the target names already deprecated in v0.8.0.

Change-Id: I7c7491496db1b302b4eb1e9fc6090b58d4acf05a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6086
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-03-19 21:54:57 +00:00
Antonio Borneo 70ead8ff5d startup.tcl: remove commands already deprecated in v0.7.0
Some command were already marked as deprecated in release v0.7.0,
more then 7 years ago, and for some of them the depredation date
is even earlier.
We can reasonably expect that in these 7 years any user of OpenOCD
has already migrated to v0.7.0 or to some following intermediate
build, thus has already updated any local/personal script to get
rid of the deprecated message.

Drop the commands already deprecated in v0.7.0.

Change-Id: I81cdc415ab855ebf30980ef5199f9780c5d7f932
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6085
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-03-19 21:54:51 +00:00
Antonio Borneo cda7bc9a4c target/arm920t: remove command 'arm920t cp15i' deprecated in v0.4.0
The command 'arm920t cp15i' was marked as deprecated in release
v0.4.0, almost 11 years ago.
We can reasonably expect that in these years any user of OpenOCD
has already migrated to v0.4.0 or to some newer release, thus has
already updated any local/personal script.
There is no run-time warning about the deprecation, but it is
reported in the help and in the documentation.

Drop the command already deprecated in v0.4.0.

Change-Id: I755c4283e13e125558fcd73b15fe20498eae95ca
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6083
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-03-19 21:54:41 +00:00
Antonio Borneo ab0def0f38 target/arm720t: remove command 'arm720t cp15' deprecated in v0.4.0
The command 'arm720t cp15' was marked as deprecated in release
v0.4.0, almost 11 years ago.
We can reasonably expect that in these years any user of OpenOCD
has already migrated to v0.4.0 or to some newer release, thus has
already updated any local/personal script.
There is no run-time warning about the deprecation, but it is
reported in the help and in the documentation.

Drop the command already deprecated in v0.4.0.

Change-Id: I2b325d0312d96ca5e5f0f1bad13bb162b3b75c52
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6082
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-03-19 21:54:32 +00:00
Tarek BOCHKATI bc0c9907d6 cortex_m: avoid reading and writing non-existent registers
Change-Id: Iedc24352c8d3444372da06d00fcec9603540f950
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6059
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-10 21:35:31 +00:00
Antonio Borneo cb8e3fb2d9 server: revert commit 7e6556b3ca
With the removal of old tpiu code, commit 7e6556b3ca ("server:
permit the add_service function to return the created service")
http://openocd.zylin.com/5717/ can be reverted.

Fix also the new calls to add_service().

Change-Id: Ib7f2dfc6a9e829239e20313e0f121911085fdc00
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6031
Tested-by: jenkins
Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
2021-03-10 21:34:13 +00:00
Antonio Borneo dc7b32ea4a armv7m_trace: get rid of the old tpiu code
Remove all the old tpiu code and replace it with a wrapper that
uses the new commands, prints-out the new commands and informs
about the deprecation.

All the code that handles the deprecated tpiu commands is enclosed
between the comments
	/* START_DEPRECATED_TPIU */
and
	/* END_DEPRECATED_TPIU */
so will be easy to remove it in the future.

Change-Id: I70b0486770128203b923346382d9a90b8ec08439
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6030
Tested-by: jenkins
Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
2021-03-10 21:34:04 +00:00
Antonio Borneo 184724d14e arm_tpiu_swo: add support for independent TPIU and SWO
This is supposed to replace big part of armv7m_trace.[ch], since
TPIU is not only the one implemented in Cortex-M3 and M4.

Change-Id: I7588d16cbefe9cdb371c52fb0aa5cdfb48518804
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5858
Tested-by: jenkins
2021-03-10 21:33:40 +00:00
Antonio Borneo f9509c92db itm: rework itm commands before 'init'
If the command 'itm port[s]' is issued before 'init', the ITM can
not be programmed because OpenOCD cannot access the target yet.
The configuration is recorded and applied after target examine.
The current test to trigger the ITM delayed-programming is based
on the TPIU configuration. This is allowed because the only use of
ITM it so send data through TPIU.
In case of system TPIU, not belonging anymore to the target, there
is no more association between target ITM and system TPIU.

Add a flag to record the pending ITM configuration requested
before 'init' and test the flag to trigger the delayed-programming
of the ITM.

Change-Id: I101eb97a116d7925cd2ff068f3e8813fc008b08e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6029
Tested-by: jenkins
2021-03-10 21:33:09 +00:00
Antonio Borneo faaa42283f stlink: fix execution order in stlink_config_trace()
The change [1] guarantees that the value pointed by 'prescaler'
gets always set, even when the adapter does not support the
specific mode requested (e.g. sync), or during trace disabling.
This works fine with the code in armv7m_trace_tpiu_config(), but
requires all the parameters to be valid also to disable the trace
(with 'enable==false'), otherwise returns error on incorrect
parameters or even causes segmentation fault if pointers
'trace_freq' or 'prescaler' are NULL.

Another problem in stlink_config_trace(), not linked with [1], is
caused by a tentative to change the settings on an already enabled
trace; the trace is disabled before the new parameters are fully
validated and in case of invalid parameters the trace is not
re-enabled.
It would be more logical to first check all the parameters, then
disable the trace, change the settings and re-enable the trace.

Practically revert [1] by checking 'enable==false' at function
entry, then disable trace and exit without any further check on
the other parameters.
For the case 'enable==true', validate all the function parameters
then disable the trace, update the trace settings and re-enable
the trace.
Modify the caller armv7m_trace_tpiu_config() to initialize the
variable 'prescaler' to a safe value to avoid the issue targeted
by [1].

[1] commit 38277fa752 ("jtag/drivers/stlink_usb: fix SWO prescaler")

Change-Id: Ia6530682162ca2c9f5ac64301f2456f70cc07ed2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5934
Tested-by: jenkins
Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
2021-03-10 21:32:43 +00:00
Adrian Negreanu 169e5bf186 armv7m_trace_itm_config: wait for ITMBusy to be cleared
pg315 of CoreSight Components:

It is recommended that the ITMEn bit is cleared and waits for the
ITMBusy bit to be cleared, before changing any fields in the
Control Register, otherwise the behavior can be unpredictable.

Change-Id: Ie9a2b842825c98ee5edc9a35776320c668047769
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Reviewed-on: http://openocd.zylin.com/6043
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-10 21:31:27 +00:00
Yasushi SHOJI 547fa6eeb7 target: Remove redundant initialization of endianness
target->endianness is initialized to TARGET_ENDIAN_UNKNOWN at 34 lines
below, before calling target_configure.  This initialization is
redundant and not needed.

Change-Id: Iea2d5e17a13c1a8b0b209ba7c20043736b520ef6
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: http://openocd.zylin.com/6039
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-10 21:30:27 +00:00
Marc Schink 02abae8cdf target/mips: Remove typedef'd struct
The C style guide forbids typedef'd structs, see 'Naming Rules'.

Change-Id: I449590251056c478c05105cdc18014ab4eb77ed8
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6033
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-10 21:30:04 +00:00
Tim Newsome 50a5971be2
RISC-V Freertos support (#582)
Support reading names/status of all threads, as well as all registers that are stored on the stack.

Limited to RV32, no FPU.

---

* WIP

Change-Id: I09417c2e45748504be449d74c39ae0b6b311e277

* WIP

Change-Id: I975fa2cabbf43ccf64f5162337c394f9c8e3017f

* Import rbtreehash-list from gnulib.

The main change to get this to build was to remove 3 includes from
config.h (actual code change in configure.ac) because lib/Makefile.am
doesn't contain the correct flags to find the files referenced there.
Instead I sprinkled necessary includes throughout the source code.

This feels like less of a hack regardless, so hopefully that's OK.

I'm not actually using the new library. Just got it to build.

Change-Id: I824000d8be0b6f58b6f2036498b37c33f453515a

* Actually use linkedhash_map.

Moved some files around to get it to link. Also note I'm using a
different module than before. This is the one I want (I think right
now).

Change-Id: I6161bffd4b5f916602c33c1930be6e061cefe982

* Properly track TCB/threadid mappings.

Change-Id: I725abb96f880745d78c5634d5faff7385c2773e1

* OpenOCD no longer crashes reading rv32 freertos regs

Change-Id: Ia84502dbf007145995d4fba8661153ab7f58f26f

* WIP

The register values reported for threads that aren't the current thread
look believable to me.

Change-Id: I94b109565c8cc2029fa77657a7fc10291bcb36e3

* Correctly mark the current thread.

Change-Id: Id94ababb55a222292090e6465e47ebf92ca26291

* Try to make the build pass.

Change-Id: I0fddd10fe22c013464f9a1e106cd21470fa7afe1
Signed-off-by: Tim Newsome <tim@sifive.com>

* Exclude new gnulib files.

Change-Id: I8b95615908034124f2236422771b5079f3304e37
Signed-off-by: Tim Newsome <tim@sifive.com>

* Style fixes.

Change-Id: I4aef0b1d0b0e366893c740ab89756fe8ea033ddb
Signed-off-by: Tim Newsome <tim@sifive.com>

* Don't include string.h.

It breaks the i686-w64-mingw32-gcc build, which complains:
error: incompatible implicit declaration of built-in function ‘strndup’

Change-Id: I8d758fe092efa503e015f71f34721f2c44632516
Signed-off-by: Tim Newsome <tim@sifive.com>

* Hopefully fix mingw32 build.

Change-Id: I8703b834b5679588b3aa6602ae4add7258dbd879
Signed-off-by: Tim Newsome <tim@sifive.com>

* Include winsock2 in replacements.

Change-Id: I77cfc90736c771a3cdefb39062e6c5b59de52cd5
Signed-off-by: Tim Newsome <tim@sifive.com>

* Zero now gets the correct value.

Change-Id: Ia7da043439a82081629b8a5991ed8cbc382d5ac8
Signed-off-by: Tim Newsome <tim@sifive.com>

* Accommodate non-general regs on the stack.

Also refactor FreeRTOS a little to separate out target-specific code
from target-indepent code.

Change-Id: Icc74d85b24f35d069be091e32e23144573560e9f

* All registers now read sane values.

It appears that FreeRTOS wastes a space on the stack, where x0 would be
saved. Am I missing something?

Correctly read mstatus as it is saved on the stack as well. This same
mechanism should also work for FPU registers, although there's more work
to be done before we get there.

Change-Id: Iabacc3af2ab368aa7b9090c1ff719451a087b5ed
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-03-05 15:52:33 -08:00
Antonio Borneo 23d8831391 target: avoid polling during 'resumed' event handler
OpenOCD is based on a single main loop that schedules all the
activities.
At the execution of a TCL command, the timestamp is checked to
eventually trigger the polling of the targets. This means that by
executing a TCL command the polling can be triggered and detect a
change of target's state.

When openocd 'resumes' a target, the target can halt again by
hitting a breakpoint.
The 'resumed' event handler is started just after the target has
been resumed, but it triggers a polling before the execution of
its very first instruction.
If the polling finds the target halted, it will run the 'halted'
event handler, that will then be executed 'before' the pending
'resumed' handler.

In case of gdb, a 'continue' command will restart the target but,
polling (and halt detection) executed before the end of the resume
process will hide the halt. As a consequence, the gdb will not be
informed of the halt and will remains waiting as if the target is
still running without showing the prompt.

This can be verified by running on the target a firmware with a
loop, run openocd with a dummy 'resumed' event, and let gdb to set
a breakpoint in the loop. A 'continue' command will cause the
target to halt again by hitting the breakpoint at the next loop
iteration, but gdb will loose it and will not return the prompt.

	openocd -f board/st_nucleo_f4.cfg -c \
		'stm32f4x.cpu configure -event resumed {echo hello}'
	arm-none-eabi-gdb -ex 'target remote :3333' -ex 'b *$pc' -ex c

Disable the polling while executing target's resume().
Document it and provide hints to developers to cope with future
implementation.

Change-Id: I3be830a8e7c2ef6278617cb4547a4d676b0ddeb5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Габитов Александр Фаритович <gabitov@planarchel.ru>
Reviewed-on: http://openocd.zylin.com/6074
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2021-03-04 14:58:58 +00:00
Peter Mamonov 54ef790149 target: use proper macro for parsing watchpoint address
Currently wp/rwp commands fail on 64-bit targets:

	> wp 0xffffffff80001400 4
	addr option value ('0xffffffff80001400') is not valid

Change-Id: I94d4af906b02b7bd463c8d79a6235a3646dfc434
Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Reviewed-on: http://openocd.zylin.com/6058
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-02-13 13:08:31 +00:00
Tim Newsome d57ab0b632
From upstream (#580)
* configure: do not make Capstone dependency automagic

This adds regular ./configure options to control dependency on the
Capstone disassembly engine. See [0] for the rationale.

[0] https://wiki.gentoo.org/wiki/Project:Quality_Assurance/Automagic_dependencies

Change-Id: I3e16dc5255d650aa1949ccf896b26dc96e522a75
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/5985
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* configure.ac: fix build with libusb0 and without libusb1

Driver 'openjtag' requires both libftdi and libusb1.
The current check is incorrect and the driver is built when
libftdi is present with libusb0 and without libusb1, which causes
the linker to fail resolving the required libusb1 symbols.

Remove the check for libusb0 on driver 'openjtag'.
Create a new adapters group LIBFTDI_USB1_ADAPTERS to hold the
driver 'openjtag'.

Change-Id: I1f5e554b519e51c829d116ede894639cb55a26aa
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5989
Tested-by: jenkins

* doc: fix over/underfull hboxes in PDF

This adds some cosmetic changes to make the PDF User Manual look
proper.

Building it now requires Texinfo 5.0 which shouldn't be problematic
according to [0]. Commit 79fdeb37f4 is
effectively reverted.

[0] https://repology.org/project/texinfo/versions

Change-Id: I990bc23bdb53d24c302b26d74fd770ea738e4096
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/5995
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* contrib: rpc_examples: haskell: fix ftbs with current libraries

And get rid of some warnings along the way.

Change-Id: I8fdbe1fa304276be6b0f25249b902b3576aa3793
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/5987
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Makefile.am: fix override of target 'check-recursive'

To prevent executing the Jim Tcl tests, the makefile's target
'check-recursive' has been overridden in commit 56d163ce79
("jimtcl: update to 0.77, the current version, enable only
specific modules").
This causes a runtime warning during build:
	Makefile:6332: warning: overriding recipe for target 'check-recursive'
	Makefile:5098: warning: ignoring old recipe for target 'check-recursive'

Instead of override the makefile's target 'check-recursive',
prevent the recursion by re-assigning as empty the variable
SUBDIRS for this specific target only.

Change-Id: I03d1c467eba42316a59aeed4612d6bdbe6211282
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 56d163ce79 ("jimtcl: update to 0.77, the current version, enable only specific modules")
Reviewed-on: http://openocd.zylin.com/5986
Tested-by: jenkins

* contrib: udev file for Cypress SuperSpeed Explorer kit

lsusb output:

Bus 003 Device 011: ID 04b4:0007 Cypress Semiconductor Corp.
Couldn't open device, some information will be missing
Device Descriptor:
  bLength                18
  bDescriptorType         1
  bcdUSB               2.00
  bDeviceClass            0 (Defined at Interface level)
  bDeviceSubClass         0
  bDeviceProtocol         0
  bMaxPacketSize0         8
  idVendor           0x04b4 Cypress Semiconductor Corp.
  idProduct          0x0007
  bcdDevice            0.00
  iManufacturer           1
  iProduct                2
  iSerial                 0
  bNumConfigurations      1
  Configuration Descriptor:
    bLength                 9
    bDescriptorType         2
    wTotalLength          114
    bNumInterfaces          4
    bConfigurationValue     1
    iConfiguration          0
    bmAttributes         0xa0
      (Bus Powered)
      Remote Wakeup
    MaxPower              100mA
    Interface Association:
      bLength                 8
      bDescriptorType        11
      bFirstInterface         0
      bInterfaceCount         2
      bFunctionClass          2 Communications
      bFunctionSubClass       2 Abstract (modem)
      bFunctionProtocol       1 AT-commands (v.25ter)
      iFunction               0
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        0
      bAlternateSetting       0
      bNumEndpoints           1
      bInterfaceClass         2 Communications
      bInterfaceSubClass      2 Abstract (modem)
      bInterfaceProtocol      1 AT-commands (v.25ter)
      iInterface              0
      CDC Header:
        bcdCDC               1.10
      CDC ACM:
        bmCapabilities       0x02
          line coding and serial state
      CDC Union:
        bMasterInterface        0
        bSlaveInterface         1
      CDC Call Management:
        bmCapabilities       0x00
        bDataInterface          1
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x83  EP 3 IN
        bmAttributes            3
          Transfer Type            Interrupt
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0040  1x 64 bytes
        bInterval              10
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        1
      bAlternateSetting       0
      bNumEndpoints           2
      bInterfaceClass        10 CDC Data
      bInterfaceSubClass      0 Unused
      bInterfaceProtocol      0
      iInterface              0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x01  EP 1 OUT
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0040  1x 64 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x82  EP 2 IN
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0040  1x 64 bytes
        bInterval               0
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        2
      bAlternateSetting       0
      bNumEndpoints           3
      bInterfaceClass       255 Vendor Specific Class
      bInterfaceSubClass      4
      bInterfaceProtocol      0
      iInterface              0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x04  EP 4 OUT
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0040  1x 64 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x85  EP 5 IN
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0040  1x 64 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x86  EP 6 IN
        bmAttributes            3
          Transfer Type            Interrupt
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0040  1x 64 bytes
        bInterval              10
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        3
      bAlternateSetting       0
      bNumEndpoints           0
      bInterfaceClass       255 Vendor Specific Class
      bInterfaceSubClass      5
      bInterfaceProtocol      0
      iInterface              0

Change-Id: I62f0300199da3551c8774a4a5a4cd106a3ab2904
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-on: http://openocd.zylin.com/3611
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target: fix memory leak on multiple '-gdb-port' flag

In the odd case of multiple flags '-gdb-port' during 'target
create' or following 'configure', the new strdup()'ed value will
replace the old one without freeing it.

Free the old value (if it exists) before replacing it.

Change-Id: I1673346613ce7023880046e3a9ba473e75f18b8a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6005
Tested-by: jenkins

* udev: fix permission for Ambiq Micro EVK's

Commit 68e204f1e9 ("udev: Add rules for Ambiq Micro EVK's.") was
initially proposed as http://openocd.zylin.com/3429/ then replaced
by http://openocd.zylin.com/3980/
The initial proposal was for file '99-openocd.rules', in which
MODE="664" was the norm.
After merge of http://openocd.zylin.com/2804/ the new udev rules
in '60-openocd.rules' switched to MODE="660", but the evolution of
the above patch missed this change.

Switch udev rules of Ambiq Micro EVK's to MODE="660" and uniform
them to the rest of the file.

Change-Id: I4b4eea535184ee8569da3264bff4f1fafb5bce4d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 68e204f1e9 ("udev: Add rules for Ambiq Micro EVK's.")
Reviewed-on: http://openocd.zylin.com/6004
Tested-by: jenkins

* doc/style: fix doxygen error

Doxygen complains about non-closed nested comments:
	doc/manual/style.txt:423: warning: Reached end of file
	while still inside a (nested) comment. Nesting level 1
	(probable line reference: 149)

This is caused by the string '/**' that is interpreted as the
beginning of a comment.

Escape the string to not let doxygen consider it as a comment

While there, replace @code/@endcode with @verbatim/@endverbatim to
properly render the line.

Change-Id: If2a27c4cf659326e317cc4ac8c0b313e97e40432
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5996
Tested-by: jenkins

* flash/nor/max32xxx: fix path of include file

The relative path should have three times '..'.

Issue identified by doxygen:
	src/flash/nor/max32xxx.c:85: warning: include file
	../../contrib/loaders/flash/max32xxx/max32xxx.inc not
	found, perhaps you forgot to add its directory to
	INCLUDE_PATH?

Change-Id: Ie7b4948c6770b8acb9eff26e08eea32945ebb219
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5997
Tested-by: jenkins

* Doxyfile.in: fix build out-of-tree

When doxygen is built out-of-tree, it fails to find the generated
file startup_tcl.inc:
	src/openocd.c:59: warning: include file startup_tcl.inc
	not found, perhaps you forgot to add its directory to
	INCLUDE_PATH?

Add '@builddir@/src' to INCLUDE_PATH.

Change-Id: I51f2f6fe7224bba0f8b3db7219f9831de4e67139
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5998
Tested-by: jenkins

* doc/manual/primer/jtag.txt: remove duplicated section name

The section name 'primerjtag' is used twice, causing doxygen to
complain:
	warning: multiple use of section label 'primerjtag',
	(first occurrence: doc/manual/primer/jtag.txt, line 107)

Rename one of them.

Change-Id: Id307915dbc51a7f647fab4fb28ab431e65344d61
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5999
Tested-by: jenkins

* Doxyfile.in: exclude libjaylink from doxygen

When build using libjaylink as git submodule, doxygen includes the
libjaylink files and complains for multiple 'mainpage' comment
block, one in OpenOCD and the other in libjaylink:
	src/jtag/drivers/libjaylink/libjaylink/core.c:37: warning:
	found more than one \mainpage comment block! (first
	occurrence: doc/manual/main.txt, line 1), Skipping current
	block!

Exclude libjaylink submodule from doxygen.

Change-Id: I5e856817344c9f21f8c26f077a23c00b83cfbcb5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6000
Tested-by: jenkins

* openocd: fix incorrect doxygen comments

Use '@param' in front of function's parameters and '@a' when the
parameter is recalled in the description.

This fixes doxygen complains:
	warning: Found unknown command '@buff16'

While there, fix a minor typo s/occured/occurred/ in a comment and
the typo s/@apram/@param/ in a doxygen comment.

Change-Id: I5cd86a80adef552331310a21c55ec5d11354be21
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6001
Tested-by: jenkins

* openocd: fix doxygen parameters of functions

Add to doxygen comment the missing parameters.
Remove from doxygen comment any non-existing parameter.
Fix the parameter names in doxygen comment to match the one in the
function prototype.
Where the parameter name in the doxygen description seems better
than the one in the code, change the code.
Escape the character '<' to prevent doxygen to interpret it as an
xml tag.

Change-Id: I22da723339ac7d7a7a64ac4c1cc4336e2416c2cc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6002
Tested-by: jenkins

* doc/manual/primer/autotools.txt: fix doxygen warning

Commit ab90b87778 ("configure: remove AM_MAINTAINER_MODE,
effectively always enabling all the rules") removes the configure
flag '--enable-maintainer-mode' and its documentation, but have
left a reference to the removed subsection 'primermaintainermode'
and this triggers a warning in doxygen:
	doc/manual/primer/autotools.txt:21: warning: unable to
	resolve reference to 'primermaintainermode' for \ref
	command

Remove the obsoleted paragraph.

Change-Id: I56e69ef033d546d159745bed1b47c6105827e7ae
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: ab90b87778 ("configure: remove AM_MAINTAINER_MODE, effectively always enabling all the rules")
Reviewed-on: http://openocd.zylin.com/6003
Tested-by: jenkins

* flash/stmqspi: fix build error with -Werror=maybe-uninitialized

using gcc 9.3 on ubuntu focal fossa with -Werror=maybe-uninitialized
we get this error:
  /src/flash/nor/stmqspi.c: In function ‘read_flash_id’:
  /src/flash/nor/stmqspi.c:1948:6: error: ‘retval’ may be used uninitialized

Change-Id: Ifd8ae60df847fc61e22ca100c008e3914c9af79b
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: http://openocd.zylin.com/6012
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/riscv: fix build error with -Werror=maybe-uninitialized

using gcc 9.3 on ubuntu focal fossa with -Werror=maybe-uninitialized
we get this error:
  /src/target/riscv/riscv.c: In function ‘riscv_address_translate’:
  /src/target/riscv/riscv.c:1536:13: error: ‘pte’ may be used uninitialized

Change-Id: I51e180b43f9b6996e4e4058db49c179b9f81bcdc
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: http://openocd.zylin.com/6013
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* cortex_m: [FIX] ARMv8-M does not support VECTRESET

ref: Arm®v8-M Architecture Reference Manual (DDI0553B.m)
     D1.2.3: AIRCR, Application Interrupt and Reset Control Register
             Bit [0] is RES0

Change-Id: I6ef451b2c114487e2732852a60e86c292ffa6a50
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: http://openocd.zylin.com/6014
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* driver/ftdi: skip trst in swd mode

When using the adapter olimex arm-jtag-swd (to convert to SWD a
JTAG-only FTDI adapter), the pin trst on JTAG side is re-used to
control the direction of pin SWDIO on SWD side.
There is a single reset API at adapter driver to assert/deassert
either srst and/or trst. A request to assert/deassert srst can
cause also trst to change value, hanging the SWD communication.

In SWD mode, ignore the value passed to trst.

Change-Id: I5fe1eed851177d405d77ae6079da9642dc1a08f1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6006
Tested-by: jenkins

* configure.ac: drop macro 'AC_PROG_CC_C99' from autoconf 2.70

The macro AC_PROG_CC_C99 has been obsoleted by autoconf 2.70 and
triggers a set of warnings from both 'aclocal' and 'autoconf'.
The test of AC_PROG_CC_C99 is now included in AC_PROG_CC.

For autoconf 2.69 and earlier the macro is still required, so
cannot be simply dropped.

Use a conditional test to avoid the warning on autoconf 2.70 but
still use AC_PROG_CC_C99 on older autoconf.

Change-Id: I5e8437f5a826fb63be6d07bcb5bb824f94683020
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6009
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>

* configure: drop macro 'AC_HEADER_TIME'

The macro AC_HEADER_TIME has been obsoleted by autoconf 2.70.

Not all systems provide 'sys/time.h', plus some old system didn't
allowed to include both 'time.h' and 'sys/time.h' because 'time.h'
was included by 'sys/time.h' and was not properly protected to
allow multiple inclusion.
The macro AC_HEADER_TIME helps to detect such odd case.
Nowadays all the systems properly protect 'time.h', so its safe to
unconditionally include 'time.h', even if it is also included by
'sys/time.h'.

The case of systems without 'sys/time.h' is already covered by
configure.ac through the directive
	AC_CHECK_HEADERS([sys/time.h])

Remove the obsoleted autoconf macro and simplify the code by
including 'time.h' unconditionally and check HAVE_SYS_TIME_H to
include 'sys/time.h'.

Change-Id: Iddb3f3f1d90c22668b97f8e756e1b4f733367a7d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6010
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>

* README.macOS: explain how to install suitable Texinfo

Change-Id: Ic5906111f412eebd906a9be3fd0e133484def3eb
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/6026
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* jlink: fix device discovery when network is off

If user specifies a serial number for the jlink device, openocd
extends the search to network jlink devices too, without checking
if the host has a valid and functional network connection. If the
network is not functional, libjaylink returns error. This error
invalidates the discovery on USB, even if it was successful.

Factor-out parts of the jlink_init into separate jlink_open_device
function, use that function to firstly discover and match USB
devices and, if matching device was not found on the USB bus and
serial number was specified, repeat discovery and matching via TCP.

Fixes: https://sourceforge.net/p/openocd/tickets/294/

Change-Id: Iea0de1640d4e5b21ecc7e9c1dd6d36f214d647c2
Signed-off-by: Bohdan Tymkiv <bohdan200@gmail.com>
Reviewed-on: http://openocd.zylin.com/6025
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>

* README: add missing items for 0.11

JTAG adapters
  Cadence DPI, Cypress Kitpro, FTDI FT232R, Linux GPIOD, Mellanox rshim,
  Nuvoton Nu-Link, Nu-Link2, NXP IMX GPIO, Remote Bitbang, TI XDS110,
  Xilinx XVC/PCIe

Debug targets
  AArch64, Cortex-M (ARMv8-M), ARCv2, MIPS64, RISC-V, ST-STM8

Flash Drivers
  ATmega128RFA1, Atmel SAM, eSi-RISC, EZR32HG, MAX32, MXC, nRF52, PSoC6,
  Renesas RPC HF and SH QSPI, SiFive Freedom E, ST BlueNRG,
  STM32 QUAD/OCTO-SPI for Flash/FRAM/EEPROM, SWM050, TI CC13xx, TI CC26xx,
  TI CC32xx, TI MSP432, Winner Micro w600, Xilinx XCF

Change-Id: I341618ac5d7189e4f98268cecd66c99447b72af8
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: http://openocd.zylin.com/6027
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

* The openocd-0.11.0-rc2 release candidate

Signed-off-by: Paul Fertser <fercerpav@gmail.com>

* Restore +dev suffix

Signed-off-by: Paul Fertser <fercerpav@gmail.com>

* steppenprobe: fix file permission

Commit 895d4a5995 ("tcl/interface/ftdi: Add Steppenprobe open
hardware interface") erroneously set the execution permission to
the configuration file.

Strip the execution permission.

Change-Id: I556451d5e6fee4aee385451e8c90216a25b6ef46
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: http://openocd.zylin.com/5653
Reviewed-on: http://openocd.zylin.com/6038
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: Paul Fertser <fercerpav@gmail.com>

* github: fix github wokflow while pushing a tag

this fix permits to add correctly the generated artifact (windows binaries)
into the release section.

Change-Id: Ia982370d3a1e08c623ebcabb5ac97e9fb49d00e0
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6047
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* doc: Fix type in Hooking up the JTAG Adapter

We are talking about adapter connectivity in this chapter. It should
be "dongles" instead of "cables".

Change-Id: I7bd4307765517375caa2af86dfc929d0ef66c3e6
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: http://openocd.zylin.com/6040
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins

* doc/manual: Fix @subpage handling

The subpage "thelist" used to have a title "Pending and Open Tasks"
but the commit c41db358a0 changed it to "The List". With
@subpage, it now renders:

    "The List of The List enumerates opportunities for"

instead of

    "The List of Pending and Open Tasks enumerates opportunities for"

This commit fix it to

    "The List enumerates opportunities for"

Change-Id: Ifee0dcd9b3c9f7e651a8748a7afda99eedea3c5c
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: http://openocd.zylin.com/6041
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* doc/manual: Fix function name typo

We have both the singular form, register_command(), and the plural form
register_commands().

Change-Id: I905ea83988b8ac70dd809b02d53b646aa4d66697
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: http://openocd.zylin.com/6042
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins

Co-authored-by: Paul Fertser <fercerpav@gmail.com>
Co-authored-by: Antonio Borneo <borneo.antonio@gmail.com>
Co-authored-by: Jiri Kastner <cz172638@gmail.com>
Co-authored-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Co-authored-by: Bohdan Tymkiv <bohdan200@gmail.com>
Co-authored-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Co-authored-by: Yasushi SHOJI <yashi@spacecubics.com>
2021-02-11 11:27:18 -08:00
Jan Matyas 9e174604b9
Fix in write_memory_bus_v1: Read sbcs properly (#578)
* Fix in write_memory_bus_v1: Read sbcs properly

Fixed an issue with system bus write: sberrors were not properly
detected because of an incomplete read of "sbcs". The read was initiated
but not completed (value not acquired by a second DMI scan).

Added debug prints in case sberror != 0.
Added few comments to explain the algorithm.

Change-Id: Id5eb07f2f1bf8e9afee2dec04b9ff5c5a57f606b
Signed-off-by: Jan Matyas <matyas@codasip.com>

* Updated per review discussion at #577.

Change-Id: I65c07edcd4e86eaa5327280a81f74db0b9c84f9c
Signed-off-by: Jan Matyas <jmatyas@codasip.com>

* Empty commit to re-trigger Travis build.

Change-Id: I95deeb28584a891203c8904be621e48003f069dc

Co-authored-by: Jan Matyas <jmatyas@codasip.com>
2021-02-04 10:04:01 -08:00
Tim Newsome 3651cbdfdc
Add memory access while running to `riscv info` (#576)
This way people can write TCL scripts that rely on these more abstract
properties instead of having to check for the existence of sbaccess,
which is not part of 0.11. (There is a similar feature but things are
named differently.)

Change-Id: I5c95a29ef43cb40c3a73b904f11fa7ca38d87b21
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-01-29 12:51:22 -08:00
Tim Newsome 8980c2038a
Select current hart before accessing vector regs. (#574)
I don't know how this worked before. Possibly caused by overzealous
removal of `-rtos riscv`.

Change-Id: I7259267b861ef45655f469ab39cc463d608fe149
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-01-29 10:58:34 -08:00
Tim Newsome 6628394c2c
Minor cleanups. (#573)
* Make a few globals const.

Looking through globals to see what needs to be removed, but const
globals are OK.

Change-Id: I4126a3f629daf91b109a3bd7120e4b4f62a9d8ee
Signed-off-by: Tim Newsome <tim@sifive.com>

* Fix comment typo.

Change-Id: I0c20837559411410b6870e0d0e52c0179a3a167e
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-01-29 10:58:11 -08:00
Tim Newsome a83ac81022
Add authdata_read/authdata_write support to 0.11. (#575)
AFAIK there is no hardware that implements this, but it should be a
close-to-done starting point in case it is ever required.

Change-Id: I49e3082e8629b1d70b12e8a847c2848e75b04508
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-01-28 09:56:51 -08:00
Jan Matyas 4d0efe0fbb
riscv-013: Fix comment for register_read() (#569)
Signed-off-by: Jan Matyas <matyas@codasip.com>
2021-01-20 13:01:16 -08:00
Tim Newsome d52e4668a6
Remove `-rtos riscv` (#567)
* Remove `-rtos riscv`.

`-rtos hwwthread` is target-independent and a cleaner way to achieve the
same thing.

Change-Id: I863a91f9ad66e37dc36f2fbcbffe403b91355556

* Little more cleanup.

Change-Id: I8fda2317368a94760bc734abc7f1de6ee5b82a7c

* Clean up some more.

Change-Id: I64a1e96aa3bd8c0561d4d19930f99e9bc40eab86

* Get rid of riscv_[sg]et_register_on_hart

Change-Id: I5ea9439bad0e74d7ed2099935e7fc7292c4a2b7f

* Remove hartid arg from set_register.

Change-Id: Ib560e3c63ff32191589c74d3ee06b12295107c6f

* Remove more references to hartid.

Change-Id: Ie9d932fb8b671c478271c1084dad43cad3b2bfbc

* Remove some unused code.

Change-Id: I233360c6c420d1fc98b923d067e65a9419d88d7b
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-01-18 12:22:43 -08:00
Tarek BOCHKATI 2dc9c1df81 cortex_m: [FIX] ARMv8-M does not support VECTRESET
ref: Arm®v8-M Architecture Reference Manual (DDI0553B.m)
     D1.2.3: AIRCR, Application Interrupt and Reset Control Register
             Bit [0] is RES0

Change-Id: I6ef451b2c114487e2732852a60e86c292ffa6a50
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: http://openocd.zylin.com/6014
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-01-18 15:32:03 +00:00
Tarek BOCHKATI 404993b29f target/riscv: fix build error with -Werror=maybe-uninitialized
using gcc 9.3 on ubuntu focal fossa with -Werror=maybe-uninitialized
we get this error:
  /src/target/riscv/riscv.c: In function ‘riscv_address_translate’:
  /src/target/riscv/riscv.c:1536:13: error: ‘pte’ may be used uninitialized

Change-Id: I51e180b43f9b6996e4e4058db49c179b9f81bcdc
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: http://openocd.zylin.com/6013
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-01-18 15:31:56 +00:00
Tim Newsome fcdecd88ae Don't write to zero.
It doesn't have any effect on real hardware, and by caching the value we
pretended it did.

Fixes #564

Change-Id: I9f4e2cc8abddee61435bbd8d992cbff971a0c28d
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-01-14 13:53:43 -08:00
Antonio Borneo 7e64e5a895 openocd: fix doxygen parameters of functions
Add to doxygen comment the missing parameters.
Remove from doxygen comment any non-existing parameter.
Fix the parameter names in doxygen comment to match the one in the
function prototype.
Where the parameter name in the doxygen description seems better
than the one in the code, change the code.
Escape the character '<' to prevent doxygen to interpret it as an
xml tag.

Change-Id: I22da723339ac7d7a7a64ac4c1cc4336e2416c2cc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6002
Tested-by: jenkins
2021-01-13 11:33:53 +00:00
Antonio Borneo 4cf5ab614b openocd: fix incorrect doxygen comments
Use '@param' in front of function's parameters and '@a' when the
parameter is recalled in the description.

This fixes doxygen complains:
	warning: Found unknown command '@buff16'

While there, fix a minor typo s/occured/occurred/ in a comment and
the typo s/@apram/@param/ in a doxygen comment.

Change-Id: I5cd86a80adef552331310a21c55ec5d11354be21
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6001
Tested-by: jenkins
2021-01-13 11:33:16 +00:00
Craig Blackmore 1158acec66 riscv: Fix comment in read_memory_progbuf
The comment should refer to reading rather than writing.

Change-Id: I72937bb48053233ab5e48d343c4bd1e394f77bda
Signed-off-by: Craig Blackmore <craig.blackmore@embecosm.com>
2021-01-13 11:32:38 +00:00
Antonio Borneo c1270bcb38 target: fix memory leak on multiple '-gdb-port' flag
In the odd case of multiple flags '-gdb-port' during 'target
create' or following 'configure', the new strdup()'ed value will
replace the old one without freeing it.

Free the old value (if it exists) before replacing it.

Change-Id: I1673346613ce7023880046e3a9ba473e75f18b8a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6005
Tested-by: jenkins
2021-01-13 11:32:34 +00:00
Tim Newsome 11b8110443 Merge branch 'master' into from_upstream
Conflicts:
	.github/workflows/snapshot.yml
	.gitmodules
	src/flash/nor/drivers.c
	src/helper/jep106.inc
	src/rtos/hwthread.c
	src/target/riscv/riscv.c
	src/target/target.c

Change-Id: I62f65e10d15dcda4c405d4042cce1d96f8e1680a
2020-12-31 13:40:49 -08:00
Antonio Borneo ed73398eb0 cortex-a: fix reset on dapdirect transports
The target code for assert reset on cortex_a has been patched on
commit b0698501b0 ("cortex_a: fix cortex_a_assert_reset() if
srst_gates_jtag") then in cdba6ba0ad ("cortex_a: fix reset for
SWD transport") to workaround the mismatch between jtag and swd
implementations. See discussion for the second patch at
http://openocd.zylin.com/3641/

While all of these mismatches should hopefully be cleaned by the
reset framework rework, an extension of the workaround of the
second patch is required for dapdirect transports, either
dapdirect_swd and dapdirect_jtag.

Extend the existing workaround to all non-jtag transports.

Change-Id: Ia6a9d43bab524cbb3de4c37ce24c45f25187353d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5979
Tested-by: jenkins
2020-12-26 15:47:48 +00:00
Antonio Borneo 722f579706 armv7m_trace: stop getting traces from adapter at exit
If OpenOCD is reading trace data from the target, at exit it
should stop the adapter to gather data, but should left the target
still producing them.

Add a helper in armv7m_trace to disable the adapter's trace and
call it during OpenOCD teardown.

This also provides a workaround for an issue in the firmware of
ST-Link V3 till version V3J7. If the SWD connection is closed when
trace is active, at following connection the trace does not work
anymore.

Change-Id: I47ccab61405384938555096c5aca789eaa090d27
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5978
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
Tested-by: jenkins
2020-12-26 15:47:44 +00:00
Tim Newsome b8620764c0
Add `riscv info` command. (#558)
Add `riscv info` command. Final output is "TCL format" and looks like this:
```
hart.xlen              64
hart.trigger_count      4
dm.abits                6
dm.progbufsize          2
dm.sbversion            0
dm.sbasize              0
dm.sbaccess128          0
dm.sbaccess64           0
dm.sbaccess32           0
dm.sbaccess16           0
dm.sbaccess8            0
```

* Add `riscv info` command.

This command displays some basic information that OpenOCD has detected
about the target. The output is displayed in YAML so it can easily be
parsed. Example of current output:
```
Hart:
  XLEN: 32
  trigger count: 4
Debug Module:
  abits: 6
  progbufsize: 2
  sbversion: 0
  sbasize: 0
  sbaccess128: 0
  sbaccess64: 0
  sbaccess32: 0
  sbaccess16: 0
  sbaccess8: 0
```

Change-Id: If920c083ff6ec9f482c50f913cd8ceaa62461217
Signed-off-by: Tim Newsome <tim@sifive.com>

* Disable workflow inherited from upstream.

Change-Id: Ifc5ed1b4f5ec2278b8bcf3279c9fd462e469fefa
Signed-off-by: Tim Newsome <tim@sifive.com>

* Switch from YAML to TCL "set array" input format.

Change-Id: I3833210e5bf6d7cffc9934c04ec5201ae7732ad8
Signed-off-by: Tim Newsome <tim@sifive.com>

* Remove indent in `riscv info` output.

That was getting a little too cute, and probably more confusing than
helpful.

Change-Id: Ie51416f53ab4b69294962f0565767d370db82867
Signed-off-by: Tim Newsome <tim@sifive.com>
2020-12-14 12:40:08 -08:00
Tim Newsome f72e5bb0d8
Fix error handling in read_memory_progbuf_one(). (#560)
* Fix error handling in read_memory_progbuf_one().

Be sure to restore mstatus/s0 even if there is a failure during the
operation.

Fixes #559.

Change-Id: Ib86ca2c7455bad4a668f34703566060a782116db
Signed-off-by: Tim Newsome <tim@sifive.com>

* Style fix suggested in review.

Change-Id: I444112a9dffea483b7d0e5f96ef7bbdaf58d249f
Signed-off-by: Tim Newsome <tim@sifive.com>
2020-12-14 12:39:00 -08:00
Jan Matyas 5d0543cc1c
Clear sbcs.sbbusyerror without affecting other sbcs bits (#547)
This is a fix for an issue reported by Joe Stoy at:
https://sourceforge.net/p/openocd/mailman/message/37128537/

When clearing sbcs.sbbusyerror, preserve other bits in the sbcs
register that are needed for subsequent system bus transactions.
2020-12-14 12:32:31 -08:00
Antonio Borneo 1d3d87695c target/register: use an array of uint8_t for register's value
The use of 'void *' makes the pointer arithmetic incompatible with
standard C, even if this is allowed by GCC extensions.
The use of 'void *' can also hide incorrect pointer assignments.

Switch to 'uint8_t *' and add GCC warning flag to track any use of
pointer arithmetic extension.

Change-Id: Ic4d15a232834cd6b374330f70e2473a359b1607f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5937
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-12-05 23:18:37 +00:00
Antonio Borneo b5e015357a mips_mips64: fix minor host endianness bug
Commit 80f1a92bd7 ("mips64: Add generic mips64 target support")
adds a log of the target's program counter in function
mips_mips64_debug_entry() by directly casting the little-endian
buffer in pc->value.
This is going to print an incorrect value on big-endian hosts.

Use the function buf_get_u64() to return the register value.

Not tested on real HW. Issue identified with GCC compiler flag
'-Wcast-align=strict' after change http://openocd.zylin.com/5937/
("target/register: use an array of uint8_t for register's value").

Change-Id: Icbda2b54a03fdec287c804e623f5db4252f9cd2a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 80f1a92bd7 ("mips64: Add generic mips64 target support")
Reviewed-on: http://openocd.zylin.com/5944
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-12-05 23:18:33 +00:00
Antonio Borneo a56b729191 arm7_9_common: fix host endianness bug in arm7_9_full_context()
The original code passes to ->read_core_regs() and to
->read_xpsr() the pointer to the little-endian buffer reg.value.
This is incorrect because the two functions above require a
pointer to uint32_t, since they already run the conversion with
arm_le_to_h_u32() in the jtag callback.
This causes a mismatch on big-endian host and the registers get
read with the incorrect endianness.

Use an intermediate buffer to read the registers as uint32_t and
to track the destination reg.value pointer, then copy the value in
reg.value after the call to jtag_execute_queue().

Tested with qemu-armeb and an OpenOCD built through buildroot
configured for cortex-a7 big-endian.

Note that if jtag_execute_queue() fails, the openocd register
cache is not updated, so the already modified flags 'valid' and
'dirty' are incorrect. This part should be moved after the call to
jtag_execute_queue() too.

Change-Id: Iba70d964ffbb74bf0860bfd9d299f218e3bc65bf
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5943
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-12-05 23:18:29 +00:00
Antonio Borneo 62686ab161 armv4_5: fix output of command 'arm reg'
Commit fc2abe63fd ("armv7m: use generic arm::core_mode") adds
two special modes for ARMv6M and ARMv7M in struct arm_mode_data[].
While these modes do not have any additional register to be dumped
by command 'arm reg', the command still prints an header for these
modes but not followed by any register.

Detect the special modes for ARMv6M and ARMv7M and skip them to
avoid printing the useless header.

Change-Id: I04145769e5742624f143c910eebf9a6f6d8e3cdc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: fc2abe63fd ("armv7m: use generic arm::core_mode")
Reviewed-on: http://openocd.zylin.com/5942
Tested-by: jenkins
2020-12-05 23:18:22 +00:00
Antonio Borneo 693b8501e5 armv4_5: fix segmentation fault in command 'arm reg'
Commit fed7131049 ("armv4_5: support weirdo ARMv6 secure monitor
mode") introduces the secure mode 28 of ARMv6 as a synonymous of
mode 22 (MON), but does not add it in the switch/case in command
'arm reg'.
When command 'arm reg' scans the array arm_mode_data[] on targets
without secure modes, it does not detect the new secure mode as
not supported by the architecture, thus triggers a segmentation
fault when it try to read the register's value from unallocated
memory.
Issue detected with target arm926ejs.

Add the new mode in the switch/case and treat it as the mode MON.

Change-Id: I2b72cc558e097879a7ee6ea601200bfda6b60270
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: fed7131049 ("armv4_5: support weirdo ARMv6 secure monitor mode")
Reviewed-on: http://openocd.zylin.com/5941
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2020-12-05 23:18:15 +00:00
Marc Schink 7b641d3d4e Add initial RTT support
Real Time Transfer (RTT) is an interface specified by SEGGER based on
basic memory reads and writes to transfer data bidirectionally between
target and host.
Every target that supports so called "background memory access", which
means that the target memory can be accessed by the debugger while the
target is running, can be used.

RTT is especially of interest for targets which do not support Serial
Wire Output (SWO) (e.g. ARM Cortex-M0) or where using semihosting is
not possible (e.g. real-time applications) [1].

The data transfer is organized in channels where each channel consists
of an up- and/or down-channel. See [2] for more details.

Channels are exposed via TCP connections. One or more RTT server can be
assigned to each channel to make them accessible to an unlimited number
of TCP connections.

The current implementation does not respect buffer flags which are used
to determine what happens when writing to a full buffer.

Note that the implementation is designed in a way that the RTT
operations can be directly performed by an adapter (e.g. J-Link).

[1] https://devzone.nordicsemi.com/tutorials/6/
[2] https://www.segger.com/jlink-rtt.html

Change-Id: I8bc8a1b381fb74e08b8752d5cf53804cc573c1e0
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/4055
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-12-02 23:15:52 +00:00
Tomas Vanek d459a2d27d adi_v5_swd: wait for readable DPIDR, ABORT if stalled
Reading of DPIDR is the very first operation after JTAG to SWD sequence.
Without this change if DPIDR read fails then swd connect fails.

Keep trying JTAG to SWD sequence and DPIDR read until success
or timeout 0.5 sec. It makes setting of adapter srst delay on SWD transport
mostly unnecessary.

Also test for ERROR_WAIT (which should not occur according to
IHI 0031E B4.3.2 but a quirk is known) and if bus is kept stalled
then issue abort to make the next connect possible.

Change-Id: Id8fe6618605bbeb4fed5061e987ed55de90a35f2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5730
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-12-02 23:15:16 +00:00
Tomas Vanek 646c3c9902 arm_adi_v5: prevent possibly endless recursion in dap_dp_init()
If dap_dp_read_atomic() in 30 trials loop fails, dap->do_reconnect is set.
Following dap_dp_read_atomic() calls dap_queue_dp_read() which in case
of SWD transport calls swd_queue_dp_read(). It starts
with swd_check_reconnect() and it calls swd_connect() because
dap->do_reconnect is set. swd_connect() does some initialization,
reads DPIDR and calls dap_dp_init() again!

Moreover if dap_dp_init() is called from cortex_m_reset_(de)assert()
one level of recursion is necessary to reconnect the target.

Introduce dap_dp_init_or_reconnect() for use in cortex_m reset
and similar.
Remove loop of 30 atomic reads of DP_STAT to prevent unwanted recursion.

Change-Id: I54052fdefe50bf5f7c7b59fe751fe2063d5710c9
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5729
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-12-02 23:15:08 +00:00
Tomas Vanek b1f488ec1e target/armv7m, cortex_m: fix misleading comments
Change-Id: I4fea29f07f4d3b8b2578b538ef0eef5f1eea285f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5876
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-11-15 21:09:08 +00:00
Tomas Vanek f32ca2d25d target/cortex_m: remove wrong xPSR.ICI/IT bits handling
If a Cortex-M (not M0, M0+) target was stopped in the middle of
a conditional IT block or in the load/store multiple instruction,
cortex_m_debug_entry() used wrong xPSR bits to detect it and then
cleared 8 bits of the exception number from xPSR
- probably wrong bit mask again.

I believe clearing of the ICI/IT bits in cortex_m_debug_entry() has no
reason as Cortex-M does not use instruction injecting.

Remove the wrong code.

The change was originally a part of http://openocd.zylin.com/4862
It is now re-submitted as #4862 is not ready.

Change-Id: If91cd91d1b81b2684f7d5f10cf20452cde1a7f56
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5874
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-11-15 21:08:41 +00:00
Tomas Vanek fc91936be7 target/armv7m: use arch_info[i].value instead of allocated memory
Change-Id: I9422cab484d0769404516947e16da1baa001a4e0
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5328
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-11-15 21:08:26 +00:00
Antonio Borneo d811d2838b cortex_m: use the new enum ARMV7M_REGSEL_name
Register xPSR is indexed directly with its value 16 or with the
incorrect enum ARMV7M_xPSR.

Replace them with the new enum ARMV7M_REGSEL_xPSR.

Change-Id: I86600e7f78e39002ce45f66d4792d5067c1f541b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5873
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-11-15 21:08:14 +00:00
Tomas Vanek 62394a6b1c target/cortex_m,hla_target: rework Cortex-M register handling part 4
Consolidate low level register read/write.

Floating point registers were handled by target_read/write_u32
unlike other registers handled by cortexm_dap_read/write_coreregister_u32
There is no reason to do so in cortex_m.
Remove cortexm_dap_read/write_coreregister_u32
and use cortex_m_load/store_core_reg_u32 directly.

Similarly HLA adapters register read/write interface supports all registers
so use it for any floating point and other registers.

Change-Id: Ida679e5f4fec02d94ffb0bd3f265ed7ed2221cdc
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5864
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-11-15 21:06:45 +00:00
Tomas Vanek d3a37b0e76 target/armv7m: rework Cortex-M register handling part 3
Move primask/basepri/faultmask/control packing/unpacking from
cortex_m.c and hla_target.c to armv7m.c armv7m_read_core_reg()
and armv7m_write_core_reg() where also the FP 32/64-bit registers
conversion takes place.

Introduce a new hidden register ARMV7M_PMSK_BPRI_FLTMSK_CTRL
for packing/unpacking of special registers in the register cache.

The new packing/unpacking is endianess safe.

While on it improve returned error codes and LOG_ messages.

Just minimal changes in cortex_m.c and hla_target.c, will be
consolidated in the next patch.

Change-Id: Id51e764e243e54b5fdaadf2a202eee7c4bc729fe
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5863
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-11-15 21:06:23 +00:00
Tomas Vanek e4160bd422 target/armv7m: rework Cortex-M register handling part 2
Make arm register id coherent with reg_list index.
Without this reg_list[ARMV7M_R12] was possible but
reg_list[ARMV7M_FPSCR] was out of bounds.

Remove unused items from reg_list index.

Change-Id: I84d3b5c496fc1839d07a5b74cb1fd1c3d4ff8989
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5862
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
2020-11-15 21:06:00 +00:00
Tomas Vanek efbc447ed8 target/armv7m: rework Cortex-M register handling part 1
Define a new enum with DCRSR.REGSEL selectors.
Introduce armv7m_map_id_to_regsel() to unify mapping in one place.
Use DCRSR.REGSEL selectors for low level register read/write.

Change-Id: Ida0ccdfa9cdb1257a1900b8bfbf172b076374d39
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5327
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
2020-11-15 21:05:51 +00:00
Tomas Vanek f8453ae52c target, register: allow a register hidden from gdb and 'reg' cmd
Introduce a 'hidden' flag in struct reg to support a register cache
containing different views of same data: e.g. Cortex-M has
primask, basepri, faultmask and control registers accessed
as one word. With the hidden flag we can add an reg_list item
corresponding to hw access without exposing the register to user level.

All the struct reg are allocated with calloc() but one in xscale.c
allocated by malloc(). Change this one to use calloc() as well
to guarantee initial value hidden=false

Change-Id: I8da9f5a5a60777ae7ef943a841307487bd80fc6f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5325
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-11-15 21:05:37 +00:00
Antonio Borneo 109dc1975f flash/stmqspi: minor fixes on coding style
Add space around operators;
use BIT() macro in place of left shifting constant 1;
remove space between cast operator and value;
do not check a pointer before free() it;
add parenthesis around parameters in macros;
fix indentation using only TABs;
remove line continuation '\' at code lines out of macros.

Change-Id: I809e8ee72d7bfe49d0edf10afb36efe2458de77c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: e44539d66c ("Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface")
Reviewed-on: http://openocd.zylin.com/5932
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
2020-11-15 21:04:29 +00:00
Kevin Yang 06c7a53f1f target/cortex_m: Change sleep to running state
When the core is in sleep mode, the core is no longer retiring
instructions. Cortext M remains in "unknown" state. This patch converts
sleep mode to "running" state.

Change-Id: I1e9b6c9be51fd0f1f6ce81af9b1f5f9f1f43c661
Signed-off-by: Kevin Yang <kangyang@google.com>
Reviewed-on: http://openocd.zylin.com/5921
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2020-11-11 21:22:16 +00:00
Andreas Bolsch e44539d66c Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface
- write speed up to 150 kByte/s on STM32F469I-disco (due to
  SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI
  with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in
  dual 4-line mode or STM32H73BI-Disco in octal mode
- tested with STM32L476G-disco (64MBit flash, 3-byte addr),
  STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and
  STM32L476G-Disco (all 128Mbit flash, 3-byte addr),
  STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr)
  STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr)
  STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr)
  STM32H73BI-Disco, STM32H735G-Disco (512MBit octo-flash, DTR, 4-byte addr)
- suitable cfg for Discovery boards included
- limited parsing of SFDP data if flash device not hardcoded
  (tested only in single/quad mode as most devices either don't
  support SFDP at all or have empty(!) SFDP memory)
- 'set' command for auto detection override (e. g. for EEPROMs)
- 'cmd' command for arbitrary SPI commands (reconfiguration, testing etc.)
- makefile for creation of binary loader files
- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg
- tcl/board/stm32f7discovery.cfg removed as name is ambiguous
  (superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)
- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q
  with two W25Q256FV, and on Nucleo-L496ZP-P and Nucleo-L4R5ZI
  with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,
  STM32H747I-Disco, STM32H750B-Disco
- read/verify/erase_check uses indirect read mode to work around silicon bug in
  H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last
  bytes causes debug interface to hang)
- octospi supported only in single/dual 1-line, 2-line, 4-line
  and single 8-line modes, (not in hyper flash mode)

Requirements:
GPIOs must be initialized appropriately, and SPI flash chip be configured
appropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip
specific, cf. included cfg files. The driver infers most parameters from
current setting in CR, CCR, ... registers.

Change-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4321
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>
2020-11-08 22:46:00 +00:00
Antonio Borneo ad06fba6f0 target/arm7tdmi: remove unused/deprecated function parameter
The function arm7tdmi_clock_out() has one unused 'deprecated'
parameter.

Drop the unused 'deprecated' parameter and the FIXME above it.

Change-Id: Ia8de41f5b8258825faccc737bba622e44c81a7ea
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5912
Tested-by: jenkins
2020-11-07 20:53:26 +00:00
Kevin Yang 92ea7e41b9 target: Examine subsequent targets after failure
When a target examination fails, continue to examine subsequent targets.
Return the number of targets that failed to examine.

Change-Id: I883a0c445edc7eb00f496b79271d773771ec6b66
Signed-off-by: Kevin Yang <kangyang@google.com>
Reviewed-on: http://openocd.zylin.com/5855
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-11-07 20:52:26 +00:00
Marc Schink 73746d78b7 target/image: Use proper data types
While at it, fix some coding style issues.

Change-Id: Id521394d89e0bf787a6f812701c2cc0fe7e4e63f
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/5919
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-11-07 20:52:00 +00:00
Adrian Negreanu 850e85fa6f semihosting: print the semihosting operation id
Change-Id: If5c3568bd1c99a48ac492137f48da0d9764efe14
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Reviewed-on: http://openocd.zylin.com/5923
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
Reviewed-by: Tim Newsome <tim@sifive.com>
2020-11-07 20:50:16 +00:00
Tarek BOCHKATI 9cce6b3c76 armv7m: add a TCP channel to stream captured trace
When trace capturing the trace is enabled using 'tpiu_config internal'
(via the internal mode), OpenOCD can collect the trace buffers then append
it to a specified file or named pipe and propagate the trace to 'tcl_trace'
command.
This change is allowing OpenOCD to stream the captured trace over TCP.

When using this configuration OpenOCD acts like a server and multiple
clients can connect and receive the captured trace.

Example on STM32F7 running at 216MHz:
  itm port 0 on
  tpiu config internal :3344 uart off 216000000


Change-Id: Idea43e7e26e87b98a33da7fb9acf7ea50fe3b345
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5345
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-11-07 20:49:57 +00:00
Tarek BOCHKATI 7e6556b3ca server: permit the add_service function to return the created service
returning the created service seems useful:

as the only method to get the freshly created service is by getting the
last item in the services linked list, and this seems to be like an
intrusion to service internal mechanism.

possibly, we could get the service from a connection but this is possible
only from [new_connection|input|connection_closed]_handler_t, but this is
not always practical:
  example: armv7m: add a TCP channel to stream captured trace
           http://openocd.zylin.com/#/c/5345/
           here we poll for trace and broadcast to all connections
           outside of these xxx_handler_t functions

also, storing one of the connections in new_connection_handler_t and get
the service from it is possible, but this will make the code less readable.

Change-Id: I5fef1baecec1e054953c6faf5b99d864ecc97f02
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5717
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2020-11-07 20:49:53 +00:00
Antonio Borneo c8628541ae target/adi_v5_jtag: remove unused global variable
Change-Id: Ia4e8b90359c23f4be1d3677b44b0ebd063bb8dcc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5901
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-11-04 17:39:53 +00:00
Antonio Borneo 9d50f3f3af cortex_m: declare local functions as static
Functions that are not used outside the file should be declared as
static.

Change-Id: Ie81f6bdce91e2a1456364b47f30aa4d35c7ee7bc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5900
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
2020-11-04 17:39:47 +00:00
Antonio Borneo 5ca2301743 target: declare local symbols as static
Functions and variables that are not used outside the file should
be declared as static.

Change-Id: I9f97571a528f0cb3c3c26f873577ab16fdec3cdc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5895
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-11-04 17:39:17 +00:00
Antonio Borneo 65de0d3bfa target: handle command 'target current' when no target is present
Is it possible to run OpenOCD without any target, for example to
only dump the rom-tables of an arm dap, or to perform low level
jtag operations.
But without any target created, the command 'target current'
causes OpenOCD to abruptly exit.

Handle in command 'target current' the case of no targets.

Change-Id: Ide15cb13bec84b88ccc3e7126523c04a6d70e636
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5881
Tested-by: jenkins
2020-11-04 17:38:20 +00:00
Antonio Borneo e2e8a5f467 gdb_server: allow multiple GDB connections to selected targets
The default way of working is to have a single GDB attached to one
target, so OpenOCD accepts only one connection to the GDB port of
each targets and rejects any further connection.

There are some barely safe use cases in which it could get useful
having a second GDB connection to the same target.
One such use case is while using GDB as a 'non-intrusive memory
inspector', as explained in the OpenOCD documentation.
One GDB can be left running an infinite loop to dump some memory
area, or even analysing the content, while keeping a second GDB
ready for user interaction or spot memory check.

Add a target configure option to specify the maximum number of GDB
connections allowed for that target, keeping the default to 1.

Change-Id: I4985a602e61588df0b527d2f2aa5b955c93e125e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5865
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2020-11-04 17:37:59 +00:00
Antonio Borneo ec0c23a3ab target/arm_cti: use adiv5_jim_mem_ap_spot_configure()
To avoid code duplication, reorganize the code to replace
cti_configure() with adiv5_jim_mem_ap_spot_configure().

Reorganize 'struct arm_cti_object' and its sub-'struct arm_cti'
moving DAP and mem-AP info in a 'struct adiv5_mem_ap_spot'.
Replace cti_configure() with adiv5_jim_mem_ap_spot_configure().
Deprecate the use of '-ctibase' in favor of '-baseaddr'.

Change-Id: I43740a37c80de67c0f5e4dc79c3400b91a12e9e8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5869
Tested-by: jenkins
2020-11-04 17:37:25 +00:00
Antonio Borneo 080fab2ecd target/arm_adi_v5: add helper to get mem_ap spot in configure/cget
This is somehow an extension of existing adiv5_jim_configure(),
but includes the 'address' in the mem_ap.
Rewrite adiv5_jim_configure() using the new helper.

Change-Id: Ia7effeeece044004d459b45126ed4961a98b8568
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5857
Tested-by: jenkins
2020-11-04 17:36:13 +00:00
Christopher Head d05ef53cbd target: restore last run state after profiling
Now that it’s possible to start profiling from either a running or a
halted state, rather than unconditionally halting after profiling
finishes, it makes more sense to restore the processor to whatever state
(running or halted) it was in before profiling started.

Change-Id: If6f6e70a1a365c1ce3b348a306c435c220b8bf12
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5237
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-10-30 22:01:07 +00:00
Christopher Head d3aa2d3536 target/cortex_m: reduce duplication in profiling
The Cortex-M implementation of profiling contains a bunch of
conditionals and checks to handle both chips which have PCSR and chips
which do not. However, the net effect of the non-PCSR branches is
actually exactly the same as what target_profiling_default does. Rather
than duplicating this code, just detect the situation where PCSR isn’t
available and delegate to target_profiling_default.

Change-Id: I1be57ac77f983816ab6bf644a3cfca77b67d6f70
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5236
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-10-30 22:00:57 +00:00
Christopher Head a7502ee8b9 target: allow profiling from running
There are a handful of implementations of profiling. There is the
default implementation, which repeatedly halts and resumes the target,
sampling PC each time. There is the Cortex-M implementation, which
uses PCSR if available, otherwise falling back to halting and resuming
and sampling PC. There is the OR1K implementation, which reads NPC
repeatedly. Finally, there is the NDS32 implementation which uses some
kind of AICE commands with which I am unfamiliar.

None of these (with the possible exception of the NDS32
implementation) actually require the target to be halted when starting
profiling. The Cortex-M and OR1K actually resume the target as pretty
much their first action. The default implementation doesn’t do this,
but is written in such a way that the target just flips back and forth
between halted and running, and the code will do the right thing from
either initial state. The NDS32 implementation I don’t know about.

As such, for everything except NDS32, it is not really necessary that
the target be halted to start profiling. For the non-PCSR Cortex-M and
default implementations, there is no real harm in such a requirement,
because profiling is intrusive anyway, but there is no benefit. For
the PCSR-based Cortex-M and the OR1K, requiring that the target is
halted is annoying because it makes profiling more intrusive.

Remove the must-be-halted check from the target_profiling function.
Add it to the NDS32 implementation because I am not sure if that will
break when invoked with a running target. Do not add it to any of the
other implementations because they don’t need it.

Change-Id: I479dce999a80eccccfd3be4fa192c904f0a45709
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5235
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-10-30 22:00:49 +00:00
Evgeniy Didin 0d3a67b23f target/arc: introduce watchpoints support
With help of actionpoint mechanism now it is possible to introduce
watchpoints support for ARC.

Change-Id: I5887335d0ba38c15c377bc1d24a1ef36e138cf65
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5867
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-10-24 23:25:03 +01:00
Sylvain Chouleur 5e61d59c90 cortex_m: support control.FPCA
Bit 2 of control register is used if the processor includes the FP
extension

Change-Id: Ie21bc9de8cae5bad9d841e1908eff3aa0bb29d4b
Signed-off-by: Sylvain Chouleur <schouleur@graimatterlabs.ai>
Reviewed-on: http://openocd.zylin.com/5853
Reviewed-by: Sylvain Chouleur <sylvain.chouleur@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-10-22 21:19:12 +01:00
Tim Newsome 3cf46af271
Add before/after timestamps to memory sampling. (#550)
This lets a user see exactly what period of time was sampled, without
having to guess how much time the target was ignored in between bursts.

Change-Id: I5c0639528636bf1a88f249be3ba59bec28c001e2
Signed-off-by: Tim Newsome <tim@sifive.com>
2020-10-21 12:21:05 -07:00
Tim Newsome ccb21ab5ac
Merge pull request #549 from riscv/from_upstream_histogram
Merge upstream changes into this branches
2020-10-16 14:16:45 -07:00
Samuel Obuch bc1d689e6d
Allow riscv_semihosting without 16 bit access to memory with instructions (#544)
* Allow riscv_semihosting without 16 bit access to memory with instrustions

Signed-off-by: Samuel Obuch <sobuch@codasip.com>

* rename *_by_any_size to riscv_*_by_any_size
2020-10-16 09:19:53 -07:00
Tim Newsome e8379cda32 Make it build again.
Change-Id: I851cfb8811d8e5d25760c9fddaeb99d7af1fdf6f
Signed-off-by: Tim Newsome <tim@sifive.com>
2020-10-15 15:06:28 -07:00
Tim Newsome 7a933ea7ad Merge branch 'master' into from_upstream_histogram
Used histogram diff strategy, which was much better than the default.

Conflicts:
	doc/openocd.texi
	src/flash/nor/fespi.c
	src/jtag/drivers/libjaylink
	src/rtos/rtos.c
	src/target/riscv/batch.c
	src/target/riscv/encoding.h
	src/target/riscv/riscv-011.c
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv.h
	src/target/target.c
	tcl/target/gd32vf103.cfg

Change-Id: I1321f62ba719419e58f93b2195f2540bd62f50d2
2020-10-15 12:32:45 -07:00
Antonio Borneo 4fc61a2f9d riscv: fix compile error
The commit b68674a1da ("Upstream tons of RISC-V changes.") was
proposed well before commit 3ac010bb9f ("Fix debug prints when
loading to flash"), but the merge got in different order.
After latest merge, the master branch fails to compile.

Fix the compile error.

Change-Id: Ia3bd21d970d589343a3b9b2d58c89e0c49f30015
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5856
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
2020-10-14 11:05:22 +01:00
Tim Newsome b68674a1da Upstream tons of RISC-V changes.
These are all the changes from https://github.com/riscv/riscv-openocd
(approximately 91dc0c0c) made just to src/target/riscv/*. Some of the
new code is disabled because it requires some other target-independent
changes which I didn't want to include here.

Built like this, OpenOCD passes:
* All single-RV32 tests against spike.
* All single-RV64 tests against spike.
* Enough HiFive1 tests. (I suspect the failures are due to the test
suite rotting.)
* Many dual-RV32 (-rtos hwthread) against spike.
* Many dual-RV64 (-rtos hwthread) against spike.

I suspect this is an overall improvement compared to what's in mainline
right now, and it gets me a lot closer to getting all the riscv-openocd
work upstreamed.

Change-Id: Ide2f80c9397400780ff6780d78a206bc6a6e2f98
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/5821
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
2020-10-14 05:43:05 +01:00
Tobias Kaiser fb477376da
Do not throw error if RISC-V tselect unimplemented (#542)
* Do not throw error if RISC-V tselect unimplemented

A RISC-V hart without Trigger Module may not implement any of the
associated CSRs such as tselect according to the specification.
riscv_enumerate_triggers previously threw an error in this case, but
only on the first invocation due to r->triggers_enumerated being set
regardless of this. Due to the propagation of this error condition to
disable_triggers and riscv_openocd_step, such a hart would remain
halted after the first 'step' (or 'continue') of a debug session.

This problem can be reproduced with the Ibex RISC-V CPU when
the DbgTriggerEn parameter is set to zero.

This commit changes the behavior of riscv_enumerate_triggers to
return ERROR_OK when tselect was not readable. This fixes the
described malfunction.

Change-Id: Ie813cb119b03702fe708801b5f3581f9bf337243
Signed-off-by: Tobias Kaiser <kaiser@tu-berlin.de>

* Add debug message if RISC-V tselect not readable

Change-Id: Ic3ad5bff9de5c50142cad983f351ce0099cec5c8
Signed-off-by: Tobias Kaiser <kaiser@tu-berlin.de>

* RISC-V triggers: continue if tselect is unreadable

In riscv_enumerate_triggers, even if for one hart tselect cannot be
accessed, other harts might provide trigger support. For this reason,
"continue;" is the appropriate action on a read failure of tselect,
which indicates that triggers are not implemented, instead of
"return ERROR_OK;".

Change-Id: Ied56f3e237b76195a15bfde159532eda9d347d21
Signed-off-by: Tobias Kaiser <kaiser@tu-berlin.de>
2020-10-12 09:16:12 -07:00
Antonio Borneo 3ffa14b043 target/aarch64: fix use of 'target->private_config'
The function adiv5_jim_configure() casts the void pointer
'target->private_config' to a struct adiv5_private_config pointer.
This is tricky in case of aarch64, where the private data are in a
struct aarch64_private_config that has as first element the struct
adiv5_private_config.

While the current solution is working fine, it's not clean and
requires special attention for any further code development.

Override 'target->private_config' to the correct pointer while
calling adiv5_jim_configure().

Change-Id: Ic2fc047dd1e57013943d96e6d5879a919d1eb7b3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5847
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2020-10-11 15:53:52 +01:00
Kevin Yang 63d3640add target/aarch64: Use apnum setting
Change aarch64 to use ap-num setting if provided. Fall back to original
behavior of using first AP when ap-num is invalid.

Change-Id: I0d3624f75c86ba5fd5a322ac60856dbbb6e71eaf
Signed-off-by: Kevin Yang <kangyang@google.com>
Reviewed-on: http://openocd.zylin.com/5831
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-10-11 15:53:43 +01:00
Tim Newsome 6c1bd05088
Add memory sample feature (#541)
* Add memory sampling feature.

Currently only gets 10 samples per second, but the overall scaffolding
looks like it works.

Change-Id: I25a2bbcba322f2101c3de598c225f83c902680fa

* Basic memory sample speed-ups.

977 samples/second.

Change-Id: I6ea874f25051aca1cbe3aa2918567a4ee316c4be

* Add base64 dumping of sample buffer.

We can't just dump raw data, because the API we use to get data to the
"user" uses NULL-terminated strings.

Change-Id: I3f33faaa485a74735c13cdaad685e336c1e2095f

* WIP on optimizing PC sampling.

1k samples per second on my laptop, which is roughly double what it was.

Change-Id: I6a77df8aa53118e44928f96d22210df84be45eda

* WIP

Change-Id: I4300692355cb0cf997ec59ab5ca71543b295abb0

* Use small batch to sample memory.

5k samples/second. No error checking.

Change-Id: I8a7f08e49cb153699021e27f8006beb0e6db70ee

* Collect memory samples near continuously.

Rewrite OpenOCD's core loop to get rid of the fixed 100ms delay.
Now collecting 15k samples/second.

Change-Id: Iba5e73e96e8d226a0b5777ecac19453c152dc634

* Fix build.

Change-Id: If2fe7a0c77e0d6545c93fa0d4a013c50a9b9d896

* Fix the mess I left after resolving conflicts.

Change-Id: I96abd47a7834bf8f5e005ba63020f0a0cc429548

* Support 64-bit address in memory sampling.

* Support sampling 64-bit values.

* Better error reporting. WIP on 64-bit support.

* Speed up single 32-bit memory sample.

21k samples/second.

* WIP on review feedback.

Change-Id: I00e453fd685d173b0206d925090beb06c1f057ca

* Make memory sample buffers/config per-target.

Change-Id: I5c2f5997795c7a434e71b36ca4c712623daf993c

* Document, and add bucket clear option.

Change-Id: I922b883adfa787fb4f5a894db872d04fda126cbd
Signed-off-by: Tim Newsome <tim@sifive.com>

* Fix whitespace.

Change-Id: Iabfeb0068d7138d9b252ac127d1b1f949cf19632
Signed-off-by: Tim Newsome <tim@sifive.com>

* Document sample buffer full behavior.

Change-Id: Ib3c30d34b1f9f30cf403afda8fdccb850bc8b4df
Signed-off-by: Tim Newsome <tim@sifive.com>

* Actually clear the sample buffer in dump_sample_buf.

Change-Id: Ifda22643f1e58f69a6382abc90474659d7330ac5
Signed-off-by: Tim Newsome <tim@sifive.com>

* Use compatible string formatting.

Change-Id: Ia5e5333e036c1dbe457bc977fcee41983b9a9b77
Signed-off-by: Tim Newsome <tim@sifive.com>
2020-10-07 14:31:36 -07:00
Daniel Trnka 87b95ab212 target/cortex_m.c: vector_catch command checks if a target is examined
If a target is not examined, command vector_catch crashes while accessing
the debug_ap NULL pointer.

maskisr and reset_config commands don't require this check.

Change-Id: I949b6f6e8b983327dd98fbe403735141f8f0b5d6
Signed-off-by: Daniel Trnka <daniel.trnka@gmail.com>
Reviewed-on: http://openocd.zylin.com/5813
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-10-03 11:21:33 +01:00
Mete Balci d7d70c2719 target/aarch64: a64 disassembler
Add A64 (AArch64) Disassembler using Capstone framework.

Change-Id: Ia92b57001843b11a818af940a468b131e42a03fd
Signed-off-by: Mete Balci <metebalci@gmail.com>
[Antonio Borneo: Rebased on current HEAD]
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5004
Tested-by: jenkins
2020-10-03 11:21:15 +01:00
Tom Hebb e2cfd4e063
Improve support for GD32VF103 MCU (#538)
* riscv: work around buggy hart states during reset in some DMs

As described in the comment this change adds, the GD32VF103 DM reports
that the hart is in more than one state while it is resetting. Because
of this, the current code acknowledges resets before they actually
complete. This sometimes prevents havereset from getting cleared as
intended, leading to a spurious "Hart 0 unexpectedly reset!" message the
next time riscv_is_halted() gets called.

To work around this, check for the absence of the unavailable state
rather than the presence of the running or halted states. This behavior
is also arguably more true to the spec than what exists now: Section 3.2
states that "The system may take an arbitrarily long time to come out of
reset, as reported by allunavail, anyunavail."

Change-Id: I34e90a16233125608bce8e4c2414dbead637600e
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>

* riscv: support custom reset-assert scripts

The reset-assert event is used, if present, to override the default
reset logic for ARM and MIPS cores. Do the same for RISC-V so that
devices with buggy ndmreset functionality (like GD32VF103) or
nonstandard reset sequences can specify the appropriate logic in Tcl.

Change-Id: I5e12077d67509853edb8ef3ad3f037f293a5fbb6
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>

* tcl/target: support GD32VF103 RISC-V MCU

The GD32VF103 is a low-cost 32-bit RISC-V microcontroller with
peripherals that are more-or-less compatible with the STM32F103 ARM
microcontroller. It is available on several low-cost dev boards, such as
the Sipeed Longan Nano, which is what I am testing on.

Add initial support for this chip, including a workaround for a buggy
ndmreset line (i.e. one that doesn't actually trigger a reset) in its
integrated debug module. Use the existing GD32VF103 flash driver that
was ported from the vendor's code in commit 48e40f3513 ("Add support
for GD32VF103 flash").

Change-Id: Iadac47ceb5437b8e18f3d35901388f10fef9f876
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>

* tcl/target/gd32vf103: add main flash alias

The GD32VF103 creates an alias to either main flash or the bootloader at
0x0, depending on how it was booted. As such, we want to indicate to
debuggers that the memory at 0x0 is flash and so cannot support software
breakpoints. To do this, add an alias to the main flash in the config.
This isn't strictly accurate in the case where we're running the
bootloader, but it still suits our purpose of fixing breakpoint
behavior.

Change-Id: I9eb8462d354f096eee231c0e5e2bffa538a5903e
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
2020-10-01 11:06:11 -07:00
Samuel Obuch 6db3ed2c86
Improve riscv expose_[csrs|custom] commands (#536)
* Improve riscv expose_[csrs|custom] commands

* Add option to specify custom name for registers.
* Allow to call commands multiple times without loss of previous data.
* Make sure the commands can only be used in the config phase (before "init").
* Validity checks and warnings.
* Change commands to be per target.
* Fix memory leaks.
* Also fix unrelated memory leaks to keep valgrind happy.

Signed-off-by: Samuel Obuch <sobuch@codasip.com>

* fixes after review

* improve error message
2020-10-01 11:05:41 -07:00
Tom Hebb 2c909f8faa
riscv: remove unused riscv_error_t type (#539)
This seems to be completely unused in these two files. It was probably
accidentally copied from riscv-011.c, where it is used.

Change-Id: I3f7ad8b2d26b005d3ea4438e2b3ec46a6c801792
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
2020-09-28 09:46:47 -07:00
Tom Hebb db2e8ad10a
riscv: remove outdated documentation in riscv.c (#540)
These comments appear to have been copied from riscv-011.c, for which
they are accurate. However, it makes no sense to also have them in
riscv.c, because 1) none of the things described are actually in
riscv.c; and 2) riscv-013.c has an entirely different code structure,
meaning everything in the comment is an implementation detail of
riscv-011.c. Remove the copy in riscv.c and just leave the one in
riscv-011.c.

Change-Id: I2873af1522482681325525040b3caad2ddddce9d
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
2020-09-28 09:45:18 -07:00
Tim Newsome 13b2ed5ec5
Minor cleanups. (#537)
Requested in http://openocd.zylin.com/#/c/5821/9

Change-Id: I775d9dd3cc8642361d4d129a05053ee3d27b99bb
Signed-off-by: Tim Newsome <tim@sifive.com>
2020-09-28 09:41:08 -07:00
Marc Schink 67008e1bea Use capstone for ARM disassembler
Change-Id: I1c9bf3f8178d4a06babe23a918e4411833ebc418
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/4812
Tested-by: jenkins
Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-09-27 17:39:44 +01:00
Tarek BOCHKATI 762ddcb749 cortex_m: add detection of Cortex M35P and M55
Change-Id: I52599b2b09c2dc50c95d64059213c832d380ea31
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5799
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-09-20 14:35:48 +01:00
Tarek BOCHKATI f2c83fade3 cortex_m: read and display core security state
Change-Id: I0fce3c66af7e98df2dc2258daf0d6af661e29ae7
Signed-off-by: Laurent LEMELE <laurent.lemele@st.com>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5798
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-09-20 14:35:44 +01:00
Tarek BOCHKATI 6e33947899 armv8-m: add SecureFault exception
Change-Id: I4e1963631e834b6334bc917e956c2db4464b7b08
Signed-off-by: Laurent LEMELE <laurent.lemele@st.com>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5797
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-09-20 14:35:04 +01:00
Jan Matyas 11c4f89b32
Allocate RISC-V arch_info during target creation (#531)
* Allocate RISC-V arch_info during target creation

* Ensured that target->arch_info is allocated as soon as the
  target is created. Needed so that per-target config commands
  (e.g. "riscv set_mem_access") can be executed also in the
  OpenOCD's config phase (before calling "init").

* Added several assert()'s for safety.

Signed-off-by: Jan Matyas <matyas@codasip.com>

* Removed a TODO comment
2020-09-17 13:20:12 -07:00
Tim Newsome 1712dc2c54
{read_from,write_to}_buf -> buf_[sg]et_u{32,64} (#529)
Requested in http://openocd.zylin.com/#/c/5821/7/src/target/riscv/riscv-013.c

Change-Id: I764d77192e902466eed8a6ccf1042b42016afb7e
Signed-off-by: Tim Newsome <tim@sifive.com>
2020-09-15 11:40:37 -07:00
Tim Newsome d4bcd8846a
Make a couple variables static. (#528) 2020-09-15 11:39:32 -07:00
Samuel Obuch 22d771d20c
Allow to put breakpoints in memories without 16 bit access (#525)
* Allow to put breakpoints in memories without 16 bit access

Signed-off-by: Samuel Obuch <sobuch@codasip.com>

* tmp

* tmp

* tmp

* read/write by any size for breakpoints

* fix style for checkpatch
2020-09-14 08:00:59 -07:00
Samuel Obuch 2ea18ef7f6
Selection of memory access methods, aampostincrement detection (#508)
* Add flexible selection of memory access methods, detection of aampostincrement.

New configuration command introduced: "riscv set_mem_access".
It allows to specify which RISC-V memory access methods (progbuf,
sysbus and/or abstract access) should be tried and in which order
of priority.

Command "riscv set_prefer_sba" is left and works in backward
compatible way, but is marked as deprecated.

First time abstract memory access is executed, it is tried with
set aampostincrement bit. If the abstract command fails or the
address is not incremented correctly, aampostincrement will not
be used for any subsequent accesses.

Signed-off-by: Samuel Obuch <sobuch@codasip.com>

* remove unnecessary variable

* fix doc
2020-09-10 13:57:51 -07:00
Tim Newsome 2bde4a918a
Add empty usage strings back in. (#526)
Comment on #521 pointed out that they're required.
2020-09-10 13:53:27 -07:00
Antonio Borneo 3934483429 target: avoid checking for non NULL pointer to free it
The function free() can be called with a NULL pointer as argument,
no need to check the argument before. If the pointer is NULL, no
operation is performed by free().

Remove the occurrences of pattern:
	if (ptr)
		free(ptr);

In target/openrisc/jsp_server.c, an error is logged if the ptr was
already NULL. This cannot happen since the pointer was already
referenced few lines before and openocd would have been already
SIGSEGV in that case, so remove the log.

Change-Id: I290a32e6d4deab167676af4ddc83523c830ae49e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5809
Tested-by: jenkins
2020-09-05 20:47:11 +01:00
Stafford Horne a098a14eb5 openrisc: Fix segv jsp due to free of unallocated data
The prompt pointer in the jtag serial port is never zero'd or allocated.
Completely remove it since there is not much use for it as the target
software will provide the actual prompt.

Change-Id: Id95d8ccb9f725e53b9d03386b11d91eba1cd6ef4
Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-on: http://openocd.zylin.com/4093
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-09-05 18:11:54 +01:00
Antonio Borneo f788949651 openocd: fix command's usage string
The usage string should contain only the command parameters.
OpenOCD will automatically prepend the command name to the usage
string while dumping the usage or help message.

Remove the repeated command name from the usage string.

Change-Id: If10a0f1c254aee302b9ca08958390b7f21cdb21b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5824
Tested-by: jenkins
2020-09-05 17:13:10 +01:00
Antonio Borneo 42faa8a4bc target/arc: fix command's usage string
The usage string should contain only the command parameters.
OpenOCD will automatically prepend the command name to the usage
string while dumping the usage or help message.

Remove the repeated command name from the usage string.

Change-Id: I691094a6395acb0e4ea3bea2347ff38379002464
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5822
Tested-by: jenkins
2020-09-05 17:13:00 +01:00
Antonio Borneo 99add6227f target: use proper format with uint32_t
Modify the format strings to properly handle uint32_t data types.

While there, fix prototype mismatch between header and C file of
the function armv7a_l1_d_cache_inval_virt().

Change-Id: I434bd241fa5c38e0c15d22cda2295097050067f5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5818
Tested-by: jenkins
2020-09-05 17:12:39 +01:00
Antonio Borneo 47d29ebe11 adi_v5: use macro DP_APSEL_MAX to allocate struct adiv5_ap
Commit 11019a824d ("adi_v5: enforce check on AP number value")
introduces the macro DP_APSEL_MAX and use it in place of hardcoded
magic numbers for the upper limit of AP selection value.

Use the macro also while defining the array of struct adiv5_ap in
struct adiv5_dap.

Change-Id: I88f53ceb710f92a48a8026a365709fbf2d9e6912
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5806
Tested-by: jenkins
2020-09-05 17:11:11 +01:00
Samuel Obuch 3ac010bb9f Fix debug prints when loading to flash
While loading to flash with debug level at least 3,
OpenOCD tries to print the whole loaded bitstream.
This will be very-very-slow due to implementation of
conversion from buffer to string.

* fix condition on selected debug level in jtag/core.c
* replace slow buf_to_str function from helper/binarybuffer.c
  with faster but_to_hex_str function

Change-Id: I3dc01d5846941ca80736f2ed12e3a54114d2b6dd
Signed-off-by: Samuel Obuch <sobuch@codasip.com>
Reviewed-on: http://openocd.zylin.com/5800
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-09-05 16:48:08 +01:00
Tim Newsome 5e84c5dd8a
Fix usage for our RISC-V commands. (#521)
Change-Id: Ia4e020637aae2384af223b0210ef2aef6a14b31a
2020-09-03 11:59:48 -07:00
Tim Newsome 9357818bb9
Check malloc/calloc return values. (#517)
Should not affect anything, but requested in
http://openocd.zylin.com/#/c/5821/5/src/target/riscv/batch.c@28

Change-Id: Ib7185bd93eeb918e72872416ab6364f8776cff88
2020-09-03 11:57:25 -07:00
Jiuyang Liu 57b57989b4
user4 0x23 should be MSB. (#519)
Signed-off-by: Jiuyang Liu <jiuyang.liu@sifive.com>
2020-09-01 10:32:31 -07:00
Tim Newsome f5a44b0d14
Make checkpatch require Signed-off-by (#516)
* Make checkpatch require Signed-off-by

This will make it easier to send changes contributed here to mainline
OpenOCD.

(Intentionally not including the required line here to make sure I can't
just merge this.)

Change-Id: I089084d38f3e08859d62cf7eface405f37af4799

* Whitespace fix.

This PR isn't building on travis. Maybe because I only changed
.travis.yml. Here's a source change to force a build (hopefully).

Change-Id: I8a828fe1d56a1960bc4bfb91d3d2f3a0790ad571

* Can't check for signoff on sources alone.

Change-Id: I741a299b64bf14857a4e1807b254a7d270b2e466
Signed-off-by: Tim Newsome <tim@sifive.com>

* Actual whitespace fixes.

Why didn't this fail to build before?

Change-Id: I339c03c4ef96546dbef5f16e635921a4fdaf9b35
Signed-off-by: Tim Newsome <tim@sifive.com>
2020-08-31 13:20:46 -07:00
Tim Newsome 91dc0c0c8e
Add SPDX tags for RISC-V files. (#513)
Requested in http://openocd.zylin.com/#/c/5821/3

Change-Id: I95551a3311d8e128300bacdf463da7ab4edf29a0
2020-08-24 15:43:03 -07:00
Tim Newsome ad5f40af8d
Update encoding.h from riscv-opcodes (#514)
Rename dscratch to dscratch0, since that is what it's called in the
spec.

Change-Id: Id6271ae272e979cef69e8ef0577b23452fb84f51
2020-08-24 15:42:45 -07:00
Tim Newsome ca6b1eff1d
Update debug_defines.h from riscv-debug-spec (#515)
A ton of constants got a new prefix, so I made a lot of changes to
match, but no functional changes.

I did define DTM_DMI_MAX_ADDRESS_LENGTH	in batch.c. That definition
never should have been in debug_defines.h, which I missed during code
review.

Change-Id: If5d86660f84bb0a3f2865fb36ef05d6630486d8b
2020-08-24 15:42:29 -07:00
Tim Newsome 920497c62f
Mostly whitespace changes. (#511)
Requested in http://openocd.zylin.com/#/c/5821/3

Change-Id: I75e6d551091396fc6e81b3642ae44bafe358eed7
2020-08-21 12:56:04 -07:00
Tim Newsome c116dc50b2
Update to version 1.0 of the vector spec. (#505)
Accessing registers on targets that implement 0.9 or earlier will no
longer work. If you need that we can talk about making it a config
option.

Change-Id: I953b639cf9a92ee9b0422e035da57c1d07504237
2020-08-18 11:07:34 -07:00
Tim Newsome 53ec10b61d
Create `riscv repeat_read` command (#510)
* WIP, apply stash with conflicts.

Change-Id: Ia794bde419aa29161c68898d20e30527e69f5a31

* Fix conflict resolution problems.

Change-Id: I4cedc348cf613f98cc5a36886f37c568ca644238

* Add repeat_read command.

Only implemented for sba v1 right now, and poorly tested at that.

Change-Id: I1d9ff63e1dea14b3f6a9f8ba4dad53668bf8038b

* Hide bogus address in repeat_read

Change-Id: Ib66c1fa60df9c7fc7cc87880b0fddc52825b48aa

* WIP make repeat read work with progbuf.

Change-Id: I555f8b880c8bf0d1ed0f3f90c7987a5b516a7a79

* WIP

Change-Id: Ic567cea68355ae907e94bd25185a2c9be6fd798d

* Fix error handling when increment is non-zero.

Change-Id: I5a2f3f2ee948fd4e12c0443a542e85b7b5c5791a

* Correctly(?) handle failures when increment is 0.

I'm not 100% convinced that this ensures every read value shows up in
the output, but it ought to work.

Change-Id: I1af3e7174cf9d5e6f293456fb5ead629e17faaaa

* Don't crash when asked to read no data.

Change-Id: I4061b5c720a43a4f828384ab9eacc89557adfa05

* Remove unnecessary comment.

Change-Id: I1be3d699b86299339b3a830ca1ef13c9f5b9fe0f

* Document `riscv repeat_read`.

Change-Id: I4a0f071f38784b2de034f8c1b0ce75d6d2d326b2
2020-08-18 11:01:41 -07:00
Samuel Obuch c1c88dccee
Account for impebreak in size requirements for progbuf (#509)
* Account for impebreak in size requirements for progbuf

* add helper function
2020-08-17 13:07:11 -07:00
Antonio Borneo cd06642314 target: fix memory leaks on target_create() fail
There are failure cases of target_create() that are not checked.
Plus, in case of failure the memory allocated in not properly
released before returning error.

Check all the possible failure in target_create().
Change current_target only when target is successfully created.
Add the new target to all_targets list only when target is
successfully created.
Release all the allocated memory before quit on failure.
Use malloc() instead of calloc() for target->type, because the
struct will be fully populated with memcpy().

Change-Id: Ib6f91cbb50c28878e7c73dc070b17b8d7d4e902f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5776
Tested-by: jenkins
2020-08-08 22:17:43 +01:00
Mikhail Rasputin 6d45e485f9 target: fix registers reading from non examined target
If a target is not examined when the debugger tries to connect to it
then it can lead to undesired/undefined behavior.

In particular it leads to a zero pointer dereference on the aarch64.


Change-Id: I67f2b714ab8b2727fd36f3de16d7f9017b4c55fe
Signed-off-by: Mikhail Rasputin <mikhail.godlike.rasputin@yandex.ru>
Reviewed-on: http://openocd.zylin.com/5727
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-08-08 22:17:08 +01:00
Jan Matyas e2d3184eba
Fix of DMI batch scans over 64-bits (#432)
This fixes buffer overrun/data corruption during DMI scan batches
on targets with large value of dtmcs.abits > 30 (unusual, but within
the spec).
2020-08-07 08:39:43 -07:00
Antonio Borneo 7c66df13ef target/arm11: fix memory leaks, including register cache
There is no deinit_target method, so few memory allocations leak
at openocd exit.
Issue identified by tracking all calls to arm_dpm_setup().

Implement the method arm11_dpm_deinit() to free all the memory
allocated in arm11_dpm_init() and call it in the new
arm11_deinit_target().

NOT TESTED on real HW.

Change-Id: Icab86e290fc2db14f70eb84c8286357aadb02a35
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5694
Tested-by: jenkins
2020-08-02 10:48:52 +01:00
Antonio Borneo 768502403e target: use one second timeout while halting target at gdb attach
By default GDB timeouts after 2 seconds, even if this value can be
modified with GDB command "set remotetimeout".
On OpenOCD side, the default event for GDB attach is to halt the
target and wait it to halt. But here the default timeout of the
halt command is 5 seconds!
If the target cannot be halted (e.g. it's kept in reset by another
core or the debugger doesn't have enough privileges) then GDB will
timeout while OpenOCD is still waiting and is unable to
communicate with GDB.

Decrease the halt timeout to 1 second in the default GDB attach
event handler.

Change-Id: I231c740816bb6a0d74b0bc679a368a6cbfb34824
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5687
Tested-by: jenkins
2020-08-02 10:48:41 +01:00
Antonio Borneo 480ba8ca88 target: fix minor typos and duplicated words
Change-Id: I8deb0017dc66a243e3dd51e285aa086db500decd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5766
Tested-by: jenkins
2020-07-26 23:09:45 +01:00
Antonio Borneo f5cc8360fd target/arm720t: fix memory leak of register cache
There is no method to free the register cache, allocated in
arm720t_init_target().
Issue identified by tracking all calls to arm7tdmi_init_target().

Implement the method arm720t_deinit_target() by calling directly
arm7tdmi_deinit_target().

NOT TESTED on a real arm720t target.
Tested on a arm926ejs (SPEAr320) by hacking the target type and
pretending it is a xscale:
	sed -i s/arm926ejs/arm720t/ tcl/target/spear3xx.cfg

Change-Id: I53c1f46c1a355a710e8df01468b19220671569dc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5697
Tested-by: jenkins
2020-07-26 20:12:56 +01:00
Antonio Borneo 19aa77cc7f target/arm7tdmi: fix memory leak of register cache
There is no method to free the register cache, allocated in
arm7tdmi_init_target(), so we get a memory leak.
Issue identified by tracking all calls to arm_build_reg_cache().

Implement the method arm7tdmi_deinit_target() that in turn calls
arm7tdmi_free_reg_cache().

NOT TESTED on a real arm7tdmi target.
Tested on a arm926ejs (SPEAr320) by hacking the target type and
pretending it is a arm7tdmi:
	sed -i s/arm926ejs/arm7tdmi/ tcl/target/spear3xx.cfg

Change-Id: Iad465b708eb4ebb298725d7155fea76357e9045c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5696
Tested-by: jenkins
2020-07-26 20:12:48 +01:00
Antonio Borneo df1dcc27ee target/xscale: fix memory leak of register cache
There is no method to free the register cache, allocated in
xscale_build_reg_cache(), so we get a memory leak.
Issue identified by tracking all calls to arm_build_reg_cache().

Implement the method xscale_deinit_target() that in turn calls the
new xscale_free_reg_cache().
Fix leak of struct xscale.

NOT TESTED on a real xscale target.
Tested on a arm926ejs (SPEAr320) by hacking the target type and
pretending it is a xscale:
	sed -i s/arm926ejs/xscale/ tcl/target/spear3xx.cfg

Change-Id: Ibb2104c42411b76f4bb77c2fa387d1b85a3d2d5d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5695
Tested-by: jenkins
2020-07-26 20:12:34 +01:00
Antonio Borneo 580b8f5da0 target: fix memory leaks on targets based on arm9tdmi
Similarly to the fix for arm926ejs (also base on arm9tdmi), fix
the other targets based on arm9tdmi.
The fix for arm926ejs is tested on SPEAr320 target.

This fix is proposed separately because is not tested on a correct
target device, but tested on SPEAr320 by hacking the target type
and pretending it is the correct one, e.g.:
	sed -i s/arm926ejs/arm920t/ tcl/target/spear3xx.cfg

The memory leaks detected and fixed are:
- arm register cache;
- EmbeddedICE register cache;
- arm_jtag_reset_callback internal data;
- struct <target_type>_common.

Change-Id: I565f9a5bf144a9df78474434d86a64127ef0fbe5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5699
Tested-by: jenkins
2020-07-26 20:12:21 +01:00
Jiri Kastner 2f40d069a1 src/target/arm_adi_v5.c: add Cortex-A35 related entries
ROM Table registers:
https://developer.arm.com/documentation/100236/0100/debug/rom-table/rom-table-peripheral-identification-registers
Debug reisters:
https://developer.arm.com/documentation/100236/0100/debug/memory-mapped-debug-registers/external-debug-peripheral-identification-registers
PMU registers:
https://developer.arm.com/documentation/100236/0100/debug/pmu-registers/performance-monitors-peripheral-identification-registers
CTI registers:
https://developer.arm.com/documentation/100236/0100/debug/cti-registers/cti-peripheral-identification-registers

Change-Id: Ibd57d91fb9b66bc46929f4e93d0bf23c2a32f11a
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-on: http://openocd.zylin.com/5773
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2020-07-26 20:10:40 +01:00
Jiri Kastner 765c319277 src/target/arm_adi_v5.c: resorted ids
Change-Id: Ieeccf48254032244a86d6cd35793f8f6076527e9
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-on: http://openocd.zylin.com/5772
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-07-26 20:09:30 +01:00
Evgeniy Didin 8fea8460db target/arc: Introduce Actionpoints support
Actionpoint mechanism allows to setup HW breakpoints and watchpoints on Synopsys ARC CPUs.
This mechanism is controlled by DEBUG register and by a set of auxilary registers.
Each actionpoint is controlled by 3 aux registers: Actionpoint(AP) match mask(AP_AMM),
AP match value(AP_AMV) and AP control(AC).

Note: some fields of actionpoint_t structure will be used in further
support of watchpoints.

Change-Id: I4efb24675f247cc19d9122501c9e63c3126fcab4
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5763
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-07-26 20:08:21 +01:00
Tim Newsome 9ed6707716
Further deprecate `-rtos riscv`. (#499)
* Further deprecate `-rtos riscv`.

Now using `-rtos riscv` will result in a failure, which you can (until
the end of this year) bypass by adding `enable_rtos_riscv` to the
configuration.

Change-Id: Ic714c303dc1b00c19e8956609730c0f83c845cb6

* Make checkpatch happy.

Change-Id: I0469ec37d38ad2eadf25efb5b2b7ac88391c0f51
2020-07-17 14:57:23 -07:00
Antonio Borneo 996ff5bcfc coding style: add arguments to function prototypes
Issue identified by checkpatch script from Linux kernel v5.1 using
the command

	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types FUNCTION_ARGUMENTS -f {} \;

This patch also fixes an incorrect function prototype in zy1000.c.
ZY1000 minidriver implementation overrides the function
arm11_run_instr_data_to_core_noack_inner(), but the prototype is
not the same as in src/target/arm11_dbgtap.c and to avoid compile
error it was changed also the prototype of the called function
arm11_run_instr_data_to_core_noack_inner_default().

Change-Id: I476cda8cdb0e1e280795b3b43ca95c40d09e4a3d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5630
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-07-08 22:08:19 +01:00
Antonio Borneo e2315ccffd coding style: fix space separation
The checkpatch script from Linux kernel v5.1 complains about using
space before comma, before semicolon and between function name and
open parenthesis.
Fix them!

Issue identified using the command

	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types SPACING -f {} \;

The patch only changes amount and position of whitespace, thus
the following commands show empty diff
	git diff -w
	git log -w -p
	git log -w --stat

Change-Id: I1062051d7f97d59922847f5061c6d6811742d30e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5627
Tested-by: jenkins
2020-07-08 22:08:08 +01:00
Antonio Borneo bf34629294 coding style: fix print of hex values as decimal
It is an error to prefix with "0x" the print of values in decimal.
Replace the incorrect decimal format specifier with PRIx32.

Issue identified by checkpatch script from Linux kernel v5.1 using
the command

	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types PRINTF_0XDECIMAL -f {} \;

Change-Id: I2eb867ef654527b2737ba573a405ec8f97c6a739
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5624
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-07-08 22:07:56 +01:00
Antonio Borneo f29d157882 target/arm926ejs: fix memory leaks
The memory leaks detected and fixed are:
- arm register cache;
- EmbeddedICE register cache;
- arm_jtag_reset_callback internal data;
- struct arm926ejs_common.

Issue identified with valgrind.
Tested on SPEAr320 based on arm926ejs.

Change-Id: If2bed02c516051ce4d0eb29b204a3f3337fe5d6a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5698
Tested-by: jenkins
2020-07-08 22:07:38 +01:00
Tim Newsome 8b929c6497
Triggers with type=0 aren't real. (#496)
Fixes #491.

Change-Id: Id01adcc68d8c7d95f7e86d49d5d2b0c97c9fb1b0
2020-07-07 11:55:57 -07:00
Tim Newsome bbfc666eba
Merge pull request #494 from riscv/from_upstream
Get changes from upstream
2020-07-02 15:22:47 -07:00
Tim Newsome b50b8da476
Warn if we are asked to read/write 0 bytes. (#492)
Technically that might be OK, but in practice it probably indicates
something went wrong somewhere. Before this change OpenOCD would crash
if it happened.

Change-Id: I2500ba67ec282915dcf2b2488f2aac9fbfdb23a3
2020-07-01 08:28:27 -07:00
Tim Newsome 43463b30ed Merge branch 'riscv' into from_upstream
Change-Id: Ia9c5d7c7f0a4913c1af17e042266736943334c7f
2020-06-30 11:04:48 -07:00
Antonio Borneo 7c88e76a76 target: do not print an error on shutdown in target events
Before commit b3ce5a0ae5 ("target: use LOG_USER to print errors
in events") an error in an event handler was silently lost, while
now the associated message is printed out.

A "shutdown" command in a target event (e.g. in gdb-detach) causes
the event to end with error code ERROR_COMMAND_CLOSE_CONNECTION,
that triggers the error message:
	shutdown command invoked
	Error executing event <event-name> on target <target-name>:

The error code returned by the command "shutdown" is required to
stop the execution in a script/proc and avoid executing any
further command in the script/proc.
It is then normal to get an error code from the "shutdown" command
and it should not be printed out.

Intercept the return code of the event in case of "shutdown", then
skip scheduling other target events and return without printing
the incorrect error message.

Change-Id: Ia3085fb46beacb90a5e4bf0abf7c6e28bb9e6a9b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Laurent Lemele <laurent.lemele@st.com>
Reviewed-on: http://openocd.zylin.com/5710
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
2020-06-27 15:34:51 +01:00
Evgeniy Didin 057aed11a2 target/arc: Introduce L1I,L1D,L2 caches support
With this commit we introduce L1 and L2 cache
flush and invalidate operations which are necessary for
getting/setting actual data during memory r/w operations.

We introduce L2 cache support, which is not presented
on currently support EMSK board. But L2 is presented
on HSDK board, which soon will be introduced.

Change-Id: I2fda505a47ecb8833cc9f5ffe24f6a4e22ab6eb0
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5688
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-27 15:34:24 +01:00
Lucas 2e6904eef5 aarch64: Add support for debugging in HYP mode on ARMv8-A cores
When debugging an ARMv8-A/AArch32 target running HYP mode, OpenOCD would
throw the following error to GDB on most operations (step, set breakpoint):

	cannot read system control register in this mode

The mode in question is 0x1A, a privilege level 2 mode available on cores
that have the virtualization extensions (such as the Raspi 3).

Note: this mode is only used when running in AArch32 compatibility mode.

Signed-off-by: Lucas Jenss <public@x3ro.de>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Change-Id: Ia8673ff34c5b3eed60e24d8da57c3ca8197a60c2
Reviewed-on: http://openocd.zylin.com/5255
Tested-by: jenkins
Reviewed-by: Lucas Jenß <lucas.jenss@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-27 15:33:57 +01:00
Tim Newsome f0151889f0
Don't halt the algorith-running hart because another is halted. (#490)
This logic is a little tortured, but it still passes the semihosting
tests that were the cause for the recent rewrite.

Change-Id: Ic6760bb068621ab2a49feb0cf3998fc6957b5cfc
2020-06-25 17:33:56 -07:00
Tim Newsome 0b1b9e2034
Accept dmstatus.version==3 (0.14) (#489)
Fixes #485.

Change-Id: I60b3d68827ca726558bc28035c0b74c5cf0d9754
2020-06-25 15:34:48 -07:00
Tim Newsome e07613de33 Merge branch 'master' into from_upstream
Conflicts:
      .gitmodules
      .travis.yml
      jimtcl
      src/jtag/core.c
      src/jtag/drivers/ftdi.c
      src/jtag/drivers/libjaylink
      src/jtag/drivers/mpsse.c
      src/jtag/drivers/stlink_usb.c
      src/rtos/hwthread.c
      src/target/riscv/riscv-013.c
      src/target/riscv/riscv.c
      tcl/board/sifive-hifive1-revb.cfg

Change-Id: I2d26ebeffb4c1374730d2e20e6e2a7710403657c
2020-06-23 13:05:43 -07:00
Tim Newsome 03f943ae23
Step/resume off manual hardware triggers (#486)
* Accommodate users setting custom triggers.

RISC-V hardware supports many more triggers than gdb can communicate to
OpenOCD. Accommodate users that set triggers by writing tdata* directly,
by disable/step/reenable when a user has done that.

Note that users must set dmode in tdata1 for this behavior to work
properly. Triggers with dmode=0 are assumed to be set and handled by the
software that is being debugged.

Change-Id: Ib0751689c5553aae3a273395b10f5b98326fa066

* Enumerate triggers when resuming from a trigger

Otherwise when we connect to a target that's already halted due to a
trigger, we won't correctly step past it.

Change-Id: I23b9482fa9597af826770f9cebf247b7ba59f65c

* Also disable/reenable triggers around single step.

Gdb is smart enough to disable/step/resume if it set the triggers, but
if a user set them manually it also needs to happen.

Change-Id: I1251bd47199b6f15f61a93e3a521a53f2b677c5f

* Fix whitespace.

Change-Id: Icc240aecbc7e3e36ce4e4d784f5703304334ca13
2020-06-18 14:47:42 -07:00
Marc Schink 5a79481d3b target/armv7m_trace: Calculate prescaler for external capture devices
This fixes a regression introduced in "2dc88e1479f29ef0141b05bfcd907ad9a3e2d54c"

Change-Id: I04dc19ed30118a4c499b83732700b2ee0fdb67b6
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/5610
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-06-18 10:11:02 +01:00
Khem Raj 3c6592cf62
riscv: Avoid shadowing read_csr/write_csr macros (#483)
The name conflict is picked by compiler and it fails to compile for rv64
Fixes
src/target/riscv/riscv-011.c:1014:44: error: too many arguments provided to function-like macro invocation
static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
                                           ^
Signed-off-by: Khem Raj <raj.khem@gmail.com>
2020-06-16 11:37:44 -07:00
Antonio Borneo f0909fe9e5 coding style: fix multi-line dereferencing
Issue identified by checkpatch script from Linux kernel v5.1 using
the command

	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types MULTILINE_DEREFERENCE -f {} \;

Change-Id: Icba05613e22a72ecc3e6a0aad7cb6b479496146f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5629
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
2020-06-06 18:06:05 +01:00
Antonio Borneo 6f88aa0fb3 target/cortex_a: fix memory leak of register cache
There is no method to free the register cache, allocated in
armv4_5, so we get a memory leak.
Issue identified by valgrind.

Implement the method arm_free_reg_cache() and call it in cortex_a
deinit and to exit for error during arm_dpm_setup().
Tested on dual cortex-A stm32mp15x.
This change is inspired from similar fix in commit b01b5fe13a
("armv7m: Fix memory leak in register caching.").

The same allocation is also used by target types "arm7tdmi",
"arm9tdmi", "arm11" and "xscale" but they all lack the deinit
method and I do not have relevant HW to test the fix. For such
reasons they are not addressed in this patch.

Change-Id: I4da1e1f12e36ec245d1f3b11a4eafcbd9a1d2e25
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5693
Tested-by: jenkins
2020-06-06 18:05:29 +01:00
Antonio Borneo 061cae171c target/mem_ap: fix two memory leaks
The target mem_ap misses the method 'deinit_target' and does not
free the memory allocated during 'target create' and 'configure'.

Add the missing method and free the allocated memory.
Issue identified with valgrind.

Change-Id: If0d0114a75dd76a8b65c2d46d96c6085fd31a09d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5700
Tested-by: jenkins
2020-06-06 18:05:08 +01:00
Antonio Borneo 37330f89d7 target/cortex-m: enable C_DEBUGEN during examine
Current code for Cortex M does not set C_DEBUGEN as soon as
possible, (which means during target examine), but later-on either:
1) at command 'halt' (e.g. for 'gdb-attach' event);
2) at command 'soft_reset_halt';
3) at commands 'reset', 'reset halt' or 'reset init';
4) during polling, but only if the target:
    = enter in 'double fault', or
    = exit from a reset, or
    = halts (not possible if C_DEBUGEN is not set)

Plus, if commands in 1) or 2) are executed before the very first
poll of the target, the value of 'cortex_m->dcb_dhcsr' is used not
initialized while writing it back in DCB_DHCSR.

Another side effect of this situation is that it's possible to set
a HW breakpoint with the target running, while C_DEBUGEN is not
set. Accordingly to [1], C1.3.1 "Debug authentication":
    When DGBEN is LOW and DHCSR.S_HALT == 0:
    ...
    FPB breakpoints do not generate an entry to Debug state and,
    if no DebugMonitor exception is generated, will escalate to
    HardFault, Lockup, or be ignored.
On STM32MP15x I get HW breakpoint ignored, while on STM32F411 I
get HardFault.
E.g. following these steps:
- power-on a pre-flashed board that starts running the firmware;
- connect openocd, without halting or resetting the board;
- set a HW breakpoint to some address often executed;
- wait, but the board doesn't halt ...;
- type the command 'halt';
- if the Cortex-M has HardFault it would be visible and the fault
  is at the breakpoint address;
- if no HardFault then type the command 'resume';
- wait and the board will finally halt at the HW breakpoint.

A similar issue has been detected on Cortex-A code and fixed by
commit bff87a7f28 ("target/cortex_a: enable DSCR_HALT_DBG_MODE
during examine").
Follow the same approach and set C_DEBUGEN during examine.
Also, initialize 'cortex_m->dcb_dhcsr' during examine.

[1] ARM DDI 0403E "ARM v7-M Architecture Reference Manual"

Change-Id: I5b0b23403634f7dfce38f104bba9f59c33eb3e99
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5702
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Moritz Fischer <moritzf@google.com>
2020-06-06 18:04:36 +01:00
Tarek BOCHKATI 2d3bbcd566 arm_adi_v5: dap_ti_be_32_quirks_command minor simplification
use handle_command_parse_bool within dap_ti_be_32_quirks_command to make
it shorter and simpler.

Change-Id: Ice179cc477933b27e27235dc2ade23fe655e233d
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5708
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-06 18:03:12 +01:00
Tarek BOCHKATI cdb6918c87 arm_adi_v5: enhance command error reporting
avoid the usage of ERROR_COMMAND_SYNTAX_ERROR when
ERROR_COMMAND_ARGUMENT_INVALID is more adequate.

Change-Id: Ic9aaedb93fedd45efee1b39f8ea20185f01af2da
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5654
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-06 18:02:21 +01:00
Tommy Murphy 95a8cd9b5d
Don't use MMU in M mode - https://github.com/riscv/riscv-openocd/issu… (#479)
* Don't use MMU in M mode - https://github.com/riscv/riscv-openocd/issues/474

* Updated code based on feedback from @timsifive
2020-05-26 10:33:30 -07:00
Antonio Borneo 3b5a24c13b openocd: properly use jim data types
The jim library exports all the data types through typedef, so
there is no need to use the internal struct types.

Fix the few remaining inconsistencies in the code.

Change-Id: Id4ae0083563ea7a371833374e7b39f17158f66a4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5662
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
2020-05-24 21:36:43 +01:00
Ake Rehnman 2bc24c06d3 stm8 target: make adapter speed settings work
Previously the adapter speed settings were hard-coded to
connect with low speed then switch over to high speed
regardless what was mentioned in the cfg files. Now the
stm8 target intercept adapter speed settings and configure
the stm8 control registers accordingly.

Change-Id: I7419514e5214e4b43b9d51253cf5b7f04a233533
Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com>
Reviewed-on: http://openocd.zylin.com/5548
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-05-24 21:34:48 +01:00
Antonio Borneo ac05f929ed swim: fix adapter speed handling
SWIM transport only supports two adapter speeds:
- "low speed"  equal to 363 kHz (8 MHz / 22)
- "high speed" equal to 800 kHz (8 MHz / 10)

Replace the previous convention that use "0" or "1" for "low" or
"high" speed with the effective speed in kHz.
Rework the implementation of stlink_speed_swim().
Set low speed in the stm8 config files, because only low speed is
permitted at debug connection; the previous code ignores the
initial value.

Change-Id: I2484c9419a2c554c59eb6b9216339393ab0b54f3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5529
Tested-by: jenkins
2020-05-24 21:31:21 +01:00
Antonio Borneo ac18e960ce swim: abstract the transport in stm8 target
SWIM is implemented by (ab)using the HLA API. This was acceptable
when OpenOCD code did not provided a clear separation between
transports and related APIs. Still today SWIM in OpenOCD is only
supported by STLink, so the decision to re-use the HLA API was the
simpler way to implement it.
After commit efd1d64222 ("adapter: switch from struct
jtag_interface to adapter_driver") the transports API are better
split and SWIM can be implemented as a separate set of API. This
would open the possibility to extend OpenOCD for other adapters
that provide SWIM, e.g. versaloon, or through SPI emulation [1].

Introduce a new set of files swim.[ch] to handle the SWIM API.
Beside the API that almost match the transport low-level data
communication (system_reset, read_mem, write_mem), add a further
API reconnect. Today, inside HLA STLink code, the reconnect is
implemented by hacking the HLA API state(). Please notice that
due to this hack the return type is incorrect; stlink_usb_state()
returns ERROR_OK in SWIM mode, while its return type is enum
target_state. Ignore the type mismatch and still call the HLA API
state in the new SWIM API reconnect. Further commit will fix it.

[1] http://kuku.eu.org/?projects/stm8spi/stm8spi

Change-Id: I52018e1e2200cbd41af8e5031f7b35dc761b61d6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5528
Tested-by: jenkins
2020-05-24 21:29:42 +01:00
Tarek BOCHKATI ac870d80a9 arm_disassembler: fix typo 'ARM_UNKNOWN_INSTUCTION' to '.._INSTRUCTION'
Change-Id: I3a3d566fe96fb1497cf8337389e993e0f728a64b
Signed-off-by: Laurent LEMELE <laurent.lemele@st.com>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5657
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-05-24 21:26:47 +01:00
Tim Newsome 4f9e2d7171
Fix semihosting for multicore targets (#478)
* WIP making semihosting work with -rtos hwthread.

Change-Id: Icb46f3eeedc1391e8fdc73c3ad8036f20267eb2e

* More WIP.

Change-Id: I670a6e1ba2a13a6ef2ae303a99559a16fdd1bbfb

* Fix halting due to a trigger.

Change-Id: Ie7caa8dde9518bcd5440e34cf31ed0d30ebf29ad

* Fix multicore semihosting without halt groups.

Change-Id: I53587e5234308ed2cc30a7132c86e4c94eb176c4

* WIP

Change-Id: I40630543b08d8b533726cb3f63aa60a62be8ef40

* Fix single core semihosting.

This was the last bug!

Change-Id: I593abac027fa9707f48b7f58163d7089574a0e28

* Fix whitespace.

Change-Id: I285c152970b87864c63803fae61312e5b79dfe6d
2020-05-19 10:34:36 -07:00
Tim Newsome 1524487a13
Speed up SBA block reads roughly 2x. (#477)
* Speed up SBA block reads roughly 2x.

Change-Id: I4e4f5530d4abae7470fd00308361e727904367d2

* Fix whitespace.

Change-Id: I28a1269c489d051560a2455973f9a8574f35f487
2020-05-18 14:43:41 -07:00
Antonio Borneo 11c5efd2ec target/arc: fix build with clang
Commit da41bce3ae ("target/arc: introduce breakpoint
functionality") introduces a mismatch between the format string
and one int constant.

Change the format string to match the int constant.

Change-Id: I0d59552205551b90e165c0a2e3fef247ad0c7701
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: da41bce3ae ("target/arc: introduce breakpoint functionality")
Reviewed-on: http://openocd.zylin.com/5655
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2020-05-14 20:28:24 +01:00
Tim Newsome fcdb5d64ec
Make mem2array work with 64-bit addresses. (#475)
Change-Id: I805389dc9934db5affe3c8059d9630acede956c1
2020-05-14 10:19:24 -07:00
iosabi dadf46f618 cortex_m: make bit fields in cortex_m unsigned.
Expression like (0xffff << 16) evaluate to type int, which is not able
to hold that value, producing a warning when compiling with
-fsanitize=undefined. This patch makes most of the cortex_m constants
unsigned using the BIT() macro or appending "ul" when possible to fix
the undefined behavior warning.

Signed-off-by: iosabi <iosabi@protonmail.com>
Change-Id: I7af194305ef612d7a32e74eaf9f11dd85fa87f32
Reviewed-on: http://openocd.zylin.com/5583
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-05-12 06:05:45 +01:00
Antonio Borneo 59cc1f6629 coding style: open function's brace at beginning of new line
Issue identified by checkpatch script from Linux kernel v5.1 using
the command

	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types OPEN_BRACE -f {} \;

Change-Id: I6d1356ed11e2699525f384efb7556bc2efdc299f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5628
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
2020-05-09 14:41:31 +01:00
Antonio Borneo e41c3f78d1 coding style: wrap lines longer than 120 chars
The coding style is quite permissive allowing 120 chars per line,
but abuses are still present.
Fix them, wrapping the lines.

Change-Id: I94d66b651d759a60ec35f7ba115c43933e70ed69
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5626
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-05-09 14:40:52 +01:00
Antonio Borneo 1946b50dba coding style: let "else" follow the close brace
The statement "else" should not be on a new line when follows a
close brace '}'. Fix it!

Issue identified by checkpatch script from Linux kernel v5.1 using
the command

	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types ELSE_AFTER_BRACE -f {} \;

Change-Id: I8af247ec3f75a69713d7cb1e73881254d16c189e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5623
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
2020-05-09 14:40:14 +01:00
Antonio Borneo 185834ef8a coding style: add missing space when split strings
Long strings are split across few lines; usually split occurs at
the white space between two words.
Check that the space between the two words is still present.
While there, adjust the amount of space between words.

Issue identified by checkpatch script from Linux kernel v5.1 using
the command

	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types MISSING_SPACE -f {} \;

Change-Id: I28b9a65564195ba967051add53d1c848c7b8fb30
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5620
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
2020-05-09 14:39:44 +01:00
Antonio Borneo 4f459660a9 coding style: avoid unnecessary line continuations
Line continuation, adding a backslash as last char of the line, is
requested in multi-line macro definition, but is not necessary in
the rest of C code.

Remove it where present.

Identified by checkpatch script from Linux kernel v5.1 using the
command

	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types LINE_CONTINUATIONS -f {} \;

Change-Id: Id0c69e93456731717a7b290b16580e9f8ae741bc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5619
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
2020-05-09 14:39:29 +01:00
Antonio Borneo e66bb9d312 coding style: add parenthesis around the argument of sizeof
The script checkpatch available in new Linux kernel offers an
experimental feature for automatically fix the code in place.
While still experimental, the feature works quite well for simple
fixes, like parenthesis.

This patch has been created automatically with the script under
review for inclusion in OpenOCD, using the command:

	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types SIZEOF_PARENTHESIS --fix-inplace -f {} \;

Change-Id: I8adb325bdb0e13211f8bae8b4770ec1979c176bf
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5618
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
2020-05-09 14:39:19 +01:00
Antonio Borneo 9b29cb58ac coding style: remove useless break after a goto or return
In a switch/case statement, a break placed after a goto or return
is never executed.
The script checkpatch available in Linux kernel v5.1 issues a
warning for such unused break statements.
In the process of reviewing the new checkpatch for its inclusion
in OpenOCD, let's get rid of these warnings.

The script checkpatch is unable to fixup automatically this case.
Thanks to having "break" command using a single code line, this
patch has been generated using the script below:

	find src/ -type f -exec ./tools/scripts/checkpatch.pl -q \
	 --types UNNECESSARY_BREAK -f {} \; \
	| sed -n '/^#/{s/^.*FILE: //;s/:$//;s/:/ /;p}' \
	| awk 'function P() {print "sed -i '\''"b"'\'' "a};
	       {
	         if ($1!=a) {
	           if (a) {P()};
	           a=$1;
	           b=$2"{d}";
	         } else {
	           b=b";"$2"{d}"
	         }
	       };
	       END {P()}'

Change-Id: I56ca098faa5fe8d1e3f712dc0a029a3f10559d99
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5617
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
2020-05-09 14:39:05 +01:00
Evgeniy Didin da41bce3ae target/arc: introduce breakpoint functionality
With this patch we introduce set/unset breakpoints
routines and add/remove bp handlers.
Currently soft breakpoints are only supported.

Changes since v1:
* Change if-statement in arc_remove_breakpoint
* Squash changes from http://openocd.zylin.com/#/c/5641/
  in this commit to fix build.

Change-Id: Ib10ccdb02fd1606e4f407f012b1bee106a8ffccd
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5641
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-05-08 21:23:05 +01:00
Evgeniy Didin c693508f77 target/arc: introduce arc_read/write_instruction functions
This commit introduces helper instruction read/write functions
for further bp functionality.

Change-Id: I619fbe2870ef6365c29ed1618bb83b6f7eb84690
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5640
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-05-08 15:09:46 +01:00
Evgeniy Didin 0af37282c7 target/arc: Add initial stepping functions
Change-Id: I84845f2ec6f1cff975990f0a495165a02de33227
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5643
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-05-08 05:57:12 +01:00
Tim Newsome 0c3e50a06a
Don't cache PC, but do cache DPC. (#473)
This fixes a bug where we read PC and marked it cached without actually
updating the cached value. The DPC value was correctly marked as valid
and updated.

Change-Id: Id6d3e94a96b981688b06f7f4a998019f2c02f6f5
2020-05-06 08:43:59 -07:00
Tim Newsome 55dd7e83ca
Add awareness of halt group cause. (#472)
Change-Id: I7f7b967ccaa3d1ff05a7e7d0c2a7ba4fa7d68ac0
2020-05-06 08:42:38 -07:00
Tomas Vanek e888fe3987 target/armv7m: cosmetic refactorization
Introduce a variable 'size' and reduce the number of dereferencing
*reg_list_size by using the variable.

Change-Id: I3bdf1485a4ed8e34435e8acb3efd0df8d802508c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5326
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-05-03 21:42:23 +01:00
Antonio Borneo 6572dd97b3 coding style: src: remove empty lines at end of text files
Empty lines at end of text files are useless.
Remove them.

Change-Id: Ibac9b36682d58f81e34ca2b51e6260e7d472fb0e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5172
Tested-by: jenkins
2020-05-02 15:40:21 +01:00
Kevin Burke 86cf8d9fb0 target/armv8: Add ARM target name on halt status
The CPU target name is added to the HALT status message so the user
can see which target halted at the designated program counter.

Tested on an Ampere eMAG8180 and Quicksilver silicon

Change-Id: I51e6f21296c85a822df28c5b7c4068e8ff66f29e
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-on: http://openocd.zylin.com/5571
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-04-24 17:39:41 +01:00
Tim Newsome e6e281197f
Cache accesses through riscv_[sg]et_register. (#467)
* Cache accesses through riscv_[sg]et_register.

This helps a lot with the address translation code, which checks satp
over and over again. Now satp is only read once per halt. It should also
help in a few other cases (but I don't have a good test setup to really
measure the impact).

Change-Id: I90392cc60d2145a70cf6c003d6a956dc9f3c0cc4

* Fix whitespace.

Change-Id: I05c5342d8a461cd8c618a3f60296925e9e84643f

* Don't read registers that we know don't exist.

Change-Id: Ie5c6226b3d4ecb6cf8f0d8954a52fda88e6e5bdd
2020-04-21 14:58:59 -07:00
Tomas Vanek ff9ee132e5 target/armv7m: minor fixes of target algo exit point check
Introduce a new ERROR_TARGET_ALGO_EXIT as currently used
ERROR_TARGET_TIMEOUT should be reserved for the timeout only.

Do not load PC directly from CPU HW as the register value
has already been cached.

Change-Id: I0d3630da41fd021676789dc12b52545cc0432ba8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5329
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2020-04-21 16:49:02 +01:00
Florian Fainelli 5c6e32612d Remove BUILD_TARGET64
BUILD_TARGET64 creates a larger test matrix and mostly gates the
building of the aarch64/armv8 target, make that unconditional, which
would help fixing any issues with 64-bit address types anyway.

Rebased by Antonio Borneo after commit 1fbe8450a9 ("mips: Add
MIPS64 support")

Change-Id: I219f62b744d540d9dde9a42e6b63fd7d91df3dbb
Suggested-by: Matthias Welwarsky <matthias@welwarsky.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5240
Tested-by: jenkins
2020-04-21 12:55:41 +01:00
Evgeniy Didin ea4f98046f target/arc: remove saving context during reset
In arc_poll() function we handle the cases, when jtag indicates, that
processor is halted, but target->state is not TARGET_HALTED.
In case, when processor was halted and target->state was TARGET_RUNNING,
we should save context. At the same time if target->state was TARGET_RESET
we do not need to save context.

Changes: 16.04:
Fix - Move setting target->state = TARGET_HALT after
"target->state == TARGET_RUNNIG" check, otherwise
this check makes no sense

Change-Id: I92ab6ec71cf58273bb8401d14a562035de3deab4
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5524
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-04-20 18:22:53 +01:00
Tim Newsome 2e9aad8914
Don't propagate failure to read satp in riscv_mmu() (#466)
If we return failure, then the caller will think something's wrong. But
it could very well be that the hardware doesn't have SATP, in which case
we should just report that the MMU is disabled.

This fixes a bug where flashing wasn't using the target algorithm
because allocating a work area failed.

Change-Id: I16e8e660036d3f8584c0b17e842c4ec8961a8410
2020-04-13 12:53:26 -07:00
Antonio Borneo 17ac52360f cortex_m: remove deprecation for soft_reset_halt
The command "soft_reset_halt" is deprecated since mid 2013 with
the commit 146dfe3295 ("cortex_m: deprecate soft_reset_halt").
Nevertheless it is still extremely useful with multicore chips
where it allows to reset only one of the cores, option not
available through asserting the chip-wide srst.
It also get useful to handle the reset on some problematic chip,
as in http://openocd.zylin.com/5489

Replace the warning about deprecation with a more light debug
message.

Change-Id: I52de6359475ba31014ae77e596a87fe88b252177
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5514
Tested-by: jenkins
Reviewed-by: Edward Fewell <efewell@ti.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2020-04-12 22:03:22 +01:00
Antonio Borneo 4873503ae4 cortex_a: don't wait for target halted in deassert_reset()
The tcl script src/target/startup.tcl has already the proper
centralized support to wait for all targets to halt after the
command "reset halt". The extra wait in cortex_a_deassert_reset()
is not required.
This extra wait is also an issue for multi-core support, because
waiting for one core to halt can delay the halt request to the
other cores.

Replace the indirect call to cortex_a_halt(), that embeds the wait
for halt, with a low-level halt sequence.

The on-going work on the reset framework is compatible with this
change; in fact it keeps in startup.tcl the wait for targets to
halt, even if current code proposal for cortex_a simply removes
the function cortex_a_deassert_reset().

Change-Id: Ic661c3791a29ba7d520e31f85a61f939a646feb5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5472
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2020-04-12 22:03:00 +01:00
Tim Newsome 464407cfd2
Expose FPRs as single and double for F and D. (#465)
If a hart support both F and D, then expose the FPRs as a union of float
and double. Fixes #336.

Change-Id: I3d4503bbf9281d6380c51259388cd01d399b94d6
2020-04-10 13:32:12 -07:00
Jan Matyas 25efc15069 target: added events TARGET_EVENT_STEP_START and _END
Events TARGET_EVENT_STEP_START and TARGET_EVENT_STEP_END
have been added - analogous to already existing events
TARGET_EVENT_RESUME_*.

This is an example of a concrete use case where having
these events is important:

In RISC-V processors without Debug Program Buffer, OpenOCD
cannot execute fence/fence.i when resuming or single-
stepping. With these events implemented, the user can
instead provide custom operations to achieve that same
effect prior to resuming the processor.

Change-Id: I786348ff08940759d99b0f24e9e0ed5a44581094
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: http://openocd.zylin.com/5551
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
2020-04-09 11:06:39 +01:00
Tarek BOCHKATI 4ce4aa752b armv8: log the register name which we failed to read or write
when openocd fails to read armv8 register, the user is not informed
which register has caused the error.

for example, in AArch32 state ESR_EL3 read/write is not supported,
thus armv8_dpm_read_current_registers is always failing without mentioning
which register has caused the error.

Change-Id: I24c5abbda9fac24fb77a01777ed15261aeaaf800
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5516
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-04-05 14:11:43 +01:00
Tim Newsome cbb15587dc
Document default values for some config options. (#461)
Change-Id: I4373b9487ea11664d3a6ea7ea10e99ea6d337232
2020-03-27 11:21:02 -07:00
Tim Newsome 3967f48843
Fix some clang static checker complaints. (#464)
The OpenOCD project looks at this, so once in a while I go through and
make sure our code is OK.

Change-Id: I50032c847f30e93604d83d6366cfad85918d6e66
2020-03-27 11:20:48 -07:00
Evgeniy Didin f00070edaf target/arc_cmd: Improve argument checks for commands
Add more argument check for "add-reg" command.

Changes since first revision:
-Removed arguments limitation(50 maximum) for "arc_set_reg_exists".

Changes:
25.03:
Removed inconsistency in "add-reg" function. Actually
"-type" option is optional and if it is not set,
register type is "int".

Change-Id: Ia21e6baf4fbda162f7811cd0fe305fc86ddafcfd
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5523
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-27 07:09:41 +00:00
Marc Schink 5ceae0eef4 target: Add possibility to remove all breakpoints
Change-Id: I46acd57956846d66bef974e0538452462b197cd0
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4916
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-26 19:30:45 +00:00
Marc Schink 9960e805b3 target: Add function to remove all breakpoints
Change-Id: I4718926844a2c8bcfd78d7a8792f6ded293548ef
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4915
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-26 19:30:34 +00:00
Tim Newsome 5b2426a4b2
Deal with vlenb being unreadable. (#458)
Instead of exiting during examine(), spit out a warning, and don't
expose the vector data registers. We do provide access to the vector
CSRs, because maybe they do work? It's just that we have no idea what
the size of the data registers is.

Change-Id: I6e9ffeb242e2e22fc62cb1b50782c2efb4ace0bd
2020-03-26 09:08:56 -07:00
Tim Newsome f6f30fb148
Update to 1.11 privileged spec. (#455)
Change-Id: I25029f7e83819464e71528fb4225b4761787793f
2020-03-18 12:24:22 -07:00
Marc Schink aff486b6a0 rtos: Destroy RTOS and fix memory leak
The memory leak can be reproduced by using an arbitrary RTOS
and valgrind:

 $ valgrind --leak-check=full --show-leak-kinds=all

[...]
==9656== 224 (80 direct, 144 indirect) bytes in 1 blocks are definitely lost in loss record 3 of 3
==9656==    at 0x483CD99: calloc (in /usr/lib/x86_64-linux-gnu/valgrind/vgpreload_memcheck-amd64-linux.so)
==9656==    by 0x1C541A: os_alloc (rtos.c:79)
==9656==    by 0x1C569E: os_alloc_create (rtos.c:111)
==9656==    by 0x1C569E: rtos_create (rtos.c:153)
==9656==    by 0x1AE332: target_configure (target.c:4899)
==9656==    by 0x1AF228: jim_target_configure (target.c:4952)
==9656==    by 0x1C9EF9: command_unknown (command.c:1066)
==9656==    by 0x313284: JimInvokeCommand (jim.c:10364)
==9656==    by 0x313FB6: Jim_EvalObj (jim.c:10814)
==9656==    by 0x3154A3: Jim_EvalFile (jim.c:11207)
==9656==    by 0x316015: Jim_SourceCoreCommand (jim.c:15230)
==9656==    by 0x313284: JimInvokeCommand (jim.c:10364)
==9656==    by 0x313B8B: JimEvalObjList (jim.c:10605)
[...]

Change-Id: I2cd41a154fb8570842601ff4e3e76502f5908f49
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/5479
Tested-by: jenkins
Reviewed-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-17 16:40:14 +00:00
Antonio Borneo b5d2b1224f target/cortex_a: add hypervisor mode
Hypervisor mode is present only if the optional virtualization
extensions are available. Moreover, virtualization extensions
require that also security extensions are implemented.

Add the required infrastructure for the shadowed registers in
hypervisor mode.
Make monitor shadowed registers visible in hypervisor mode too.
Make hypervisor shadowed registers visible in hypervisor mode
only.
Check during cortex_a examine if virtualization extensions are
present and then conditionally enable the visibility of both
hypervisor and monitor modes shadowed registers.

Change-Id: I81dbb1ee8baf4c9f1a2226b77c10c8a2a7b34871
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5261
Tested-by: jenkins
2020-03-12 10:11:19 +00:00
Antonio Borneo 6900c5af4e armv7a: access monitor registers only with security extensions
Accordingly to ARM DDI 0406C at B1.5, the security extensions for
armv7a are optional extensions and can be detected by reading
ID_PFR1.
The monitor mode is part of the security extensions and the shadow
registers "sp_mon", "lr_mon" and "spsr_mon" are only present with
the security extensions.

Read the register ID_PFR1 during cortex_a examine, determine if
security extension is present and then conditionally enable the
visibility of the monitor mode shadow registers.

Change-Id: Ib4834698659046566f6dc5cd35b44de122dc02e5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5259
Tested-by: jenkins
2020-03-12 10:10:33 +00:00
Antonio Borneo 9626402c5a target/armv4_5: remove unused macro
The macro ARMV4_5_CORE_REG_MODENUM() is unused.
Remove it!

Change-Id: I183df57bd86c9428710ea3583e43fba88fd26e0a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5260
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org>
2020-03-12 10:09:15 +00:00
Antonio Borneo fba438fde7 arm: Use different enum for core_type and core_mode
The fields core_type and core_mode use the same enum arm_mode
but encode different information, making the code less immediate
to read.

Use a different enum arm_core_type for the field core_type.
The code behavior is not changed.

Change-Id: I60f2095ea6801dfe22f6da81ec295ca71ef90466
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5258
Tested-by: jenkins
2020-03-12 10:05:42 +00:00