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target/armv7m: rework Cortex-M register handling part 1 

Define a new enum with DCRSR.REGSEL selectors.
Introduce armv7m_map_id_to_regsel() to unify mapping in one place.
Use DCRSR.REGSEL selectors for low level register read/write.

Change-Id: Ida0ccdfa9cdb1257a1900b8bfbf172b076374d39
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5327
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
This commit is contained in:
Tomas Vanek 2019-10-20 10:12:32 +02:00 committed by Antonio Borneo
parent f8453ae52c
commit efbc447ed8
4 changed files with 189 additions and 102 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
src/target/armv7m.c
View File

@ -211,6 +211,40 @@ static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
return ERROR_OK;
}
static uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
{
switch (arm_reg_id) {
case ARMV7M_R0 ... ARMV7M_R14:
case ARMV7M_PC:
case ARMV7M_xPSR:
case ARMV7M_MSP:
case ARMV7M_PSP:
/* NOTE: we "know" here that the register identifiers
* match the Cortex-M DCRSR.REGSEL selectors values
* for R0..R14, PC, xPSR, MSP, and PSP.
*/
return arm_reg_id;
case ARMV7M_FPSCR:
return ARMV7M_REGSEL_FPSCR;
case ARMV7M_D0 ... ARMV7M_D15:
return ARMV7M_REGSEL_S0 + 2 * (arm_reg_id - ARMV7M_D0);
/* TODO: remove. This is temporary hack until packing/unpacking
* of special regs is moved to armv7m.c */
case ARMV7M_PRIMASK:
case ARMV7M_BASEPRI:
case ARMV7M_FAULTMASK:
case ARMV7M_CONTROL:
return arm_reg_id;
default:
LOG_ERROR("Bad register ID %u", arm_reg_id);
return arm_reg_id;
}
}
static int armv7m_read_core_reg(struct target *target, struct reg *r,
int num, enum arm_mode mode)
{
@ -223,22 +257,23 @@ static int armv7m_read_core_reg(struct target *target, struct reg *r,
armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
uint32_t regsel = armv7m_map_id_to_regsel(armv7m_core_reg->num);
if ((armv7m_core_reg->num >= ARMV7M_D0) && (armv7m_core_reg->num <= ARMV7M_D15)) {
/* map D0..D15 to S0..S31 */
size_t regidx = ARMV7M_S0 + 2 * (armv7m_core_reg->num - ARMV7M_D0);
retval = armv7m->load_core_reg_u32(target, regidx, &reg_value);
retval = armv7m->load_core_reg_u32(target, regsel, &reg_value);
if (retval != ERROR_OK)
return retval;
buf_set_u32(armv7m->arm.core_cache->reg_list[num].value,
0, 32, reg_value);
retval = armv7m->load_core_reg_u32(target, regidx + 1, &reg_value);
retval = armv7m->load_core_reg_u32(target, regsel + 1, &reg_value);
if (retval != ERROR_OK)
return retval;
buf_set_u32(armv7m->arm.core_cache->reg_list[num].value + 4,
0, 32, reg_value);
} else {
retval = armv7m->load_core_reg_u32(target,
armv7m_core_reg->num, &reg_value);
regsel, &reg_value);
if (retval != ERROR_OK)
return retval;
buf_set_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32, reg_value);
@ -261,24 +296,24 @@ static int armv7m_write_core_reg(struct target *target, struct reg *r,
armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
uint32_t regsel = armv7m_map_id_to_regsel(armv7m_core_reg->num);
if ((armv7m_core_reg->num >= ARMV7M_D0) && (armv7m_core_reg->num <= ARMV7M_D15)) {
/* map D0..D15 to S0..S31 */
size_t regidx = ARMV7M_S0 + 2 * (armv7m_core_reg->num - ARMV7M_D0);
uint32_t t = buf_get_u32(value, 0, 32);
retval = armv7m->store_core_reg_u32(target, regidx, t);
retval = armv7m->store_core_reg_u32(target, regsel, t);
if (retval != ERROR_OK)
goto out_error;
t = buf_get_u32(value + 4, 0, 32);
retval = armv7m->store_core_reg_u32(target, regidx + 1, t);
retval = armv7m->store_core_reg_u32(target, regsel + 1, t);
if (retval != ERROR_OK)
goto out_error;
} else {
uint32_t t = buf_get_u32(value, 0, 32);
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, t);
retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->num, t);
retval = armv7m->store_core_reg_u32(target, regsel, t);
if (retval != ERROR_OK)
goto out_error;
}

112
src/target/armv7m.h
View File

@ -34,36 +34,100 @@ extern const int armv7m_msp_reg_map[];
const char *armv7m_exception_string(int number);
/* Cortex-M DCRSR.REGSEL selectors */
enum {
ARMV7M_REGSEL_R0,
ARMV7M_REGSEL_R1,
ARMV7M_REGSEL_R2,
ARMV7M_REGSEL_R3,
ARMV7M_REGSEL_R4,
ARMV7M_REGSEL_R5,
ARMV7M_REGSEL_R6,
ARMV7M_REGSEL_R7,
ARMV7M_REGSEL_R8,
ARMV7M_REGSEL_R9,
ARMV7M_REGSEL_R10,
ARMV7M_REGSEL_R11,
ARMV7M_REGSEL_R12,
ARMV7M_REGSEL_R13,
ARMV7M_REGSEL_R14,
ARMV7M_REGSEL_PC = 15,
ARMV7M_REGSEL_xPSR = 16,
ARMV7M_REGSEL_MSP,
ARMV7M_REGSEL_PSP,
ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL = 0x14,
ARMV7M_REGSEL_FPSCR = 0x21,
/* 32bit Floating-point registers */
ARMV7M_REGSEL_S0 = 0x40,
ARMV7M_REGSEL_S1,
ARMV7M_REGSEL_S2,
ARMV7M_REGSEL_S3,
ARMV7M_REGSEL_S4,
ARMV7M_REGSEL_S5,
ARMV7M_REGSEL_S6,
ARMV7M_REGSEL_S7,
ARMV7M_REGSEL_S8,
ARMV7M_REGSEL_S9,
ARMV7M_REGSEL_S10,
ARMV7M_REGSEL_S11,
ARMV7M_REGSEL_S12,
ARMV7M_REGSEL_S13,
ARMV7M_REGSEL_S14,
ARMV7M_REGSEL_S15,
ARMV7M_REGSEL_S16,
ARMV7M_REGSEL_S17,
ARMV7M_REGSEL_S18,
ARMV7M_REGSEL_S19,
ARMV7M_REGSEL_S20,
ARMV7M_REGSEL_S21,
ARMV7M_REGSEL_S22,
ARMV7M_REGSEL_S23,
ARMV7M_REGSEL_S24,
ARMV7M_REGSEL_S25,
ARMV7M_REGSEL_S26,
ARMV7M_REGSEL_S27,
ARMV7M_REGSEL_S28,
ARMV7M_REGSEL_S29,
ARMV7M_REGSEL_S30,
ARMV7M_REGSEL_S31,
};
/* offsets into armv7m core register cache */
enum {
/* for convenience, the first set of indices match
* the Cortex-M3/-M4 DCRSR selectors
* the Cortex-M DCRSR.REGSEL selectors
*/
ARMV7M_R0,
ARMV7M_R1,
ARMV7M_R2,
ARMV7M_R3,
ARMV7M_R0 = ARMV7M_REGSEL_R0,
ARMV7M_R1 = ARMV7M_REGSEL_R1,
ARMV7M_R2 = ARMV7M_REGSEL_R2,
ARMV7M_R3 = ARMV7M_REGSEL_R3,
ARMV7M_R4,
ARMV7M_R5,
ARMV7M_R6,
ARMV7M_R7,
ARMV7M_R4 = ARMV7M_REGSEL_R4,
ARMV7M_R5 = ARMV7M_REGSEL_R5,
ARMV7M_R6 = ARMV7M_REGSEL_R6,
ARMV7M_R7 = ARMV7M_REGSEL_R7,
ARMV7M_R8,
ARMV7M_R9,
ARMV7M_R10,
ARMV7M_R11,
ARMV7M_R8 = ARMV7M_REGSEL_R8,
ARMV7M_R9 = ARMV7M_REGSEL_R9,
ARMV7M_R10 = ARMV7M_REGSEL_R10,
ARMV7M_R11 = ARMV7M_REGSEL_R11,
ARMV7M_R12,
ARMV7M_R13,
ARMV7M_R14,
ARMV7M_PC = 15,
ARMV7M_R12 = ARMV7M_REGSEL_R12,
ARMV7M_R13 = ARMV7M_REGSEL_R13,
ARMV7M_R14 = ARMV7M_REGSEL_R14,
ARMV7M_PC = ARMV7M_REGSEL_PC,
ARMV7M_xPSR = 16,
ARMV7M_MSP,
ARMV7M_PSP,
ARMV7M_xPSR = ARMV7M_REGSEL_xPSR,
ARMV7M_MSP = ARMV7M_REGSEL_MSP,
ARMV7M_PSP = ARMV7M_REGSEL_PSP,
/* this next set of indices is arbitrary */
/* following indices are arbitrary, do not match DCRSR.REGSEL selectors */
ARMV7M_PRIMASK,
ARMV7M_BASEPRI,
ARMV7M_FAULTMASK,
@ -137,7 +201,7 @@ enum {
};
#define ARMV7M_NUM_CORE_REGS (ARMV7M_xPSR + 1)
#define ARMV7M_NUM_CORE_REGS_NOFP (ARMV7M_NUM_CORE_REGS + 6)
#define ARMV7M_NUM_CORE_REGS_NOFP (ARMV7M_CONTROL + 1)
#define ARMV7M_COMMON_MAGIC 0x2A452A45
@ -159,8 +223,8 @@ struct armv7m_common {
struct armv7m_trace_config trace_config;
/* Direct processor core register read and writes */
int (*load_core_reg_u32)(struct target *target, uint32_t num, uint32_t *value);
int (*store_core_reg_u32)(struct target *target, uint32_t num, uint32_t value);
int (*load_core_reg_u32)(struct target *target, uint32_t regsel, uint32_t *value);
int (*store_core_reg_u32)(struct target *target, uint32_t regsel, uint32_t value);
int (*examine_debug_reason)(struct target *target);
int (*post_debug_entry)(struct target *target);

64
src/target/cortex_m.c
View File

@ -1607,29 +1607,25 @@ void cortex_m_enable_watchpoints(struct target *target)
}
static int cortex_m_load_core_reg_u32(struct target *target,
uint32_t num, uint32_t *value)
uint32_t regsel, uint32_t *value)
{
int retval;
/* NOTE: we "know" here that the register identifiers used
* in the v7m header match the Cortex-M3 Debug Core Register
* Selector values for R0..R15, xPSR, MSP, and PSP.
*/
switch (num) {
case 0 ... 18:
switch (regsel) {
case ARMV7M_REGSEL_R0 ... ARMV7M_REGSEL_PSP:
/* read a normal core register */
retval = cortexm_dap_read_coreregister_u32(target, value, num);
retval = cortexm_dap_read_coreregister_u32(target, value, regsel);
if (retval != ERROR_OK) {
LOG_ERROR("JTAG failure %i", retval);
return ERROR_JTAG_DEVICE_ERROR;
}
LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
LOG_DEBUG("load from core reg %" PRIu32 " value 0x%" PRIx32 "", regsel, *value);
break;
case ARMV7M_FPSCR:
case ARMV7M_REGSEL_FPSCR:
/* Floating-point Status and Registers */
retval = target_write_u32(target, DCB_DCRSR, 0x21);
retval = target_write_u32(target, DCB_DCRSR, ARMV7M_REGSEL_FPSCR);
if (retval != ERROR_OK)
return retval;
retval = target_read_u32(target, DCB_DCRDR, value);
@ -1638,16 +1634,16 @@ static int cortex_m_load_core_reg_u32(struct target *target,
LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
break;
case ARMV7M_S0 ... ARMV7M_S31:
case ARMV7M_REGSEL_S0 ... ARMV7M_REGSEL_S31:
/* Floating-point Status and Registers */
retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
retval = target_write_u32(target, DCB_DCRSR, regsel);
if (retval != ERROR_OK)
return retval;
retval = target_read_u32(target, DCB_DCRDR, value);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
(int)(num - ARMV7M_S0), *value);
(int)(regsel - ARMV7M_REGSEL_S0), *value);
break;
case ARMV7M_PRIMASK:
@ -1658,9 +1654,9 @@ static int cortex_m_load_core_reg_u32(struct target *target,
* in one Debug Core register. So say r0 and r2 docs;
* it was removed from r1 docs, but still works.
*/
cortexm_dap_read_coreregister_u32(target, value, 20);
cortexm_dap_read_coreregister_u32(target, value, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
switch (num) {
switch (regsel) {
case ARMV7M_PRIMASK:
*value = buf_get_u32((uint8_t *)value, 0, 1);
break;
@ -1678,7 +1674,7 @@ static int cortex_m_load_core_reg_u32(struct target *target,
break;
}
LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
LOG_DEBUG("load from special reg %" PRIu32 " value 0x%" PRIx32 "", regsel, *value);
break;
default:
@ -1689,51 +1685,47 @@ static int cortex_m_load_core_reg_u32(struct target *target,
}
static int cortex_m_store_core_reg_u32(struct target *target,
uint32_t num, uint32_t value)
uint32_t regsel, uint32_t value)
{
int retval;
uint32_t reg;
struct armv7m_common *armv7m = target_to_armv7m(target);
/* NOTE: we "know" here that the register identifiers used
* in the v7m header match the Cortex-M3 Debug Core Register
* Selector values for R0..R15, xPSR, MSP, and PSP.
*/
switch (num) {
case 0 ... 18:
retval = cortexm_dap_write_coreregister_u32(target, value, num);
switch (regsel) {
case ARMV7M_REGSEL_R0 ... ARMV7M_REGSEL_PSP:
retval = cortexm_dap_write_coreregister_u32(target, value, regsel);
if (retval != ERROR_OK) {
struct reg *r;
LOG_ERROR("JTAG failure");
r = armv7m->arm.core_cache->reg_list + num;
r = armv7m->arm.core_cache->reg_list + regsel; /* TODO: don't use regsel as register index */
r->dirty = r->valid;
return ERROR_JTAG_DEVICE_ERROR;
}
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
LOG_DEBUG("write core reg %" PRIu32 " value 0x%" PRIx32 "", regsel, value);
break;
case ARMV7M_FPSCR:
case ARMV7M_REGSEL_FPSCR:
/* Floating-point Status and Registers */
retval = target_write_u32(target, DCB_DCRDR, value);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
retval = target_write_u32(target, DCB_DCRSR, ARMV7M_REGSEL_FPSCR | DCRSR_WnR);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
break;
case ARMV7M_S0 ... ARMV7M_S31:
case ARMV7M_REGSEL_S0 ... ARMV7M_REGSEL_S31:
/* Floating-point Status and Registers */
retval = target_write_u32(target, DCB_DCRDR, value);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
retval = target_write_u32(target, DCB_DCRSR, regsel | DCRSR_WnR);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
(int)(num - ARMV7M_S0), value);
(int)(regsel - ARMV7M_REGSEL_S0), value);
break;
case ARMV7M_PRIMASK:
@ -1744,9 +1736,9 @@ static int cortex_m_store_core_reg_u32(struct target *target,
* in one Debug Core register. So say r0 and r2 docs;
* it was removed from r1 docs, but still works.
*/
cortexm_dap_read_coreregister_u32(target, &reg, 20);
cortexm_dap_read_coreregister_u32(target, &reg, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
switch (num) {
switch (regsel) {
case ARMV7M_PRIMASK:
buf_set_u32((uint8_t *)&reg, 0, 1, value);
break;
@ -1764,9 +1756,9 @@ static int cortex_m_store_core_reg_u32(struct target *target,
break;
}
cortexm_dap_write_coreregister_u32(target, reg, 20);
cortexm_dap_write_coreregister_u32(target, reg, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
LOG_DEBUG("write special reg %" PRIu32 " value 0x%" PRIx32 " ", regsel, value);
break;
default:

62
src/target/hla_target.c
View File

@ -51,7 +51,7 @@ static inline struct hl_interface_s *target_to_adapter(struct target *target)
}
static int adapter_load_core_reg_u32(struct target *target,
uint32_t num, uint32_t *value)
uint32_t regsel, uint32_t *value)
{
int retval;
struct hl_interface_s *adapter = target_to_adapter(target);
@ -62,21 +62,21 @@ static int adapter_load_core_reg_u32(struct target *target,
* in the v7m header match the Cortex-M3 Debug Core Register
* Selector values for R0..R15, xPSR, MSP, and PSP.
*/
switch (num) {
case 0 ... 18:
switch (regsel) {
case ARMV7M_REGSEL_R0 ... ARMV7M_REGSEL_PSP:
/* read a normal core register */
retval = adapter->layout->api->read_reg(adapter->handle, num, value);
retval = adapter->layout->api->read_reg(adapter->handle, regsel, value);
if (retval != ERROR_OK) {
LOG_ERROR("JTAG failure %i", retval);
return ERROR_JTAG_DEVICE_ERROR;
}
LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
LOG_DEBUG("load from core reg %" PRIu32 " value 0x%" PRIx32 "", regsel, *value);
break;
case ARMV7M_FPSCR:
case ARMV7M_REGSEL_FPSCR:
/* Floating-point Status and Registers */
retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33);
retval = target_write_u32(target, ARMV7M_SCS_DCRSR, regsel);
if (retval != ERROR_OK)
return retval;
retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
@ -85,16 +85,16 @@ static int adapter_load_core_reg_u32(struct target *target,
LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
break;
case ARMV7M_S0 ... ARMV7M_S31:
case ARMV7M_REGSEL_S0 ... ARMV7M_REGSEL_S31:
/* Floating-point Status and Registers */
retval = target_write_u32(target, ARMV7M_SCS_DCRSR, num-ARMV7M_S0+64);
retval = target_write_u32(target, ARMV7M_SCS_DCRSR, regsel);
if (retval != ERROR_OK)
return retval;
retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
(int)(num - ARMV7M_S0), *value);
(int)(regsel - ARMV7M_REGSEL_S0), *value);
break;
case ARMV7M_PRIMASK:
@ -105,11 +105,11 @@ static int adapter_load_core_reg_u32(struct target *target,
* in one Debug Core register. So say r0 and r2 docs;
* it was removed from r1 docs, but still works.
*/
retval = adapter->layout->api->read_reg(adapter->handle, 20, value);
retval = adapter->layout->api->read_reg(adapter->handle, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL, value);
if (retval != ERROR_OK)
return retval;
switch (num) {
switch (regsel) {
case ARMV7M_PRIMASK:
*value = buf_get_u32((uint8_t *) value, 0, 1);
break;
@ -127,8 +127,8 @@ static int adapter_load_core_reg_u32(struct target *target,
break;
}
LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "",
(int)num, *value);
LOG_DEBUG("load from special reg %" PRIu32 " value 0x%" PRIx32 "",
regsel, *value);
break;
default:
@ -139,7 +139,7 @@ static int adapter_load_core_reg_u32(struct target *target,
}
static int adapter_store_core_reg_u32(struct target *target,
uint32_t num, uint32_t value)
uint32_t regsel, uint32_t value)
{
int retval;
uint32_t reg;
@ -148,46 +148,42 @@ static int adapter_store_core_reg_u32(struct target *target,
LOG_DEBUG("%s", __func__);
/* NOTE: we "know" here that the register identifiers used
* in the v7m header match the Cortex-M3 Debug Core Register
* Selector values for R0..R15, xPSR, MSP, and PSP.
*/
switch (num) {
case 0 ... 18:
retval = adapter->layout->api->write_reg(adapter->handle, num, value);
switch (regsel) {
case ARMV7M_REGSEL_R0 ... ARMV7M_REGSEL_PSP:
retval = adapter->layout->api->write_reg(adapter->handle, regsel, value);
if (retval != ERROR_OK) {
struct reg *r;
LOG_ERROR("JTAG failure");
r = armv7m->arm.core_cache->reg_list + num;
r = armv7m->arm.core_cache->reg_list + regsel; /* TODO: don't use regsel as register index */
r->dirty = r->valid;
return ERROR_JTAG_DEVICE_ERROR;
}
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
LOG_DEBUG("write core reg %" PRIu32 " value 0x%" PRIx32 "", regsel, value);
break;
case ARMV7M_FPSCR:
case ARMV7M_REGSEL_FPSCR:
/* Floating-point Status and Registers */
retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33 | (1<<16));
retval = target_write_u32(target, ARMV7M_SCS_DCRSR, ARMV7M_REGSEL_FPSCR | DCRSR_WnR);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
break;
case ARMV7M_S0 ... ARMV7M_S31:
case ARMV7M_REGSEL_S0 ... ARMV7M_REGSEL_S31:
/* Floating-point Status and Registers */
retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, ARMV7M_SCS_DCRSR, (num-ARMV7M_S0+64) | (1<<16));
retval = target_write_u32(target, ARMV7M_SCS_DCRSR, regsel | DCRSR_WnR);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
(int)(num - ARMV7M_S0), value);
(int)(regsel - ARMV7M_REGSEL_S0), value);
break;
case ARMV7M_PRIMASK:
@ -199,9 +195,9 @@ static int adapter_store_core_reg_u32(struct target *target,
* it was removed from r1 docs, but still works.
*/
adapter->layout->api->read_reg(adapter->handle, 20, &reg);
adapter->layout->api->read_reg(adapter->handle, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL, &reg);
switch (num) {
switch (regsel) {
case ARMV7M_PRIMASK:
buf_set_u32((uint8_t *) &reg, 0, 1, value);
break;
@ -219,9 +215,9 @@ static int adapter_store_core_reg_u32(struct target *target,
break;
}
adapter->layout->api->write_reg(adapter->handle, 20, reg);
adapter->layout->api->write_reg(adapter->handle, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL, reg);
LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
LOG_DEBUG("write special reg %" PRIu32 " value 0x%" PRIx32 " ", regsel, value);
break;
default: