flash/stmqspi: minor fixes on coding style
Add space around operators;
use BIT() macro in place of left shifting constant 1;
remove space between cast operator and value;
do not check a pointer before free() it;
add parenthesis around parameters in macros;
fix indentation using only TABs;
remove line continuation '\' at code lines out of macros.
Change-Id: I809e8ee72d7bfe49d0edf10afb36efe2458de77c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: e44539d66c ("Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface")
Reviewed-on: http://openocd.zylin.com/5932
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
This commit is contained in:
Antonio Borneo
parent
175f30e695
commit
109dc1975f
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@ -81,7 +81,7 @@ int spi_sfdp(struct flash_bank *bank, struct flash_device *dev,
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/* retrieve SFDP header */
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memset(&header, 0, sizeof(header));
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retval = read_sfdp_block(bank, 0x0, sizeof(header) >> 2, (uint32_t *) &header);
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retval = read_sfdp_block(bank, 0x0, sizeof(header) >> 2, (uint32_t *)&header);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("header 0x%08" PRIx32 " 0x%08" PRIx32, header.signature, header.revision);
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@ -105,7 +105,7 @@ int spi_sfdp(struct flash_bank *bank, struct flash_device *dev,
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}
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memset(pheaders, 0, sizeof(struct sfdp_phdr) * nph);
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retval = read_sfdp_block(bank, sizeof(header),
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(sizeof(struct sfdp_phdr) >> 2) * nph, (uint32_t *) pheaders);
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(sizeof(struct sfdp_phdr) >> 2) * nph, (uint32_t *)pheaders);
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if (retval != ERROR_OK)
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goto err;
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@ -132,7 +132,7 @@ int spi_sfdp(struct flash_bank *bank, struct flash_device *dev,
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LOG_DEBUG("word %02d 0x%08X", j + 1, ptable[j]);
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if (id == SFDP_BASIC_FLASH) {
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struct sfdp_basic_flash_param *table = (struct sfdp_basic_flash_param *) ptable;
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struct sfdp_basic_flash_param *table = (struct sfdp_basic_flash_param *)ptable;
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uint16_t erase;
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if (words < 9) {
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@ -215,7 +215,7 @@ int spi_sfdp(struct flash_bank *bank, struct flash_device *dev,
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LOG_INFO("device has to be switched to 4-byte addresses");
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}
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} else if (id == SFDP_4BYTE_ADDR) {
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struct sfdp_4byte_addr_param *table = (struct sfdp_4byte_addr_param *) ptable;
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struct sfdp_4byte_addr_param *table = (struct sfdp_4byte_addr_param *)ptable;
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if (words >= (offsetof(struct sfdp_4byte_addr_param, erase_t1234)
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+ sizeof(table->erase_t1234)) >> 2) {
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@ -40,6 +40,7 @@
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#endif
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#include "imp.h"
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#include <helper/bits.h>
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#include <helper/time_support.h>
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#include <target/algorithm.h>
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#include <target/armv7m.h>
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@ -137,7 +138,7 @@
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/* 4-byte address in octo mode, else 3-byte address for read SFDP */
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#define OCTOSPI_CCR_READ_SFDP(len) \
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((OCTOSPI_MODE_CCR & OCTOSPI_NO_DDTR & ~OCTOSPI_ADDR4 & OCTOSPI_NO_ALTB) | \
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((len < 4) ? OCTOSPI_ADDR3 : OCTOSPI_ADDR4))
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(((len) < 4) ? OCTOSPI_ADDR3 : OCTOSPI_ADDR4))
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#define OCTOSPI_CCR_WRITE_ENABLE \
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((OCTOSPI_MODE_CCR & OCTOSPI_NO_ADDR & OCTOSPI_NO_ALTB & OCTOSPI_NO_DATA))
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@ -153,17 +154,17 @@
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#define SPI_ADSIZE (((stmqspi_info->saved_ccr >> SPI_ADSIZE_POS) & 0x3) + 1)
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#define OPI_CMD(cmd) ((OPI_MODE ? ((((uint16_t) cmd)<<8) | (~cmd & 0xFFU)) : cmd))
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#define OPI_CMD(cmd) ((OPI_MODE ? ((((uint16_t)(cmd)) << 8) | (~(cmd) & 0xFFU)) : (cmd)))
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#define OCTOSPI_CMD(mode, ccr, ir) \
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({ \
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retval = target_write_u32(target, io_base + OCTOSPI_CR, \
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OCTOSPI_MODE | mode); \
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OCTOSPI_MODE | (mode)); \
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if (retval == ERROR_OK) \
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retval = target_write_u32(target, io_base + OCTOSPI_TCR, \
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(stmqspi_info->saved_tcr & ~OCTOSPI_DCYC_MASK) | \
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((OPI_MODE && (mode == OCTOSPI_READ_MODE)) ? \
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(OPI_DUMMY<<OCTOSPI_DCYC_POS) : 0)); \
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((OPI_MODE && ((mode) == OCTOSPI_READ_MODE)) ? \
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(OPI_DUMMY << OCTOSPI_DCYC_POS) : 0)); \
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if (retval == ERROR_OK) \
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retval = target_write_u32(target, io_base + OCTOSPI_CCR, ccr); \
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if (retval == ERROR_OK) \
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@ -177,7 +178,7 @@ static inline uint32_t h_to_le_32(uint32_t val)
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{
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uint32_t result;
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h_u32_to_le((uint8_t *) &result, val);
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h_u32_to_le((uint8_t *)&result, val);
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return result;
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}
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@ -248,10 +249,10 @@ static int poll_busy(struct flash_bank *bank, int timeout)
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endtime = timeval_ms() + timeout;
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do {
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spi_sr = READ_REG(SPI_SR);
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if ((spi_sr & (1U<<SPI_BUSY)) == 0) {
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if ((spi_sr & BIT(SPI_BUSY)) == 0) {
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if (retval == ERROR_OK) {
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/* Clear transmit finished flag */
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retval = target_write_u32(target, io_base + SPI_FCR, (1U<<SPI_TCF));
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retval = target_write_u32(target, io_base + SPI_FCR, BIT(SPI_TCF));
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}
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return retval;
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} else
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@ -278,7 +279,7 @@ static int set_mm_mode(struct flash_bank *bank)
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/* Abort any previous operation */
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retval = target_write_u32(target, io_base + SPI_CR,
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READ_REG(SPI_CR) | (1U<<SPI_ABORT));
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READ_REG(SPI_CR) | BIT(SPI_ABORT));
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if (retval != ERROR_OK)
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return retval;
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@ -321,7 +322,7 @@ static int read_status_reg(struct flash_bank *bank, uint16_t *status)
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/* Abort any previous operation */
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retval = target_write_u32(target, io_base + SPI_CR,
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READ_REG(SPI_CR) | (1U<<SPI_ABORT));
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READ_REG(SPI_CR) | BIT(SPI_ABORT));
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if (retval != ERROR_OK)
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return retval;
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@ -333,7 +334,7 @@ static int read_status_reg(struct flash_bank *bank, uint16_t *status)
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/* Read always two (for DTR mode) bytes per chip */
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count = 2;
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retval = target_write_u32(target, io_base + SPI_DLR,
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((stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? 2 * count : count) - 1);
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((stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 2 * count : count) - 1);
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if (retval != ERROR_OK)
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goto err;
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@ -354,11 +355,11 @@ static int read_status_reg(struct flash_bank *bank, uint16_t *status)
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*status = 0;
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/* for debugging only */
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(void) READ_REG(SPI_SR);
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(void)READ_REG(SPI_SR);
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for ( ; count > 0; --count) {
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if ((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) | (1U<<SPI_FSEL_FLASH)))
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!= (1U<<SPI_FSEL_FLASH)) {
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if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
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!= BIT(SPI_FSEL_FLASH)) {
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/* get status of flash 1 in dual mode or flash 1 only mode */
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retval = target_read_u8(target, io_base + SPI_DR, &data);
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if (retval != ERROR_OK)
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@ -366,13 +367,12 @@ static int read_status_reg(struct flash_bank *bank, uint16_t *status)
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*status |= data;
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}
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if ((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) | (1U<<SPI_FSEL_FLASH)))
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!= (0U<<SPI_FSEL_FLASH)) {
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if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) {
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/* get status of flash 2 in dual mode or flash 2 only mode */
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retval = target_read_u8(target, io_base + SPI_DR, &data);
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if (retval != ERROR_OK)
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goto err;
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*status |= ((uint16_t) data) << 8;
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*status |= ((uint16_t)data) << 8;
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}
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}
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@ -417,7 +417,7 @@ static int qspi_write_enable(struct flash_bank *bank)
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/* Abort any previous operation */
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retval = target_write_u32(target, io_base + SPI_CR,
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READ_REG(SPI_CR) | (1U<<SPI_ABORT));
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READ_REG(SPI_CR) | BIT(SPI_ABORT));
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if (retval != ERROR_OK)
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return retval;
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@ -435,7 +435,7 @@ static int qspi_write_enable(struct flash_bank *bank)
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if (retval != ERROR_OK)
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goto err;
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}
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} else
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} else
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retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_WRITE_ENABLE);
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if (retval != ERROR_OK)
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goto err;
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@ -452,8 +452,8 @@ static int qspi_write_enable(struct flash_bank *bank)
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goto err;
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/* Check write enabled for flash 1 */
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if (((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) | (1U<<SPI_FSEL_FLASH)))
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!= (1U<<SPI_FSEL_FLASH)))
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if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
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!= BIT(SPI_FSEL_FLASH))
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if ((status & (SPIFLASH_WE_BIT | SPIFLASH_BSY_BIT)) != SPIFLASH_WE_BIT) {
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LOG_ERROR("Cannot write enable flash1. Status=0x%02" PRIx8,
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status & 0xFF);
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@ -462,8 +462,7 @@ static int qspi_write_enable(struct flash_bank *bank)
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/* Check write enabled for flash 2 */
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status >>= 8;
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if (((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) | (1U<<SPI_FSEL_FLASH)))
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!= (0U<<SPI_FSEL_FLASH)))
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if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0)
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if ((status & (SPIFLASH_WE_BIT | SPIFLASH_BSY_BIT)) != SPIFLASH_WE_BIT) {
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LOG_ERROR("Cannot write enable flash2. Status=0x%02" PRIx8,
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status & 0xFF);
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@ -546,8 +545,8 @@ COMMAND_HANDLER(stmqspi_handle_mass_erase_command)
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goto err;
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/* Check for command in progress for flash 1 */
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if (((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) | (1U<<SPI_FSEL_FLASH)))
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!= (1U<<SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
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if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
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!= BIT(SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
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((status & SPIFLASH_WE_BIT) != 0)) {
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LOG_ERROR("Mass erase command not accepted by flash1. Status=0x%02" PRIx8,
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status & 0xFF);
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@ -557,8 +556,8 @@ COMMAND_HANDLER(stmqspi_handle_mass_erase_command)
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/* Check for command in progress for flash 2 */
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status >>= 8;
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if (((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) | (1U<<SPI_FSEL_FLASH)))
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!= (0U<<SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
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if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) &&
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((status & SPIFLASH_BSY_BIT) == 0) &&
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((status & SPIFLASH_WE_BIT) != 0)) {
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LOG_ERROR("Mass erase command not accepted by flash2. Status=0x%02" PRIx8,
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status & 0xFF);
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@ -595,7 +594,7 @@ static int log2u(uint32_t word)
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int result;
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for (result = 0; (unsigned int) result < sizeof(uint32_t) * CHAR_BIT; result++)
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if (word == (1UL<<result))
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if (word == BIT(result))
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return result;
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return -1;
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@ -613,7 +612,7 @@ COMMAND_HANDLER(stmqspi_handle_set)
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LOG_DEBUG("%s", __func__);
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dual = (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? 1 : 0;
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dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
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/* chip_erase_cmd, sectorsize and erase_cmd are optional */
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if ((CMD_ARGC < 7) || (CMD_ARGC > 10))
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@ -715,14 +714,14 @@ COMMAND_HANDLER(stmqspi_handle_set)
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bank->size = stmqspi_info->dev.size_in_bytes << dual;
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io_base = stmqspi_info->io_base;
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fsize = (READ_REG(SPI_DCR)>>SPI_FSIZE_POS) & ((1U<<SPI_FSIZE_LEN) - 1);
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fsize = (READ_REG(SPI_DCR) >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("FSIZE = 0x%04x", fsize);
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if (bank->size == (1U<<(fsize + 1)))
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if (bank->size == BIT(fsize + 1))
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LOG_DEBUG("FSIZE in DCR(1) matches actual capacity. Beware of silicon bug in H7, L4+, MP1.");
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else if (bank->size == (1U<<(fsize + 0)))
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else if (bank->size == BIT(fsize + 0))
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LOG_DEBUG("FSIZE in DCR(1) is off by one regarding actual capacity. Fix for silicon bug?");
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else
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LOG_ERROR("FSIZE in DCR(1) doesn't match actual capacity.");
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@ -749,12 +748,12 @@ COMMAND_HANDLER(stmqspi_handle_set)
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LOG_INFO("flash \'%s\' id = unknown\nchip size = %" PRIu32 "kbytes,"
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" bank size = %" PRIu32 "kbytes", stmqspi_info->dev.name,
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stmqspi_info->dev.size_in_bytes / 1024,
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(stmqspi_info->dev.size_in_bytes / 1024)<<dual);
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(stmqspi_info->dev.size_in_bytes / 1024) << dual);
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else
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LOG_INFO("flash \'%s\' id = unknown\nchip size = %" PRIu32 "bytes,"
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" bank size = %" PRIu32 "bytes", stmqspi_info->dev.name,
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stmqspi_info->dev.size_in_bytes,
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stmqspi_info->dev.size_in_bytes<<dual);
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stmqspi_info->dev.size_in_bytes << dual);
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stmqspi_info->probed = true;
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@ -803,7 +802,7 @@ COMMAND_HANDLER(stmqspi_handle_cmd)
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if (num_read == 0) {
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/* nothing to read, then one command byte and for dual flash
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* an *even* number of data bytes to follow */
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if (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) {
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if (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) {
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if ((num_write & 1) == 0) {
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LOG_ERROR("number of data bytes to write must be even in dual mode");
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return ERROR_COMMAND_SYNTAX_ERROR;
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@ -811,7 +810,7 @@ COMMAND_HANDLER(stmqspi_handle_cmd)
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}
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} else {
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/* read mode, one command byte and up to four following address bytes */
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if (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) {
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if (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) {
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if ((num_read & 1) != 0) {
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LOG_ERROR("number of bytes to read must be even in dual mode");
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return ERROR_COMMAND_SYNTAX_ERROR;
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@ -825,7 +824,7 @@ COMMAND_HANDLER(stmqspi_handle_cmd)
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/* Abort any previous operation */
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retval = target_write_u32(target, io_base + SPI_CR,
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READ_REG(SPI_CR) | (1U<<SPI_ABORT));
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READ_REG(SPI_CR) | BIT(SPI_ABORT));
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if (retval != ERROR_OK)
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return retval;
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@ -838,7 +837,7 @@ COMMAND_HANDLER(stmqspi_handle_cmd)
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snprintf(output, sizeof(output), "spi: %02x ", cmd_byte);
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if (num_read == 0) {
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/* write, send cmd byte */
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retval = target_write_u32(target, io_base + SPI_DLR, ((uint32_t) num_write) - 2);
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retval = target_write_u32(target, io_base + SPI_DLR, ((uint32_t)num_write) - 2);
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if (retval != ERROR_OK)
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goto err;
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@ -858,7 +857,7 @@ COMMAND_HANDLER(stmqspi_handle_cmd)
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for (count = 3; count < CMD_ARGC; count++) {
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COMMAND_PARSE_NUMBER(u8, CMD_ARGV[count], data);
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snprintf(temp, sizeof(temp), "%02" PRIx8 " ", data);
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retval = target_write_u8(target, io_base + SPI_DR, data); \
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retval = target_write_u8(target, io_base + SPI_DR, data);
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if (retval != ERROR_OK)
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goto err;
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strncat(output, temp, sizeof(output) - strlen(output) - 1);
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@ -876,19 +875,19 @@ COMMAND_HANDLER(stmqspi_handle_cmd)
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strncat(output, "-> ", sizeof(output) - strlen(output) - 1);
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/* send cmd byte, if ADMODE indicates no address, this already triggers command */
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retval = target_write_u32(target, io_base + SPI_DLR, ((uint32_t) num_read) - 1);
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retval = target_write_u32(target, io_base + SPI_DLR, ((uint32_t)num_read) - 1);
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if (retval != ERROR_OK)
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goto err;
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if (IS_OCTOSPI)
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retval = OCTOSPI_CMD(OCTOSPI_READ_MODE,
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(OCTOSPI_MODE_CCR & OCTOSPI_NO_DDTR & OCTOSPI_NO_ALTB & ~OCTOSPI_ADDR4 &
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((num_write == 1) ? OCTOSPI_NO_ADDR : ~0U)) |
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(((num_write - 2) & 0x3U)<<SPI_ADSIZE_POS), cmd_byte);
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(((num_write - 2) & 0x3U) << SPI_ADSIZE_POS), cmd_byte);
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else
|
||||
retval = target_write_u32(target, io_base + QSPI_CCR,
|
||||
(QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ALTB & ~QSPI_ADDR4 &
|
||||
((num_write == 1) ? QSPI_NO_ADDR : ~0U)) |
|
||||
((QSPI_READ_MODE | (((num_write - 2) & 0x3U)<<SPI_ADSIZE_POS) | cmd_byte)));
|
||||
((QSPI_READ_MODE | (((num_write - 2) & 0x3U) << SPI_ADSIZE_POS) | cmd_byte)));
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
|
||||
|
|
@ -957,8 +956,8 @@ static int qspi_erase_sector(struct flash_bank *bank, unsigned int sector)
|
|||
|
||||
/* Check for command in progress for flash 1 */
|
||||
/* If BSY and WE are already cleared the erase did probably complete already */
|
||||
if (((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) | (1U<<SPI_FSEL_FLASH)))
|
||||
!= (1U<<SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
|
||||
if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
|
||||
!= BIT(SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
|
||||
((status & SPIFLASH_WE_BIT) != 0)) {
|
||||
LOG_ERROR("Sector erase command not accepted by flash1. Status=0x%02" PRIx8,
|
||||
status & 0xFF);
|
||||
|
|
@ -969,8 +968,8 @@ static int qspi_erase_sector(struct flash_bank *bank, unsigned int sector)
|
|||
/* Check for command in progress for flash 2 */
|
||||
/* If BSY and WE are already cleared the erase did probably complete already */
|
||||
status >>= 8;
|
||||
if (((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) | (1U<<SPI_FSEL_FLASH)))
|
||||
!= (0U<<SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
|
||||
if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) &&
|
||||
((status & SPIFLASH_BSY_BIT) == 0) &&
|
||||
((status & SPIFLASH_WE_BIT) != 0)) {
|
||||
LOG_ERROR("Sector erase command not accepted by flash2. Status=0x%02" PRIx8,
|
||||
status & 0xFF);
|
||||
|
|
@ -1084,7 +1083,7 @@ static int stmqspi_blank_check(struct flash_bank *bank)
|
|||
|
||||
/* Abort any previous operation */
|
||||
retval = target_write_u32(target, io_base + SPI_CR,
|
||||
READ_REG(SPI_CR) | (1U<<SPI_ABORT));
|
||||
READ_REG(SPI_CR) | BIT(SPI_ABORT));
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
|
|
@ -1150,7 +1149,7 @@ static int stmqspi_blank_check(struct flash_bank *bank)
|
|||
/* prepare QSPI/OCTOSPI_CCR register values */
|
||||
retval = target_write_buffer(target, algorithm->address
|
||||
+ codesize - sizeof(ccr_buffer),
|
||||
sizeof(ccr_buffer), (uint8_t *) ccr_buffer);
|
||||
sizeof(ccr_buffer), (uint8_t *)ccr_buffer);
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
|
||||
|
|
@ -1177,7 +1176,7 @@ static int stmqspi_blank_check(struct flash_bank *bank)
|
|||
|
||||
retval = target_write_buffer(target, algorithm->address
|
||||
+ codesize + index * sizeof(erase_check_info),
|
||||
sizeof(erase_check_info), (uint8_t *) &erase_check_info);
|
||||
sizeof(erase_check_info), (uint8_t *)&erase_check_info);
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
}
|
||||
|
|
@ -1202,7 +1201,7 @@ static int stmqspi_blank_check(struct flash_bank *bank)
|
|||
for (index = 0; index < count; index++) {
|
||||
retval = target_read_buffer(target, algorithm->address
|
||||
+ codesize + index * sizeof(erase_check_info),
|
||||
sizeof(erase_check_info), (uint8_t *) &erase_check_info);
|
||||
sizeof(erase_check_info), (uint8_t *)&erase_check_info);
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
|
||||
|
|
@ -1276,7 +1275,7 @@ static int qspi_verify(struct flash_bank *bank, uint8_t *buffer,
|
|||
pagesize = SPIFLASH_DEF_PAGESIZE;
|
||||
|
||||
/* adjust size according to dual flash mode */
|
||||
pagesize = (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? pagesize << 1 : pagesize;
|
||||
pagesize = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? pagesize << 1 : pagesize;
|
||||
|
||||
/* This will overlay the last 4 words of stmqspi/stmoctospi_crc32_code in target */
|
||||
/* for read use the saved settings (memory mapped mode) but indirect read mode */
|
||||
|
|
@ -1307,7 +1306,7 @@ static int qspi_verify(struct flash_bank *bank, uint8_t *buffer,
|
|||
/* prepare QSPI/OCTOSPI_CCR register values */
|
||||
retval = target_write_buffer(target, algorithm->address
|
||||
+ codesize - sizeof(ccr_buffer),
|
||||
sizeof(ccr_buffer), (uint8_t *) ccr_buffer);
|
||||
sizeof(ccr_buffer), (uint8_t *)ccr_buffer);
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
|
||||
|
|
@ -1379,7 +1378,7 @@ static int qspi_read_write_block(struct flash_bank *bank, uint8_t *buffer,
|
|||
LOG_DEBUG("%s: offset=0x%08" PRIx32 " len=0x%08" PRIx32,
|
||||
__func__, offset, count);
|
||||
|
||||
dual = (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? 1 : 0;
|
||||
dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
|
||||
|
||||
/* see contrib/loaders/flash/stmqspi/stmqspi_read.S for src */
|
||||
static const uint8_t stmqspi_read_code[] = {
|
||||
|
|
@ -1412,7 +1411,7 @@ static int qspi_read_write_block(struct flash_bank *bank, uint8_t *buffer,
|
|||
h_to_le_32(OCTOSPI_MODE | OCTOSPI_READ_MODE),
|
||||
h_to_le_32(IS_OCTOSPI ? OCTOSPI_CCR_READ_STATUS : QSPI_CCR_READ_STATUS),
|
||||
h_to_le_32((stmqspi_info->saved_tcr & ~OCTOSPI_DCYC_MASK) |
|
||||
(OPI_MODE ? (OPI_DUMMY<<OCTOSPI_DCYC_POS) : 0)),
|
||||
(OPI_MODE ? (OPI_DUMMY << OCTOSPI_DCYC_POS) : 0)),
|
||||
h_to_le_32(OPI_CMD(SPIFLASH_READ_STATUS)),
|
||||
},
|
||||
{
|
||||
|
|
@ -1490,7 +1489,7 @@ static int qspi_read_write_block(struct flash_bank *bank, uint8_t *buffer,
|
|||
/* prepare QSPI/OCTOSPI_CCR register values */
|
||||
retval = target_write_buffer(target, algorithm->address
|
||||
+ codesize - sizeof(ccr_buffer),
|
||||
sizeof(ccr_buffer), (uint8_t *) ccr_buffer);
|
||||
sizeof(ccr_buffer), (uint8_t *)ccr_buffer);
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
|
||||
|
|
@ -1592,7 +1591,7 @@ static int stmqspi_read(struct flash_bank *bank, uint8_t *buffer,
|
|||
|
||||
/* Abort any previous operation */
|
||||
retval = target_write_u32(target, io_base + SPI_CR,
|
||||
READ_REG(SPI_CR) | (1U<<SPI_ABORT));
|
||||
READ_REG(SPI_CR) | BIT(SPI_ABORT));
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
|
|
@ -1617,8 +1616,8 @@ static int stmqspi_write(struct flash_bank *bank, const uint8_t *buffer,
|
|||
LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
|
||||
__func__, offset, count);
|
||||
|
||||
dual = (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? 1 : 0;
|
||||
octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & (1U<<OCTOSPI_DDTR));
|
||||
dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
|
||||
octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & BIT(OCTOSPI_DDTR));
|
||||
|
||||
if (target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("Target not halted");
|
||||
|
|
@ -1639,9 +1638,9 @@ static int stmqspi_write(struct flash_bank *bank, const uint8_t *buffer,
|
|||
for (sector = 0; sector < bank->num_sectors; sector++) {
|
||||
/* Start offset in or before this sector? */
|
||||
/* End offset in or behind this sector? */
|
||||
if ((offset < (bank->sectors[sector].offset + bank->sectors[sector].size))
|
||||
&& ((offset + count - 1) >= bank->sectors[sector].offset)
|
||||
&& bank->sectors[sector].is_protected) {
|
||||
if ((offset < (bank->sectors[sector].offset + bank->sectors[sector].size)) &&
|
||||
((offset + count - 1) >= bank->sectors[sector].offset) &&
|
||||
bank->sectors[sector].is_protected) {
|
||||
LOG_ERROR("Flash sector %u protected", sector);
|
||||
return ERROR_FLASH_PROTECTED;
|
||||
}
|
||||
|
|
@ -1655,7 +1654,7 @@ static int stmqspi_write(struct flash_bank *bank, const uint8_t *buffer,
|
|||
|
||||
/* Abort any previous operation */
|
||||
retval = target_write_u32(target, io_base + SPI_CR,
|
||||
READ_REG(SPI_CR) | (1U<<SPI_ABORT));
|
||||
READ_REG(SPI_CR) | BIT(SPI_ABORT));
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
|
|
@ -1664,7 +1663,7 @@ static int stmqspi_write(struct flash_bank *bank, const uint8_t *buffer,
|
|||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
return qspi_read_write_block(bank, (uint8_t *) buffer, offset, count, true);
|
||||
return qspi_read_write_block(bank, (uint8_t *)buffer, offset, count, true);
|
||||
}
|
||||
|
||||
static int stmqspi_verify(struct flash_bank *bank, const uint8_t *buffer,
|
||||
|
|
@ -1680,8 +1679,8 @@ static int stmqspi_verify(struct flash_bank *bank, const uint8_t *buffer,
|
|||
LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
|
||||
__func__, offset, count);
|
||||
|
||||
dual = (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? 1 : 0;
|
||||
octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & (1U<<OCTOSPI_DDTR));
|
||||
dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
|
||||
octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & BIT(OCTOSPI_DDTR));
|
||||
|
||||
if (target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("Target not halted");
|
||||
|
|
@ -1706,7 +1705,7 @@ static int stmqspi_verify(struct flash_bank *bank, const uint8_t *buffer,
|
|||
|
||||
/* Abort any previous operation */
|
||||
retval = target_write_u32(target, io_base + SPI_CR,
|
||||
READ_REG(SPI_CR) | (1U<<SPI_ABORT));
|
||||
READ_REG(SPI_CR) | BIT(SPI_ABORT));
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
|
|
@ -1715,7 +1714,7 @@ static int stmqspi_verify(struct flash_bank *bank, const uint8_t *buffer,
|
|||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
return qspi_verify(bank, (uint8_t *) buffer, offset, count);
|
||||
return qspi_verify(bank, (uint8_t *)buffer, offset, count);
|
||||
}
|
||||
|
||||
/* Find appropriate dummy setting, in particular octo mode */
|
||||
|
|
@ -1726,18 +1725,18 @@ static int find_sfdp_dummy(struct flash_bank *bank, int len)
|
|||
uint32_t io_base = stmqspi_info->io_base;
|
||||
uint8_t data;
|
||||
unsigned int dual, count;
|
||||
bool flash1 = !(stmqspi_info->saved_cr & (1U<<SPI_FSEL_FLASH));
|
||||
bool flash1 = !(stmqspi_info->saved_cr & BIT(SPI_FSEL_FLASH));
|
||||
int retval;
|
||||
const unsigned int max_bytes = 64;
|
||||
|
||||
dual = (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? 1 : 0;
|
||||
dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
|
||||
|
||||
LOG_DEBUG("%s: len=%d, dual=%u, flash1=%d",
|
||||
__func__, len, dual, flash1);
|
||||
|
||||
/* Abort any previous operation */
|
||||
retval = target_write_u32(target, io_base + SPI_CR,
|
||||
stmqspi_info->saved_cr | (1U<<SPI_ABORT));
|
||||
stmqspi_info->saved_cr | BIT(SPI_ABORT));
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
|
||||
|
|
@ -1806,7 +1805,7 @@ static int find_sfdp_dummy(struct flash_bank *bank, int len)
|
|||
err:
|
||||
/* Abort operation */
|
||||
retval = target_write_u32(target, io_base + SPI_CR,
|
||||
READ_REG(SPI_CR) | (1U<<SPI_ABORT));
|
||||
READ_REG(SPI_CR) | BIT(SPI_ABORT));
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
|
@ -1818,11 +1817,11 @@ static int read_sfdp_block(struct flash_bank *bank, uint32_t addr,
|
|||
struct target *target = bank->target;
|
||||
struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
|
||||
uint32_t io_base = stmqspi_info->io_base;
|
||||
bool flash1 = !(stmqspi_info->saved_cr & (1U<<SPI_FSEL_FLASH));
|
||||
bool flash1 = !(stmqspi_info->saved_cr & BIT(SPI_FSEL_FLASH));
|
||||
unsigned int dual, count, len, *dummy;
|
||||
int retval;
|
||||
|
||||
dual = (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? 1 : 0;
|
||||
dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
|
||||
|
||||
if (IS_OCTOSPI && (((stmqspi_info->saved_ccr >> SPI_DMODE_POS) & 0x7) > 3)) {
|
||||
/* in OCTO mode 4-byte address and (yet) unknown number of dummy clocks */
|
||||
|
|
@ -1840,7 +1839,7 @@ static int read_sfdp_block(struct flash_bank *bank, uint32_t addr,
|
|||
len = 3;
|
||||
|
||||
/* use sfdp_dummy1/2 according to currently selected flash */
|
||||
dummy = (stmqspi_info->saved_cr & (1U<<SPI_FSEL_FLASH)) ?
|
||||
dummy = (stmqspi_info->saved_cr & BIT(SPI_FSEL_FLASH)) ?
|
||||
&stmqspi_info->sfdp_dummy2 : &stmqspi_info->sfdp_dummy1;
|
||||
|
||||
/* according to SFDP standard, there should always be 8 dummy *CLOCKS*
|
||||
|
|
@ -1859,7 +1858,7 @@ static int read_sfdp_block(struct flash_bank *bank, uint32_t addr,
|
|||
|
||||
/* Abort any previous operation */
|
||||
retval = target_write_u32(target, io_base + SPI_CR,
|
||||
stmqspi_info->saved_cr | (1U<<SPI_ABORT));
|
||||
stmqspi_info->saved_cr | BIT(SPI_ABORT));
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
|
||||
|
|
@ -1894,7 +1893,7 @@ static int read_sfdp_block(struct flash_bank *bank, uint32_t addr,
|
|||
|
||||
/* dummy clocks */
|
||||
for (count = *dummy << dual; count > 0; --count) {
|
||||
retval = target_read_u8(target, io_base + SPI_DR, (uint8_t *) buffer);
|
||||
retval = target_read_u8(target, io_base + SPI_DR, (uint8_t *)buffer);
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
}
|
||||
|
|
@ -1929,7 +1928,7 @@ static int read_sfdp_block(struct flash_bank *bank, uint32_t addr,
|
|||
LOG_DEBUG("raw SFDP data 0x%08" PRIx32, *buffer);
|
||||
|
||||
/* endian correction, sfdp data is always le uint32_t based */
|
||||
*buffer = le_to_h_u32((uint8_t *) buffer);
|
||||
*buffer = le_to_h_u32((uint8_t *)buffer);
|
||||
buffer++;
|
||||
}
|
||||
|
||||
|
|
@ -1961,7 +1960,7 @@ static int read_flash_id(struct flash_bank *bank, uint32_t *id1, uint32_t *id2)
|
|||
for (type = (IS_OCTOSPI && OPI_MODE) ? 1 : 0; type < 2 ; type++) {
|
||||
/* Abort any previous operation */
|
||||
retval = target_write_u32(target, io_base + SPI_CR,
|
||||
READ_REG(SPI_CR) | (1U<<SPI_ABORT));
|
||||
READ_REG(SPI_CR) | BIT(SPI_ABORT));
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
|
||||
|
|
@ -1978,7 +1977,7 @@ static int read_flash_id(struct flash_bank *bank, uint32_t *id1, uint32_t *id2)
|
|||
/* Read at most 16 bytes per chip */
|
||||
count = 16;
|
||||
retval = target_write_u32(target, io_base + SPI_DLR,
|
||||
(stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH) ? count * 2 : count) - 1);
|
||||
(stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH) ? count * 2 : count) - 1);
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
|
||||
|
|
@ -2014,29 +2013,29 @@ static int read_flash_id(struct flash_bank *bank, uint32_t *id1, uint32_t *id2)
|
|||
}
|
||||
|
||||
/* for debugging only */
|
||||
(void) READ_REG(SPI_SR);
|
||||
(void)READ_REG(SPI_SR);
|
||||
|
||||
/* Read ID from Data Register */
|
||||
for (len1 = 0, len2 = 0; count > 0; --count) {
|
||||
if ((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) |
|
||||
(1U<<SPI_FSEL_FLASH))) != (1U<<SPI_FSEL_FLASH)) {
|
||||
if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
|
||||
BIT(SPI_FSEL_FLASH))) != BIT(SPI_FSEL_FLASH)) {
|
||||
retval = target_read_u8(target, io_base + SPI_DR, &byte);
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
/* collect 3 bytes without continuation codes */
|
||||
if ((byte != 0x7F) && (len1 < 3)) {
|
||||
*id1 = (*id1 >> 8) | ((uint32_t) byte) << 16;
|
||||
*id1 = (*id1 >> 8) | ((uint32_t)byte) << 16;
|
||||
len1++;
|
||||
}
|
||||
}
|
||||
if ((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) |
|
||||
(1U<<SPI_FSEL_FLASH))) != 0) {
|
||||
if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
|
||||
BIT(SPI_FSEL_FLASH))) != 0) {
|
||||
retval = target_read_u8(target, io_base + SPI_DR, &byte);
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
/* collect 3 bytes without continuation codes */
|
||||
if ((byte != 0x7F) && (len2 < 3)) {
|
||||
*id2 = (*id2 >> 8) | ((uint32_t) byte) << 16;
|
||||
*id2 = (*id2 >> 8) | ((uint32_t)byte) << 16;
|
||||
len2++;
|
||||
}
|
||||
}
|
||||
|
|
@ -2047,8 +2046,8 @@ static int read_flash_id(struct flash_bank *bank, uint32_t *id1, uint32_t *id2)
|
|||
break;
|
||||
}
|
||||
|
||||
if ((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) |
|
||||
(1U<<SPI_FSEL_FLASH))) != (1U<<SPI_FSEL_FLASH)) {
|
||||
if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
|
||||
BIT(SPI_FSEL_FLASH))) != BIT(SPI_FSEL_FLASH)) {
|
||||
if ((*id1 == 0x000000) || (*id1 == 0xFFFFFF)) {
|
||||
/* no id retrieved, so id must be set manually */
|
||||
LOG_INFO("No id from flash1");
|
||||
|
|
@ -2056,8 +2055,7 @@ static int read_flash_id(struct flash_bank *bank, uint32_t *id1, uint32_t *id2)
|
|||
}
|
||||
}
|
||||
|
||||
if ((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) |
|
||||
(1U<<SPI_FSEL_FLASH))) != (0U<<SPI_FSEL_FLASH)) {
|
||||
if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) {
|
||||
if ((*id2 == 0x000000) || (*id2 == 0xFFFFFF)) {
|
||||
/* no id retrieved, so id must be set manually */
|
||||
LOG_INFO("No id from flash2");
|
||||
|
|
@ -2085,8 +2083,7 @@ static int stmqspi_probe(struct flash_bank *bank)
|
|||
if (stmqspi_info->probed) {
|
||||
bank->size = 0;
|
||||
bank->num_sectors = 0;
|
||||
if (bank->sectors)
|
||||
free(bank->sectors);
|
||||
free(bank->sectors);
|
||||
bank->sectors = NULL;
|
||||
memset(&stmqspi_info->dev, 0, sizeof(stmqspi_info->dev));
|
||||
stmqspi_info->sfdp_dummy1 = 0;
|
||||
|
|
@ -2096,7 +2093,7 @@ static int stmqspi_probe(struct flash_bank *bank)
|
|||
|
||||
/* Abort any previous operation */
|
||||
retval = target_write_u32(target, io_base + SPI_CR,
|
||||
READ_REG(SPI_CR) | (1U<<SPI_ABORT));
|
||||
READ_REG(SPI_CR) | BIT(SPI_ABORT));
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
|
|
@ -2133,7 +2130,7 @@ static int stmqspi_probe(struct flash_bank *bank)
|
|||
if (IS_OCTOSPI) {
|
||||
uint32_t mtyp;
|
||||
|
||||
mtyp = ((READ_REG(OCTOSPI_DCR1) & OCTOSPI_MTYP_MASK))>>OCTOSPI_MTYP_POS;
|
||||
mtyp = ((READ_REG(OCTOSPI_DCR1) & OCTOSPI_MTYP_MASK)) >> OCTOSPI_MTYP_POS;
|
||||
if (retval == ERROR_OK)
|
||||
stmqspi_info->saved_tcr = READ_REG(OCTOSPI_TCR);
|
||||
if (retval == ERROR_OK)
|
||||
|
|
@ -2167,8 +2164,8 @@ static int stmqspi_probe(struct flash_bank *bank)
|
|||
}
|
||||
}
|
||||
|
||||
dual = (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? 1 : 0;
|
||||
octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & (1U<<OCTOSPI_DDTR));
|
||||
dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
|
||||
octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & BIT(OCTOSPI_DDTR));
|
||||
if (dual || octal_dtr)
|
||||
bank->write_start_alignment = bank->write_end_alignment = 2;
|
||||
else
|
||||
|
|
@ -2207,7 +2204,7 @@ static int stmqspi_probe(struct flash_bank *bank)
|
|||
uint32_t saved_cr = stmqspi_info->saved_cr;
|
||||
|
||||
/* select flash1 */
|
||||
stmqspi_info->saved_cr = stmqspi_info->saved_cr & ~(1U<<SPI_FSEL_FLASH);
|
||||
stmqspi_info->saved_cr = stmqspi_info->saved_cr & ~BIT(SPI_FSEL_FLASH);
|
||||
retval = spi_sfdp(bank, &temp, &read_sfdp_block);
|
||||
|
||||
/* restore saved_cr */
|
||||
|
|
@ -2265,7 +2262,7 @@ static int stmqspi_probe(struct flash_bank *bank)
|
|||
uint32_t saved_cr = stmqspi_info->saved_cr;
|
||||
|
||||
/* select flash2 */
|
||||
stmqspi_info->saved_cr = stmqspi_info->saved_cr | (1U<<SPI_FSEL_FLASH);
|
||||
stmqspi_info->saved_cr = stmqspi_info->saved_cr | BIT(SPI_FSEL_FLASH);
|
||||
retval = spi_sfdp(bank, &temp, &read_sfdp_block);
|
||||
|
||||
/* restore saved_cr */
|
||||
|
|
@ -2304,14 +2301,14 @@ static int stmqspi_probe(struct flash_bank *bank)
|
|||
/* Set correct size value */
|
||||
bank->size = stmqspi_info->dev.size_in_bytes << dual;
|
||||
|
||||
fsize = ((READ_REG(SPI_DCR)>>SPI_FSIZE_POS) & ((1U<<SPI_FSIZE_LEN) - 1));
|
||||
fsize = ((READ_REG(SPI_DCR) >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1));
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
|
||||
LOG_DEBUG("FSIZE = 0x%04x", fsize);
|
||||
if (bank->size == (1U<<(fsize + 1)))
|
||||
if (bank->size == BIT((fsize + 1)))
|
||||
LOG_DEBUG("FSIZE in DCR(1) matches actual capacity. Beware of silicon bug in H7, L4+, MP1.");
|
||||
else if (bank->size == (1U<<(fsize + 0)))
|
||||
else if (bank->size == BIT((fsize + 0)))
|
||||
LOG_DEBUG("FSIZE in DCR(1) is off by one regarding actual capacity. Fix for silicon bug?");
|
||||
else
|
||||
LOG_ERROR("FSIZE in DCR(1) doesn't match actual capacity.");
|
||||
|
|
@ -2380,10 +2377,10 @@ static int get_stmqspi_info(struct flash_bank *bank, char *buf, int buf_size)
|
|||
", read = 0x%02" PRIx8 ", qread = 0x%02" PRIx8
|
||||
", pprog = 0x%02" PRIx8 ", mass_erase = 0x%02" PRIx8
|
||||
", sector size = %" PRIu32 "%sbytes, sector_erase = 0x%02" PRIx8 ")",
|
||||
((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) |
|
||||
(1U<<SPI_FSEL_FLASH))) != (1U<<SPI_FSEL_FLASH)) ? "1" : "",
|
||||
((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) |
|
||||
(1U<<SPI_FSEL_FLASH))) != (0U<<SPI_FSEL_FLASH)) ? "2" : "",
|
||||
((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
|
||||
BIT(SPI_FSEL_FLASH))) != BIT(SPI_FSEL_FLASH)) ? "1" : "",
|
||||
((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
|
||||
BIT(SPI_FSEL_FLASH))) != 0) ? "2" : "",
|
||||
stmqspi_info->dev.name, stmqspi_info->dev.device_id,
|
||||
bank->size / 4096 ? bank->size / 1024 : bank->size,
|
||||
bank->size / 4096 ? "k" : "", stmqspi_info->dev.pagesize,
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@
|
|||
#define SPI_DMODE_POS 24 /* bit position of DMODE */
|
||||
#define QSPI_DCYC_POS 18 /* bit position of DCYC */
|
||||
#define QSPI_DCYC_LEN 5 /* width of DCYC field */
|
||||
#define QSPI_DCYC_MASK (((1U<<QSPI_DCYC_LEN) - 1)<<QSPI_DCYC_POS)
|
||||
#define QSPI_DCYC_MASK ((BIT(QSPI_DCYC_LEN) - 1) << QSPI_DCYC_POS)
|
||||
#define SPI_ADSIZE_POS 12 /* bit position of ADSIZE */
|
||||
|
||||
#define QSPI_WRITE_MODE 0x00000000U /* indirect write mode */
|
||||
|
|
@ -62,8 +62,8 @@
|
|||
#define QSPI_NO_DATA (~0x03000000U) /* no data */
|
||||
#define QSPI_NO_ALTB (~QSPI_ALTB_MODE) /* no alternate */
|
||||
#define QSPI_NO_ADDR (~0x00000C00U) /* no address */
|
||||
#define QSPI_ADDR3 (0x2U<<SPI_ADSIZE_POS) /* 3 byte address */
|
||||
#define QSPI_ADDR4 (0x3U<<SPI_ADSIZE_POS) /* 4 byte address */
|
||||
#define QSPI_ADDR3 (0x2U << SPI_ADSIZE_POS) /* 3 byte address */
|
||||
#define QSPI_ADDR4 (0x3U << SPI_ADSIZE_POS) /* 4 byte address */
|
||||
|
||||
/* OCTOSPI register offsets */
|
||||
#define OCTOSPI_CR (0x000) /* Control register */
|
||||
|
|
@ -92,7 +92,7 @@
|
|||
/* additional fields in OCTOSPI_DCR1 */
|
||||
#define OCTOSPI_MTYP_POS (24) /* bit position of MTYP */
|
||||
#define OCTOSPI_MTYP_LEN (3) /* width of MTYP field */
|
||||
#define OCTOSPI_MTYP_MASK (((1U<<OCTOSPI_MTYP_LEN) - 1)<<OCTOSPI_MTYP_POS)
|
||||
#define OCTOSPI_MTYP_MASK ((BIT(OCTOSPI_MTYP_LEN) - 1) << OCTOSPI_MTYP_POS)
|
||||
|
||||
/* fields in OCTOSPI_CCR */
|
||||
#define OCTOSPI_ALTB_MODE 0x001F0000U /* alternate byte mode */
|
||||
|
|
@ -100,17 +100,17 @@
|
|||
#define OCTOSPI_NO_DATA (~0x0F000000U) /* no data */
|
||||
#define OCTOSPI_NO_ALTB (~OCTOSPI_ALTB_MODE) /* no alternate */
|
||||
#define OCTOSPI_NO_ADDR (~0x00000F00U) /* no address */
|
||||
#define OCTOSPI_ADDR3 (0x2U<<SPI_ADSIZE_POS) /* 3 byte address */
|
||||
#define OCTOSPI_ADDR4 (0x3U<<SPI_ADSIZE_POS) /* 4 byte address */
|
||||
#define OCTOSPI_ADDR3 (0x2U << SPI_ADSIZE_POS) /* 3 byte address */
|
||||
#define OCTOSPI_ADDR4 (0x3U << SPI_ADSIZE_POS) /* 4 byte address */
|
||||
#define OCTOSPI_DQSEN 29 /* DQS enable */
|
||||
#define OCTOSPI_DDTR 27 /* DTR for data */
|
||||
#define OCTOSPI_NO_DDTR (~(1U<<OCTOSPI_DDTR)) /* no DTR for data, but maybe still DQS */
|
||||
#define OCTOSPI_NO_DDTR (~BIT(OCTOSPI_DDTR)) /* no DTR for data, but maybe still DQS */
|
||||
#define OCTOSPI_ISIZE_MASK (0x30) /* ISIZE field */
|
||||
|
||||
/* fields in OCTOSPI_TCR */
|
||||
#define OCTOSPI_DCYC_POS 0 /* bit position of DCYC */
|
||||
#define OCTOSPI_DCYC_LEN 5 /* width of DCYC field */
|
||||
#define OCTOSPI_DCYC_MASK (((1U<<OCTOSPI_DCYC_LEN) - 1)<<OCTOSPI_DCYC_POS)
|
||||
#define OCTOSPI_DCYC_MASK ((BIT(OCTOSPI_DCYC_LEN) - 1) << OCTOSPI_DCYC_POS)
|
||||
|
||||
#define IS_OCTOSPI (stmqspi_info->octo)
|
||||
#define SPI_CR (IS_OCTOSPI ? OCTOSPI_CR : QSPI_CR)
|
||||
|
|
|
|||
|
|
@ -1154,7 +1154,7 @@ int target_run_read_async_algorithm(struct target *target,
|
|||
}
|
||||
|
||||
LOG_DEBUG("offs 0x%zx count 0x%" PRIx32 " wp 0x%" PRIx32 " rp 0x%" PRIx32,
|
||||
(size_t) (buffer - buffer_orig), count, wp, rp);
|
||||
(size_t)(buffer - buffer_orig), count, wp, rp);
|
||||
|
||||
if (wp == 0) {
|
||||
LOG_ERROR("flash read algorithm aborted by target");
|
||||
|
|
|
|||
Loading…
Reference in New Issue