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target: use proper format with uint32_t 

Modify the format strings to properly handle uint32_t data types.

While there, fix prototype mismatch between header and C file of
the function armv7a_l1_d_cache_inval_virt().

Change-Id: I434bd241fa5c38e0c15d22cda2295097050067f5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5818
Tested-by: jenkins
This commit is contained in:
Antonio Borneo 2020-08-18 18:56:27 +02:00
parent e66593f824
commit 99add6227f
30 changed files with 121 additions and 121 deletions
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6
src/target/aarch64.c
View File

@ -105,7 +105,7 @@ static int aarch64_restore_system_control_reg(struct target *target)
break;
default:
LOG_ERROR("cannot read system control register in this mode: (%s : 0x%" PRIx32 ")",
LOG_ERROR("cannot read system control register in this mode: (%s : 0x%x)",
armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode);
return ERROR_FAIL;
}
@ -180,7 +180,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
break;
default:
LOG_DEBUG("unknown cpu state 0x%" PRIx32, armv8->arm.core_mode);
LOG_DEBUG("unknown cpu state 0x%x", armv8->arm.core_mode);
break;
}
@ -1042,7 +1042,7 @@ static int aarch64_post_debug_entry(struct target *target)
break;
default:
LOG_ERROR("cannot read system control register in this mode: (%s : 0x%" PRIx32 ")",
LOG_ERROR("cannot read system control register in this mode: (%s : 0x%x)",
armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode);
return ERROR_FAIL;
}

12
src/target/arc.c
View File

@ -197,7 +197,7 @@ int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
arc->num_regs += 1;
LOG_DEBUG(
"added register {name=%s, num=0x%x, type=%s%s%s%s}",
"added register {name=%s, num=0x%" PRIx32 ", type=%s%s%s%s}",
arc_reg->name, arc_reg->arch_num, arc_reg->data_type->id,
arc_reg->is_core ? ", core" : "", arc_reg->is_bcr ? ", bcr" : "",
arc_reg->is_general ? ", general" : ""
@ -889,7 +889,7 @@ static int arc_save_context(struct target *target)
core_cnt += 1;
reg->valid = true;
reg->dirty = false;
LOG_DEBUG("Get core register regnum=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
LOG_DEBUG("Get core register regnum=%u, name=%s, value=0x%08" PRIx32,
i, arc_reg->name, core_values[core_cnt]);
}
}
@ -904,7 +904,7 @@ static int arc_save_context(struct target *target)
aux_cnt += 1;
reg->valid = true;
reg->dirty = false;
LOG_DEBUG("Get aux register regnum=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
LOG_DEBUG("Get aux register regnum=%u, name=%s, value=0x%08" PRIx32,
i, arc_reg->name, aux_values[aux_cnt]);
}
}
@ -1464,7 +1464,7 @@ static int arc_configure_actionpoint(struct target *target, uint32_t ap_num,
if (control_tt != AP_AC_TT_DISABLE) {
if (arc->actionpoints_num_avail < 1) {
LOG_ERROR("No free actionpoints, maximim amount is %" PRIu32,
LOG_ERROR("No free actionpoints, maximim amount is %u",
arc->actionpoints_num);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@ -1551,7 +1551,7 @@ static int arc_set_breakpoint(struct target *target,
}
if (bp_num >= arc->actionpoints_num) {
LOG_ERROR("No free actionpoints, maximum amount is %" PRIu32,
LOG_ERROR("No free actionpoints, maximum amount is %u",
arc->actionpoints_num);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@ -1607,7 +1607,7 @@ static int arc_unset_breakpoint(struct target *target,
} else {
LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
" has been overwritten outside of debugger."
"Expected: @0x%" PRIx32 ", got: @0x%" PRIx32,
"Expected: @0x%x, got: @0x%" PRIx32,
breakpoint->address, ARC_SDBBP_32, current_instr);
}
} else if (breakpoint->length == 2) {

2
src/target/arc.h
View File

@ -55,7 +55,7 @@
#define REG_TYPE_MAX_NAME_LENGTH 20
/* ARC 32bits opcodes */
#define ARC_SDBBP_32 0x256F003F /* BRK */
#define ARC_SDBBP_32 0x256F003FU /* BRK */
/* ARC 16bits opcodes */
#define ARC_SDBBP_16 0x7FFF /* BRK_S */

10
src/target/arm7_9_common.c
View File

@ -102,7 +102,7 @@ static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *br
} else
LOG_ERROR("BUG: no hardware comparator available");
LOG_DEBUG("BPID: %" PRId32 " (0x%08" TARGET_PRIxADDR ") using hw wp: %d",
LOG_DEBUG("BPID: %" PRIu32 " (0x%08" TARGET_PRIxADDR ") using hw wp: %d",
breakpoint->unique_id,
breakpoint->address,
breakpoint->set);
@ -188,7 +188,7 @@ static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *break
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int retval = ERROR_OK;
LOG_DEBUG("BPID: %" PRId32 ", Address: 0x%08" TARGET_PRIxADDR ", Type: %d",
LOG_DEBUG("BPID: %" PRIu32 ", Address: 0x%08" TARGET_PRIxADDR ", Type: %d",
breakpoint->unique_id,
breakpoint->address,
breakpoint->type);
@ -300,7 +300,7 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
LOG_DEBUG("BPID: %" PRId32 ", Address: 0x%08" TARGET_PRIxADDR,
LOG_DEBUG("BPID: %" PRIu32 ", Address: 0x%08" TARGET_PRIxADDR,
breakpoint->unique_id,
breakpoint->address);
@ -310,7 +310,7 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre
}
if (breakpoint->type == BKPT_HARD) {
LOG_DEBUG("BPID: %" PRId32 " Releasing hw wp: %d",
LOG_DEBUG("BPID: %" PRIu32 " Releasing hw wp: %d",
breakpoint->unique_id,
breakpoint->set);
if (breakpoint->set == 1) {
@ -1725,7 +1725,7 @@ int arm7_9_resume(struct target *target,
breakpoint = breakpoint_find(target,
buf_get_u32(arm->pc->value, 0, 32));
if (breakpoint != NULL) {
LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR " (id: %" PRId32,
LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR " (id: %" PRIu32,
breakpoint->address,
breakpoint->unique_id);
retval = arm7_9_unset_breakpoint(target, breakpoint);

4
src/target/arm946e.c
View File

@ -596,7 +596,7 @@ COMMAND_HANDLER(arm946e_handle_cp15)
uint32_t value;
retval = arm946e_read_cp15(target, address, &value);
if (retval != ERROR_OK) {
command_print(CMD, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
command_print(CMD, "%s cp15 reg %" PRIu32 " access failed", target_name(target), address);
return retval;
}
retval = jtag_execute_queue();
@ -611,7 +611,7 @@ COMMAND_HANDLER(arm946e_handle_cp15)
retval = arm946e_write_cp15(target, address, value);
if (retval != ERROR_OK) {
command_print(CMD, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
command_print(CMD, "%s cp15 reg %" PRIu32 " access failed", target_name(target), address);
return retval;
}
if (address == CP15_CTL)

8
src/target/arm966e.c
View File

@ -199,7 +199,7 @@ COMMAND_HANDLER(arm966e_handle_cp15_command)
retval = arm966e_read_cp15(target, address, &value);
if (retval != ERROR_OK) {
command_print(CMD,
"couldn't access reg %" PRIi32,
"couldn't access reg %" PRIu32,
address);
return ERROR_OK;
}
@ -207,7 +207,7 @@ COMMAND_HANDLER(arm966e_handle_cp15_command)
if (retval != ERROR_OK)
return retval;
command_print(CMD, "%" PRIi32 ": %8.8" PRIx32,
command_print(CMD, "%" PRIu32 ": %8.8" PRIx32,
address, value);
} else if (CMD_ARGC == 2) {
uint32_t value;
@ -215,11 +215,11 @@ COMMAND_HANDLER(arm966e_handle_cp15_command)
retval = arm966e_write_cp15(target, address, value);
if (retval != ERROR_OK) {
command_print(CMD,
"couldn't access reg %" PRIi32,
"couldn't access reg %" PRIu32,
address);
return ERROR_OK;
}
command_print(CMD, "%" PRIi32 ": %8.8" PRIx32,
command_print(CMD, "%" PRIu32 ": %8.8" PRIx32,
address, value);
}
}

6
src/target/arm_adi_v5.c
View File

@ -1682,7 +1682,7 @@ COMMAND_HANDLER(dap_memaccess_command)
}
dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
command_print(CMD, "memory bus access delay set to %" PRIi32 " tck",
command_print(CMD, "memory bus access delay set to %" PRIu32 " tck",
dap->ap[dap->apsel].memaccess_tck);
return ERROR_OK;
@ -1695,7 +1695,7 @@ COMMAND_HANDLER(dap_apsel_command)
switch (CMD_ARGC) {
case 0:
command_print(CMD, "%" PRIi32, dap->apsel);
command_print(CMD, "%" PRIu32, dap->apsel);
return ERROR_OK;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
@ -1721,7 +1721,7 @@ COMMAND_HANDLER(dap_apcsw_command)
switch (CMD_ARGC) {
case 0:
command_print(CMD, "ap %" PRIi32 " selected, csw 0x%8.8" PRIx32,
command_print(CMD, "ap %" PRIu32 " selected, csw 0x%8.8" PRIx32,
dap->apsel, apcsw);
return ERROR_OK;
case 1:

28
src/target/armv7a.c
View File

@ -257,10 +257,10 @@ int armv7a_handle_cache_info_command(struct command_invocation *cmd,
if (arch->ctype & 1) {
command_print(cmd,
"L%d I-Cache: linelen %" PRIi32
", associativity %" PRIi32
", nsets %" PRIi32
", cachesize %" PRId32 " KBytes",
"L%d I-Cache: linelen %" PRIu32
", associativity %" PRIu32
", nsets %" PRIu32
", cachesize %" PRIu32 " KBytes",
cl+1,
arch->i_size.linelen,
arch->i_size.associativity,
@ -270,10 +270,10 @@ int armv7a_handle_cache_info_command(struct command_invocation *cmd,
if (arch->ctype >= 2) {
command_print(cmd,
"L%d D-Cache: linelen %" PRIi32
", associativity %" PRIi32
", nsets %" PRIi32
", cachesize %" PRId32 " KBytes",
"L%d D-Cache: linelen %" PRIu32
", associativity %" PRIu32
", nsets %" PRIu32
", cachesize %" PRIu32 " KBytes",
cl+1,
arch->d_u_size.linelen,
arch->d_u_size.associativity,
@ -283,7 +283,7 @@ int armv7a_handle_cache_info_command(struct command_invocation *cmd,
}
if (l2x_cache != NULL)
command_print(cmd, "Outer unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
command_print(cmd, "Outer unified cache Base Address 0x%" PRIx32 ", %" PRIu32 " ways",
l2x_cache->base, l2x_cache->way);
return ERROR_OK;
@ -399,7 +399,7 @@ int armv7a_identify_cache(struct target *target)
cache->iminline = 4UL << (ctr & 0xf);
cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRId32 " ctr.dminline %" PRId32,
LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
ctr, cache->iminline, cache->dminline);
/* retrieve CLIDR
@ -439,13 +439,13 @@ int armv7a_identify_cache(struct target *target)
goto done;
cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
LOG_DEBUG("data/unified cache index %d << %d, way %d << %d",
LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
cache->arch[cl].d_u_size.index,
cache->arch[cl].d_u_size.index_shift,
cache->arch[cl].d_u_size.way,
cache->arch[cl].d_u_size.way_shift);
LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
cache->arch[cl].d_u_size.linelen,
cache->arch[cl].d_u_size.cachesize,
cache->arch[cl].d_u_size.associativity);
@ -459,13 +459,13 @@ int armv7a_identify_cache(struct target *target)
goto done;
cache->arch[cl].i_size = decode_cache_reg(cache_reg);
LOG_DEBUG("instruction cache index %d << %d, way %d << %d",
LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
cache->arch[cl].i_size.index,
cache->arch[cl].i_size.index_shift,
cache->arch[cl].i_size.way,
cache->arch[cl].i_size.way_shift);
LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
cache->arch[cl].i_size.linelen,
cache->arch[cl].i_size.cachesize,
cache->arch[cl].i_size.associativity);

2
src/target/armv7a_cache.h
View File

@ -25,7 +25,7 @@
int armv7a_l1_d_cache_clean_virt(struct target *target, uint32_t virt,
unsigned int size);
int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt,
unsigned int size);
uint32_t size);
int armv7a_l1_d_cache_flush_virt(struct target *target, uint32_t virt,
unsigned int size);
int armv7a_l1_i_cache_inval_all(struct target *target);

2
src/target/armv7a_cache_l2x.c
View File

@ -185,7 +185,7 @@ static int arm7a_handle_l2x_cache_info_command(struct command_invocation *cmd,
}
command_print(cmd,
"L2 unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
"L2 unified cache Base Address 0x%" PRIx32 ", %" PRIu32 " ways",
l2x_cache->base, l2x_cache->way);
return ERROR_OK;

2
src/target/armv7a_mmu.c
View File

@ -266,7 +266,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
uint32_t first_lvl_descriptor = target_buffer_get_u32(target,
(uint8_t *)&first_lvl_ptbl[pt_idx]);
LOG_DEBUG("L1 desc[%8.8"PRIx32"]: %8.8"PRIx32, pt_idx << 20, first_lvl_descriptor);
LOG_DEBUG("L1 desc[%8.8x]: %8.8"PRIx32, pt_idx << 20, first_lvl_descriptor);
/* skip empty entries in the first level table */
if ((first_lvl_descriptor & 3) == 0) {

2
src/target/armv8.c
View File

@ -1054,7 +1054,7 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command)
nsec = n->name;
if (sec == NULL || nsec == NULL) {
LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02x", edeccr & 0xff);
LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02" PRIx32, edeccr & 0xff);
return ERROR_FAIL;
}

26
src/target/armv8_cache.c
View File

@ -203,10 +203,10 @@ static int armv8_handle_inner_cache_info_command(struct command_invocation *cmd,
if (arch->ctype & 1) {
command_print(cmd,
"L%d I-Cache: linelen %" PRIi32
", associativity %" PRIi32
", nsets %" PRIi32
", cachesize %" PRId32 " KBytes",
"L%d I-Cache: linelen %" PRIu32
", associativity %" PRIu32
", nsets %" PRIu32
", cachesize %" PRIu32 " KBytes",
cl+1,
arch->i_size.linelen,
arch->i_size.associativity,
@ -216,10 +216,10 @@ static int armv8_handle_inner_cache_info_command(struct command_invocation *cmd,
if (arch->ctype >= 2) {
command_print(cmd,
"L%d D-Cache: linelen %" PRIi32
", associativity %" PRIi32
", nsets %" PRIi32
", cachesize %" PRId32 " KBytes",
"L%d D-Cache: linelen %" PRIu32
", associativity %" PRIu32
", nsets %" PRIu32
", cachesize %" PRIu32 " KBytes",
cl+1,
arch->d_u_size.linelen,
arch->d_u_size.associativity,
@ -336,7 +336,7 @@ int armv8_identify_cache(struct armv8_common *armv8)
cache->iminline = 4UL << (ctr & 0xf);
cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRId32 " ctr.dminline %" PRId32,
LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
ctr, cache->iminline, cache->dminline);
/* retrieve CLIDR */
@ -373,13 +373,13 @@ int armv8_identify_cache(struct armv8_common *armv8)
goto done;
cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
LOG_DEBUG("data/unified cache index %d << %d, way %d << %d",
LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
cache->arch[cl].d_u_size.index,
cache->arch[cl].d_u_size.index_shift,
cache->arch[cl].d_u_size.way,
cache->arch[cl].d_u_size.way_shift);
LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
cache->arch[cl].d_u_size.linelen,
cache->arch[cl].d_u_size.cachesize,
cache->arch[cl].d_u_size.associativity);
@ -393,13 +393,13 @@ int armv8_identify_cache(struct armv8_common *armv8)
goto done;
cache->arch[cl].i_size = decode_cache_reg(cache_reg);
LOG_DEBUG("instruction cache index %d << %d, way %d << %d",
LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
cache->arch[cl].i_size.index,
cache->arch[cl].i_size.index_shift,
cache->arch[cl].i_size.way,
cache->arch[cl].i_size.way_shift);
LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
cache->arch[cl].i_size.linelen,
cache->arch[cl].i_size.cachesize,
cache->arch[cl].i_size.associativity);

6
src/target/armv8_dpm.c
View File

@ -253,11 +253,11 @@ static int dpmv8_exec_opcode(struct arm_dpm *dpm,
/* update dscr and el after each command execution */
dpm->dscr = dscr;
if (dpm->last_el != ((dscr >> 8) & 3))
LOG_DEBUG("EL %i -> %i", dpm->last_el, (dscr >> 8) & 3);
LOG_DEBUG("EL %i -> %" PRIu32, dpm->last_el, (dscr >> 8) & 3);
dpm->last_el = (dscr >> 8) & 3;
if (dscr & DSCR_ERR) {
LOG_ERROR("Opcode 0x%08"PRIx32", DSCR.ERR=1, DSCR.EL=%i", opcode, dpm->last_el);
LOG_ERROR("Opcode 0x%08" PRIx32 ", DSCR.ERR=1, DSCR.EL=%i", opcode, dpm->last_el);
armv8_dpm_handle_exception(dpm, true);
retval = ERROR_FAIL;
}
@ -560,7 +560,7 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
LOG_DEBUG("restoring mode, cpsr = 0x%08"PRIx32, cpsr);
} else {
LOG_DEBUG("setting mode 0x%"PRIx32, mode);
LOG_DEBUG("setting mode 0x%x", mode);
cpsr = mode;
}

8
src/target/cortex_a.c
View File

@ -2498,7 +2498,7 @@ static int cortex_a_read_phys_memory(struct target *target,
if (!count || !buffer)
return ERROR_COMMAND_SYNTAX_ERROR;
LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
address, size, count);
/* read memory through the CPU */
@ -2515,7 +2515,7 @@ static int cortex_a_read_memory(struct target *target, target_addr_t address,
int retval;
/* cortex_a handles unaligned memory access */
LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
address, size, count);
cortex_a_prep_memaccess(target, 0);
@ -2534,7 +2534,7 @@ static int cortex_a_write_phys_memory(struct target *target,
if (!count || !buffer)
return ERROR_COMMAND_SYNTAX_ERROR;
LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
address, size, count);
/* write memory through the CPU */
@ -2551,7 +2551,7 @@ static int cortex_a_write_memory(struct target *target, target_addr_t address,
int retval;
/* cortex_a handles unaligned memory access */
LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
address, size, count);
/* memory writes bypass the caches, must flush before writing */

2
src/target/dsp563xx.c
View File

@ -937,7 +937,7 @@ static int dsp563xx_examine(struct target *target)
if (((chip>>5)&0x1f) == 0)
chip += 300;
LOG_INFO("DSP56%03" PRId32 " device found", chip);
LOG_INFO("DSP56%03" PRIu32 " device found", chip);
/* Clear all breakpoints */
dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OBCR, 0);

16
src/target/esirisc_jtag.c
View File

@ -181,8 +181,8 @@ static int esirisc_jtag_check_status(struct esirisc_jtag *jtag_info)
{
uint8_t eid = esirisc_jtag_get_eid(jtag_info);
if (eid != EID_NONE) {
LOG_ERROR("esirisc_jtag: bad status: 0x%02" PRIx32 " (DA: %" PRId32 ", "
"S: %" PRId32 ", EID: 0x%02" PRIx32 ")",
LOG_ERROR("esirisc_jtag: bad status: 0x%02" PRIx8 " (DA: %" PRId32 ", "
"S: %" PRId32 ", EID: 0x%02" PRIx8 ")",
jtag_info->status, esirisc_jtag_is_debug_active(jtag_info),
esirisc_jtag_is_stopped(jtag_info), eid);
return ERROR_FAIL;
@ -201,13 +201,13 @@ static int esirisc_jtag_send_and_recv(struct esirisc_jtag *jtag_info, uint8_t co
retval = esirisc_jtag_send(jtag_info, command, num_out_fields, out_fields);
if (retval != ERROR_OK) {
LOG_ERROR("esirisc_jtag: send failed (command: 0x%02" PRIx32 ")", command);
LOG_ERROR("esirisc_jtag: send failed (command: 0x%02" PRIx8 ")", command);
return ERROR_FAIL;
}
retval = esirisc_jtag_recv(jtag_info, num_in_fields, in_fields);
if (retval != ERROR_OK) {
LOG_ERROR("esirisc_jtag: recv failed (command: 0x%02" PRIx32 ")", command);
LOG_ERROR("esirisc_jtag: recv failed (command: 0x%02" PRIx8 ")", command);
return ERROR_FAIL;
}
@ -409,7 +409,7 @@ int esirisc_jtag_read_reg(struct esirisc_jtag *jtag_info, uint8_t reg, uint32_t
return retval;
*data = le_to_h_u32(d);
LOG_DEBUG("register: 0x%" PRIx32 ", data: 0x%" PRIx32, reg, *data);
LOG_DEBUG("register: 0x%" PRIx8 ", data: 0x%" PRIx32, reg, *data);
return ERROR_OK;
}
@ -419,7 +419,7 @@ int esirisc_jtag_write_reg(struct esirisc_jtag *jtag_info, uint8_t reg, uint32_t
struct scan_field out_fields[2];
uint8_t d[4];
LOG_DEBUG("register: 0x%" PRIx32 ", data: 0x%" PRIx32, reg, data);
LOG_DEBUG("register: 0x%" PRIx8 ", data: 0x%" PRIx32, reg, data);
out_fields[0].num_bits = 8;
out_fields[0].out_value = &reg;
@ -457,7 +457,7 @@ int esirisc_jtag_read_csr(struct esirisc_jtag *jtag_info, uint8_t bank, uint8_t
return retval;
*data = le_to_h_u32(d);
LOG_DEBUG("bank: 0x%" PRIx32 ", csr: 0x%" PRIx32 ", data: 0x%" PRIx32, bank, csr, *data);
LOG_DEBUG("bank: 0x%" PRIx8 ", csr: 0x%" PRIx8 ", data: 0x%" PRIx32, bank, csr, *data);
return ERROR_OK;
}
@ -467,7 +467,7 @@ int esirisc_jtag_write_csr(struct esirisc_jtag *jtag_info, uint8_t bank, uint8_t
struct scan_field out_fields[2];
uint8_t c[2], d[4];
LOG_DEBUG("bank: 0x%" PRIx32 ", csr: 0x%" PRIx32 ", data: 0x%" PRIx32, bank, csr, data);
LOG_DEBUG("bank: 0x%" PRIx8 ", csr: 0x%" PRIx8 ", data: 0x%" PRIx32, bank, csr, data);
out_fields[0].num_bits = 16;
out_fields[0].out_value = c;

8
src/target/esirisc_trace.c
View File

@ -461,7 +461,7 @@ static int esirisc_trace_analyze_full(struct command_invocation *cmd, uint8_t *b
if (retval != ERROR_OK)
goto fail;
command_print(cmd, "repeats %" PRId32 " %s", count,
command_print(cmd, "repeats %" PRIu32 " %s", count,
(count == 1) ? "time" : "times");
break;
}
@ -470,13 +470,13 @@ static int esirisc_trace_analyze_full(struct command_invocation *cmd, uint8_t *b
return ERROR_OK;
default:
command_print(cmd, "invalid extended trace ID: %" PRId32, ext_id);
command_print(cmd, "invalid extended trace ID: %" PRIu32, ext_id);
return ERROR_FAIL;
}
break;
}
default:
command_print(cmd, "invalid trace ID: %" PRId32, id);
command_print(cmd, "invalid trace ID: %" PRIu32, id);
return ERROR_FAIL;
}
}
@ -729,7 +729,7 @@ COMMAND_HANDLER(handle_esirisc_trace_info_command)
command_print(CMD, "trigger delay: %s",
esirisc_trace_delay_strings[trace_info->delay]);
command_print(CMD, "trigger delay cycles: %i", trace_info->delay_cycles);
command_print(CMD, "trigger delay cycles: %" PRIu32, trace_info->delay_cycles);
return ERROR_OK;
}

4
src/target/ls1_sap.c
View File

@ -182,7 +182,7 @@ static int ls1_sap_read_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
LOG_DEBUG("Reading memory at physical address 0x%" TARGET_PRIxADDR
"; size %" PRId32 "; count %" PRId32, address, size, count);
"; size %" PRIu32 "; count %" PRIu32, address, size, count);
if (count == 0 || buffer == NULL)
return ERROR_COMMAND_SYNTAX_ERROR;
@ -204,7 +204,7 @@ static int ls1_sap_write_memory(struct target *target, target_addr_t address,
const uint8_t *buffer)
{
LOG_DEBUG("Writing memory at physical address 0x%" TARGET_PRIxADDR
"; size %" PRId32 "; count %" PRId32, address, size, count);
"; size %" PRIu32 "; count %" PRIu32, address, size, count);
if (count == 0 || buffer == NULL)

4
src/target/mem_ap.c
View File

@ -150,7 +150,7 @@ static int mem_ap_read_memory(struct target *target, target_addr_t address,
struct mem_ap *mem_ap = target->arch_info;
LOG_DEBUG("Reading memory at physical address " TARGET_ADDR_FMT
"; size %" PRId32 "; count %" PRId32, address, size, count);
"; size %" PRIu32 "; count %" PRIu32, address, size, count);
if (count == 0 || buffer == NULL)
return ERROR_COMMAND_SYNTAX_ERROR;
@ -165,7 +165,7 @@ static int mem_ap_write_memory(struct target *target, target_addr_t address,
struct mem_ap *mem_ap = target->arch_info;
LOG_DEBUG("Writing memory at physical address " TARGET_ADDR_FMT
"; size %" PRId32 "; count %" PRId32, address, size, count);
"; size %" PRIu32 "; count %" PRIu32, address, size, count);
if (count == 0 || buffer == NULL)
return ERROR_COMMAND_SYNTAX_ERROR;

10
src/target/mips32.c
View File

@ -725,7 +725,7 @@ int mips32_read_config_regs(struct target *target)
else
return ERROR_OK; /* already successfully read */
LOG_DEBUG("read %"PRId32" config registers", ejtag_info->config_regs);
LOG_DEBUG("read %"PRIu32" config registers", ejtag_info->config_regs);
if (ejtag_info->impcode & EJTAG_IMP_MIPS16) {
mips32->isa_imp = MIPS32_MIPS16;
@ -950,11 +950,11 @@ COMMAND_HANDLER(mips32_handle_cp0_command)
retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
if (retval != ERROR_OK) {
command_print(CMD,
"couldn't access reg %" PRIi32,
"couldn't access reg %" PRIu32,
cp0_reg);
return ERROR_OK;
}
command_print(CMD, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
cp0_reg, cp0_sel, value);
} else if (CMD_ARGC == 3) {
@ -963,11 +963,11 @@ COMMAND_HANDLER(mips32_handle_cp0_command)
retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
if (retval != ERROR_OK) {
command_print(CMD,
"couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
"couldn't access cp0 reg %" PRIu32 ", select %" PRIu32,
cp0_reg, cp0_sel);
return ERROR_OK;
}
command_print(CMD, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
cp0_reg, cp0_sel, value);
}
}

6
src/target/mips64_pracc.c
View File

@ -221,7 +221,7 @@ int mips64_pracc_exec(struct mips_ejtag *ejtag_info,
unsigned i;
for (i = 0; i < code_len; i++)
LOG_DEBUG("%08x", code[i]);
LOG_DEBUG("%08" PRIx32, code[i]);
ctx.local_iparam = param_in;
ctx.local_oparam = param_out;
@ -247,7 +247,7 @@ int mips64_pracc_exec(struct mips_ejtag *ejtag_info,
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
mips_ejtag_drscan_32(ejtag_info, &address32);
LOG_DEBUG("-> %08x", address32);
LOG_DEBUG("-> %08" PRIx32, address32);
address = 0xffffffffff200000ull | address32;
int psz = (ejtag_ctrl >> 29) & 3;
@ -1349,7 +1349,7 @@ int mips64_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info,
LOG_DEBUG("%s using " TARGET_ADDR_FMT " for write handler", __func__,
source->address);
LOG_DEBUG("daddiu: %08x", handler_code[11]);
LOG_DEBUG("daddiu: %08" PRIx32, handler_code[11]);
jmp_code[0] |= UPPER16(source->address);
jmp_code[1] |= LOWER16(source->address);

8
src/target/mips_m4k.c
View File

@ -1309,11 +1309,11 @@ COMMAND_HANDLER(mips_m4k_handle_cp0_command)
retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
if (retval != ERROR_OK) {
command_print(CMD,
"couldn't access reg %" PRIi32,
"couldn't access reg %" PRIu32,
cp0_reg);
return ERROR_OK;
}
command_print(CMD, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
cp0_reg, cp0_sel, value);
} else if (CMD_ARGC == 3) {
@ -1322,11 +1322,11 @@ COMMAND_HANDLER(mips_m4k_handle_cp0_command)
retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
if (retval != ERROR_OK) {
command_print(CMD,
"couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
"couldn't access cp0 reg %" PRIu32 ", select %" PRIu32,
cp0_reg, cp0_sel);
return ERROR_OK;
}
command_print(CMD, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
cp0_reg, cp0_sel, value);
}
}

12
src/target/mips_mips64.c
View File

@ -247,7 +247,7 @@ static int mips_mips64_set_hwbp(struct target *target, struct breakpoint *bp)
bp_num++;
if (bp_num >= mips64->num_inst_bpoints) {
LOG_DEBUG("ERROR Can not find free FP Comparator(bpid: %d)",
LOG_DEBUG("ERROR Can not find free FP Comparator(bpid: %" PRIu32 ")",
bp->unique_id);
LOG_WARNING("ERROR Can not find free FP Comparator");
exit(-1);
@ -274,7 +274,7 @@ static int mips_mips64_set_hwbp(struct target *target, struct breakpoint *bp)
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx64 "", bp->unique_id,
LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx64, bp->unique_id,
bp_num, c->bp_value);
return ERROR_OK;
@ -354,7 +354,7 @@ static int mips_mips64_set_breakpoint(struct target *target,
if (bp->type == BKPT_HARD) {
retval = mips_mips64_set_hwbp(target, bp);
} else {
LOG_DEBUG("bpid: %d", bp->unique_id);
LOG_DEBUG("bpid: %" PRIu32, bp->unique_id);
switch (bp->length) {
case MIPS64_SDBBP_SIZE:
@ -511,12 +511,12 @@ static int mips_mips64_unset_hwbp(struct target *target, struct breakpoint *bp)
bp_num = bp->set - 1;
if ((bp_num < 0) || (bp_num >= mips64->num_inst_bpoints)) {
LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
bp->unique_id);
return ERROR_OK;
}
LOG_DEBUG("bpid: %d - releasing hw: %d", bp->unique_id, bp_num);
LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d", bp->unique_id, bp_num);
comparator_list[bp_num].used = false;
comparator_list[bp_num].bp_value = 0;
@ -576,7 +576,7 @@ static int mips_mips64_unset_breakpoint(struct target *target,
if (bp->type == BKPT_HARD) {
retval = mips_mips64_unset_hwbp(target, bp);
} else {
LOG_DEBUG("bpid: %d", bp->unique_id);
LOG_DEBUG("bpid: %" PRIu32, bp->unique_id);
switch (bp->length) {
case MIPS64_SDBBP_SIZE:

2
src/target/nds32_reg.c
View File

@ -367,7 +367,7 @@ bool nds32_reg_exception(uint32_t number, uint32_t value)
field_value = (value >> ex_reg_value->ex_value_bit_pos) &
ex_reg_value->ex_value_mask;
if (field_value == ex_reg_value->ex_value) {
LOG_WARNING("It will generate exceptions as setting %" PRId32 " to %s",
LOG_WARNING("It will generate exceptions as setting %" PRIu32 " to %s",
value, nds32_regs[number].simple_mnemonic);
return true;
}

4
src/target/openrisc/or1k.c
View File

@ -923,7 +923,7 @@ static int or1k_add_breakpoint(struct target *target,
struct or1k_du *du_core = or1k_to_du(or1k);
uint8_t data;
LOG_DEBUG("Adding breakpoint: addr 0x%08" TARGET_PRIxADDR ", len %d, type %d, set: %d, id: %" PRId32,
LOG_DEBUG("Adding breakpoint: addr 0x%08" TARGET_PRIxADDR ", len %d, type %d, set: %d, id: %" PRIu32,
breakpoint->address, breakpoint->length, breakpoint->type,
breakpoint->set, breakpoint->unique_id);
@ -982,7 +982,7 @@ static int or1k_remove_breakpoint(struct target *target,
struct or1k_common *or1k = target_to_or1k(target);
struct or1k_du *du_core = or1k_to_du(or1k);
LOG_DEBUG("Removing breakpoint: addr 0x%08" TARGET_PRIxADDR ", len %d, type %d, set: %d, id: %" PRId32,
LOG_DEBUG("Removing breakpoint: addr 0x%08" TARGET_PRIxADDR ", len %d, type %d, set: %d, id: %" PRIu32,
breakpoint->address, breakpoint->length, breakpoint->type,
breakpoint->set, breakpoint->unique_id);

4
src/target/openrisc/or1k_du_adv.c
View File

@ -869,7 +869,7 @@ static int or1k_adv_cpu_reset(struct or1k_jtag *jtag_info, int action)
static int or1k_adv_jtag_read_memory(struct or1k_jtag *jtag_info,
uint32_t addr, uint32_t size, int count, uint8_t *buffer)
{
LOG_DEBUG("Reading WB%" PRId32 " at 0x%08" PRIx32, size * 8, addr);
LOG_DEBUG("Reading WB%" PRIu32 " at 0x%08" PRIx32, size * 8, addr);
int retval;
if (!jtag_info->or1k_jtag_inited) {
@ -924,7 +924,7 @@ static int or1k_adv_jtag_read_memory(struct or1k_jtag *jtag_info,
static int or1k_adv_jtag_write_memory(struct or1k_jtag *jtag_info,
uint32_t addr, uint32_t size, int count, const uint8_t *buffer)
{
LOG_DEBUG("Writing WB%" PRId32 " at 0x%08" PRIx32, size * 8, addr);
LOG_DEBUG("Writing WB%" PRIu32 " at 0x%08" PRIx32, size * 8, addr);
int retval;
if (!jtag_info->or1k_jtag_inited) {

8
src/target/openrisc/or1k_tap_vjtag.c
View File

@ -218,7 +218,7 @@ static int or1k_tap_vjtag_init(struct or1k_jtag *jtag_info)
LOG_DEBUG("m_width = %d", m_width);
LOG_DEBUG("manufacturer_id = 0x%02" PRIx32, MANUF(hub_info));
LOG_DEBUG("nb_of_node = %d", nb_nodes);
LOG_DEBUG("version = %" PRId32, VER(hub_info));
LOG_DEBUG("version = %" PRIu32, VER(hub_info));
LOG_DEBUG("VIR length = %d", guess_addr_width(nb_nodes) + m_width);
/* Because the number of SLD nodes is now known, the Nodes on the hub can be
@ -257,11 +257,11 @@ static int or1k_tap_vjtag_init(struct or1k_jtag *jtag_info)
LOG_DEBUG("Node info register");
LOG_DEBUG("--------------------");
LOG_DEBUG("instance_id = %" PRId32, ID(node_info));
LOG_DEBUG("instance_id = %" PRIu32, ID(node_info));
LOG_DEBUG("manufacturer_id = 0x%02" PRIx32, MANUF(node_info));
LOG_DEBUG("node_id = %" PRId32 " (%s)", ID(node_info),
LOG_DEBUG("node_id = %" PRIu32 " (%s)", ID(node_info),
id_to_string(ID(node_info)));
LOG_DEBUG("version = %" PRId32, VER(node_info));
LOG_DEBUG("version = %" PRIu32, VER(node_info));
if (ID(node_info) == VJTAG_NODE_ID)
vjtag_node_address = node_index + 1;

16
src/target/stm8.c
View File

@ -1308,7 +1308,7 @@ static int stm8_arch_state(struct target *target)
static int stm8_step(struct target *target, int current,
target_addr_t address, int handle_breakpoints)
{
LOG_DEBUG("%" PRIx32 " " TARGET_ADDR_FMT " %" PRIx32,
LOG_DEBUG("%x " TARGET_ADDR_FMT " %x",
current, address, handle_breakpoints);
/* get pointers to arch-specific information */
@ -1969,7 +1969,7 @@ int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi)
return e;
stm8->blocksize = w;
LOG_DEBUG("blocksize=%8.8x", stm8->blocksize);
LOG_DEBUG("blocksize=%8.8" PRIx32, stm8->blocksize);
return JIM_OK;
}
if (!strcmp(arg, "-flashstart")) {
@ -1988,7 +1988,7 @@ int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi)
return e;
stm8->flashstart = w;
LOG_DEBUG("flashstart=%8.8x", stm8->flashstart);
LOG_DEBUG("flashstart=%8.8" PRIx32, stm8->flashstart);
return JIM_OK;
}
if (!strcmp(arg, "-flashend")) {
@ -2007,7 +2007,7 @@ int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi)
return e;
stm8->flashend = w;
LOG_DEBUG("flashend=%8.8x", stm8->flashend);
LOG_DEBUG("flashend=%8.8" PRIx32, stm8->flashend);
return JIM_OK;
}
if (!strcmp(arg, "-eepromstart")) {
@ -2026,7 +2026,7 @@ int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi)
return e;
stm8->eepromstart = w;
LOG_DEBUG("eepromstart=%8.8x", stm8->eepromstart);
LOG_DEBUG("eepromstart=%8.8" PRIx32, stm8->eepromstart);
return JIM_OK;
}
if (!strcmp(arg, "-eepromend")) {
@ -2045,7 +2045,7 @@ int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi)
return e;
stm8->eepromend = w;
LOG_DEBUG("eepromend=%8.8x", stm8->eepromend);
LOG_DEBUG("eepromend=%8.8" PRIx32, stm8->eepromend);
return JIM_OK;
}
if (!strcmp(arg, "-optionstart")) {
@ -2064,7 +2064,7 @@ int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi)
return e;
stm8->optionstart = w;
LOG_DEBUG("optionstart=%8.8x", stm8->optionstart);
LOG_DEBUG("optionstart=%8.8" PRIx32, stm8->optionstart);
return JIM_OK;
}
if (!strcmp(arg, "-optionend")) {
@ -2083,7 +2083,7 @@ int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi)
return e;
stm8->optionend = w;
LOG_DEBUG("optionend=%8.8x", stm8->optionend);
LOG_DEBUG("optionend=%8.8" PRIx32, stm8->optionend);
return JIM_OK;
}
if (!strcmp(arg, "-enable_step_irq")) {

14
src/target/target.c
View File

@ -2201,7 +2201,7 @@ static int target_profiling_default(struct target *target, uint32_t *samples,
*/
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
{
LOG_DEBUG("writing buffer of %" PRIi32 " byte at " TARGET_ADDR_FMT,
LOG_DEBUG("writing buffer of %" PRIu32 " byte at " TARGET_ADDR_FMT,
size, address);
if (!target_was_examined(target)) {
@ -2263,7 +2263,7 @@ static int target_write_buffer_default(struct target *target,
*/
int target_read_buffer(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
{
LOG_DEBUG("reading buffer of %" PRIi32 " byte at " TARGET_ADDR_FMT,
LOG_DEBUG("reading buffer of %" PRIu32 " byte at " TARGET_ADDR_FMT,
size, address);
if (!target_was_examined(target)) {
@ -2333,7 +2333,7 @@ int target_checksum_memory(struct target *target, target_addr_t address, uint32_
if (retval != ERROR_OK) {
buffer = malloc(size);
if (buffer == NULL) {
LOG_ERROR("error allocating buffer for section (%" PRId32 " bytes)", size);
LOG_ERROR("error allocating buffer for section (%" PRIu32 " bytes)", size);
return ERROR_COMMAND_SYNTAX_ERROR;
}
retval = target_read_buffer(target, address, size, buffer);
@ -4301,7 +4301,7 @@ static int target_mem2array(Jim_Interp *interp, struct target *target, int argc,
} else {
char buf[100];
Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
sprintf(buf, "mem2array address: 0x%08" PRIx32 " is not aligned for %" PRId32 " byte reads",
sprintf(buf, "mem2array address: 0x%08" PRIx32 " is not aligned for %" PRIu32 " byte reads",
addr,
width);
Jim_AppendStrings(interp, Jim_GetResult(interp), buf, NULL);
@ -4333,7 +4333,7 @@ static int target_mem2array(Jim_Interp *interp, struct target *target, int argc,
retval = target_read_memory(target, addr, width, count, buffer);
if (retval != ERROR_OK) {
/* BOO !*/
LOG_ERROR("mem2array: Read @ 0x%08" PRIx32 ", w=%" PRId32 ", cnt=%" PRId32 ", failed",
LOG_ERROR("mem2array: Read @ 0x%08" PRIx32 ", w=%" PRIu32 ", cnt=%" PRIu32 ", failed",
addr,
width,
count);
@ -4507,7 +4507,7 @@ static int target_array2mem(Jim_Interp *interp, struct target *target,
} else {
char buf[100];
Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
sprintf(buf, "array2mem address: 0x%08" PRIx32 " is not aligned for %" PRId32 " byte reads",
sprintf(buf, "array2mem address: 0x%08" PRIx32 " is not aligned for %" PRIu32 " byte reads",
addr,
width);
Jim_AppendStrings(interp, Jim_GetResult(interp), buf, NULL);
@ -4556,7 +4556,7 @@ static int target_array2mem(Jim_Interp *interp, struct target *target,
retval = target_write_memory(target, addr, width, count, buffer);
if (retval != ERROR_OK) {
/* BOO !*/
LOG_ERROR("array2mem: Write @ 0x%08" PRIx32 ", w=%" PRId32 ", cnt=%" PRId32 ", failed",
LOG_ERROR("array2mem: Write @ 0x%08" PRIx32 ", w=%" PRIu32 ", cnt=%" PRIu32 ", failed",
addr,
width,
count);