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armv4_5: support weirdo ARMv6 secure monitor mode 

On the ARM PB1176JZF-S the system comes up in secure monitor
mode after reset. However the modebits in CPSR form the value
28 (0x1c) and CPSR is 0x800001dc deeming it UNRECOGNIZED.
Define this mode to be synonymous to mode 22 (MON) and things
start to work like a charm.

Change-Id: I001f7773ee1076202c0c633e466d2d833f7a1413
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-on: http://openocd.zylin.com/3196
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This commit is contained in:
Linus Walleij 2016-01-12 10:46:07 +01:00 committed by Andreas Fritiofson
parent f2fbcb217b
commit fed7131049
2 changed files with 8 additions and 0 deletions
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1
src/target/arm.h
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@ -61,6 +61,7 @@ enum arm_mode {
ARM_MODE_MON = 22,
ARM_MODE_ABT = 23,
ARM_MODE_UND = 27,
ARM_MODE_1176_MON = 28,
ARM_MODE_SYS = 31,
ARM_MODE_THREAD = 0,

7
src/target/armv4_5.c
View File

@ -140,6 +140,12 @@ static const struct {
.n_indices = ARRAY_SIZE(arm_mon_indices),
.indices = arm_mon_indices,
},
{
.name = "Secure Monitor ARM1176JZF-S",
.psr = ARM_MODE_1176_MON,
.n_indices = ARRAY_SIZE(arm_mon_indices),
.indices = arm_mon_indices,
},
/* These special modes are currently only supported
* by ARMv6M and ARMv7M profiles */
@ -199,6 +205,7 @@ int arm_mode_to_number(enum arm_mode mode)
case ARM_MODE_SYS:
return 6;
case ARM_MODE_MON:
case ARM_MODE_1176_MON:
return 7;
default:
LOG_ERROR("invalid mode value encountered %d", mode);