.. |
dynamic_part_select
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Adding latch tests for shift&mask AST dynamic part-select enhancements
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2020-06-09 15:17:01 -05:00 |
.gitignore
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Add plugin.so.dSYM to .gitignore
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2021-01-18 11:13:21 -07:00 |
abc9.v
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Another sloppy mistake!
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2019-11-21 16:33:20 -08:00 |
abc9.ys
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abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
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2020-05-29 17:17:40 -07:00 |
async.sh
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Improve tests/various/async, disable failing ffl test
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2019-07-09 22:21:25 +02:00 |
async.v
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Fix tests/various/async FFL test
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2019-07-09 22:44:39 +02:00 |
attrib05_port_conn.v
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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2019-06-04 10:42:42 +02:00 |
attrib05_port_conn.ys
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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2019-06-04 10:42:42 +02:00 |
attrib07_func_call.v
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tests: fix some test warnings
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2020-05-25 10:07:58 -07:00 |
attrib07_func_call.ys
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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2019-06-04 10:42:42 +02:00 |
autoname.ys
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autoname: add testcase with $-prefix-ed port
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2020-01-14 10:13:03 -08:00 |
bug1496.ys
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Fix #1496.
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2019-11-18 04:16:48 +01:00 |
bug1531.ys
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Add testcase
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2019-12-11 16:52:37 -08:00 |
bug1614.ys
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add testcase for #1614
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2020-02-03 21:29:54 +01:00 |
bug1710.ys
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ast: fixes #1710; do not generate RTLIL for unreachable ternary
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2020-02-27 16:55:55 -08:00 |
bug1745.ys
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Add regression tests for new handling of comments in constants
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2020-03-14 11:41:09 +01:00 |
bug1781.ys
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fsm_extract: Initialize celltypes with full design.
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2020-03-19 18:51:21 +01:00 |
bug1876.ys
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tests: add testcases from #1876
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2020-04-14 12:39:10 -07:00 |
bug2014.ys
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test: add test for #2014
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2020-05-02 14:22:37 -07:00 |
chparam.sh
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Add tests/various/chparam.sh
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2019-05-06 16:03:15 +02:00 |
const_arg_loop.v
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Fix constants bound to redeclared function args
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2020-12-26 08:48:01 -07:00 |
const_arg_loop.ys
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Avoid generating wires for function args which are constant
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2020-07-24 21:18:24 -06:00 |
const_func.v
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Allow reals as constant function parameters
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2020-07-19 20:27:09 -06:00 |
const_func.ys
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Allow constant function calls in for loops and generate if and case
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2020-06-29 16:06:17 -06:00 |
const_func_block_var.v
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Allow localparams in constant functions
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2020-08-20 20:10:24 -04:00 |
const_func_block_var.ys
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Allow blocks with declarations within constant functions
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2020-07-25 10:16:12 -06:00 |
constcomment.ys
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Add regression tests for new handling of comments in constants
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2020-03-14 11:41:09 +01:00 |
constmsk_test.v
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Added tests/various/constmsk_test.ys
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2014-09-04 15:07:30 +02:00 |
constmsk_test.ys
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Added tests/various/constmsk_test.ys
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2014-09-04 15:07:30 +02:00 |
constmsk_testmap.v
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tests: fix some test warnings
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2020-05-25 10:07:58 -07:00 |
deminout_unused.ys
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deminout: Don't demote inouts with unused bits
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2020-03-04 18:44:38 +00:00 |
design.ys
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design: add test
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2020-04-16 12:48:40 -07:00 |
design1.ys
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design: add test
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2020-04-16 12:48:40 -07:00 |
design2.ys
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tests: add design -delete tests
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2020-04-16 08:05:18 -07:00 |
dynamic_part_select.ys
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Removing trailing whitespace
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2020-06-10 10:35:40 -05:00 |
elab_sys_tasks.sv
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Initial implementation of elaboration system tasks
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2019-05-03 03:10:43 +03:00 |
elab_sys_tasks.ys
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Initial implementation of elaboration system tasks
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2019-05-03 03:10:43 +03:00 |
equiv_opt_multiclock.ys
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Add equiv_opt -multiclock
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2019-09-11 13:55:59 +01:00 |
equiv_opt_undef.ys
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equiv_induct: Fix up assumption for $equiv cells in -undef mode.
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2020-07-27 18:36:13 +02:00 |
exec.ys
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Add test for `exec` command.
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2020-03-16 07:52:58 +00:00 |
fib.v
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verilog: improved support for recursive functions
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2020-12-31 18:33:59 -07:00 |
fib.ys
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verilog: improved support for recursive functions
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2020-12-31 18:33:59 -07:00 |
func_port_implied_dir.sv
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sv: complete support for implied task/function port directions
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2020-12-31 16:17:13 -07:00 |
func_port_implied_dir.ys
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sv: complete support for implied task/function port directions
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2020-12-31 16:17:13 -07:00 |
gen_if_null.v
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verilog: allow null gen-if then block
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2020-05-06 08:43:02 -04:00 |
gen_if_null.ys
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verilog: allow null gen-if then block
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2020-05-06 08:43:02 -04:00 |
global_scope.ys
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ast: Fix handling of identifiers in the global scope
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2020-04-16 10:30:07 +01:00 |
gzip_verilog.v.gz
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Add support for reading gzip'd input files
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2019-07-26 10:23:58 +01:00 |
gzip_verilog.ys
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Add support for reading gzip'd input files
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2019-07-26 10:23:58 +01:00 |
help.ys
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Add "help -all" and "help -celltypes" sanity test
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2020-01-28 18:11:34 -08:00 |
hierarchy.sh
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Fix tests
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2019-04-21 11:40:20 +02:00 |
hierarchy_defer.ys
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Expand test with `hierarchy' without -auto-top
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2019-09-03 12:17:26 -07:00 |
hierarchy_param.ys
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hierarchy: Convert positional parameters to named.
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2020-04-21 19:09:00 +02:00 |
ice40_mince_abc9.ys
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Add test for abc9+mince issue
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2020-03-20 20:35:28 +00:00 |
integer_range_bad_syntax.ys
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Revert "Revert PRs #2203 and #2244."
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2020-07-10 09:59:48 +02:00 |
integer_real_bad_syntax.ys
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Revert "Revert PRs #2203 and #2244."
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2020-07-10 09:59:48 +02:00 |
logger_error.ys
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Added back tests for logger
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2020-03-13 15:00:18 +01:00 |
logger_nowarning.ys
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Added back tests for logger
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2020-03-13 15:00:18 +01:00 |
logger_warn.ys
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Added back tests for logger
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2020-03-13 15:00:18 +01:00 |
logger_warning.ys
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Added back tests for logger
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2020-03-13 15:00:18 +01:00 |
logic_param_simple.ys
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Revert "Revert PRs #2203 and #2244."
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2020-07-10 09:59:48 +02:00 |
mem2reg.ys
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Change attribute search value to specify precise location instead of simple line number.
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2020-02-24 01:39:36 +00:00 |
memory_word_as_index.data
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Fix elaboration of whole memory words used as indices
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2020-12-26 21:47:38 -07:00 |
memory_word_as_index.v
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Fix elaboration of whole memory words used as indices
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2020-12-26 21:47:38 -07:00 |
memory_word_as_index.ys
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Fix elaboration of whole memory words used as indices
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2020-12-26 21:47:38 -07:00 |
muxcover.ys
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Merge origin/master
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2019-06-27 11:20:15 -07:00 |
muxpack.v
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Add more tests
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2019-06-21 12:31:04 -07:00 |
muxpack.ys
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Removal of more `stat` calls from tests
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2019-08-18 21:28:45 -07:00 |
peepopt.ys
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peepopt: Remove now-redundant dffmux pattern.
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2020-08-07 13:21:34 +02:00 |
plugin.cc
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Use C++11 final/override keywords.
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2020-06-18 23:34:52 +00:00 |
plugin.sh
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tests: use `yosys-config --datdir` instead of hard-coded
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2020-04-22 08:29:45 -07:00 |
pmgen_reduce.ys
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Add test for pmtest_test "reduce" demo pattern
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2019-08-17 14:05:10 +02:00 |
pmux2shiftx.v
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Cleanup tests
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2020-02-27 10:17:29 -08:00 |
pmux2shiftx.ys
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Add #1135 testcase
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2019-06-27 11:02:52 -07:00 |
port_sign_extend.v
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genrtlil: fix mux2rtlil generated wire signedness
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2020-12-22 17:49:16 -07:00 |
port_sign_extend.ys
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Sign extend port connections where necessary
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2020-12-18 20:33:14 -07:00 |
primitives.ys
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tests: add tests for primitives' src
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2020-05-04 10:21:47 -07:00 |
printattr.ys
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printattrs: Add test.
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2020-05-27 08:00:00 +00:00 |
rand_const.sv
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Allow combination of rand and const modifiers
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2021-01-21 08:42:05 -07:00 |
rand_const.ys
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Allow combination of rand and const modifiers
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2021-01-21 08:42:05 -07:00 |
reg_wire_error.sv
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Modified errors into warnings
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2018-06-05 18:03:22 +03:00 |
reg_wire_error.ys
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reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
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2018-06-05 18:00:06 +03:00 |
run-test.sh
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tests: Centralize test collection and Makefile generation
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2020-09-21 15:07:02 +02:00 |
scratchpad.ys
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add assert option to scratchpad command
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2019-12-16 14:00:21 +01:00 |
script.ys
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Update test for Pass::call_on_module()
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2019-07-02 08:22:31 -07:00 |
sformatf.ys
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ast: Add support for $sformatf system function
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2020-01-19 21:20:17 +00:00 |
shregmap.v
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tests: fix some test warnings
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2020-05-25 10:07:58 -07:00 |
shregmap.ys
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Remove Xilinx test
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2019-08-22 16:18:07 -07:00 |
signed.ys
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Revert "Revert PRs #2203 and #2244."
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2020-07-10 09:59:48 +02:00 |
signext.ys
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Extend sign extension tests
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2019-06-20 12:43:59 -07:00 |
sim_const.ys
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sim: Fix handling of constant-connected cell inputs at startup
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2020-04-21 08:58:52 +01:00 |
specify.v
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verilog: ignore ranges too without -specify
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2020-02-13 17:58:43 -08:00 |
specify.ys
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verilog: fix specify src attribute
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2020-05-04 10:53:06 -07:00 |
src.ys
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verilog: add test
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2020-03-11 06:51:03 -07:00 |
submod.ys
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Remove submod changes
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2019-12-30 14:56:14 -08:00 |
submod_extract.ys
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Added tests/various/submod_extract.ys
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2014-07-26 17:22:18 +02:00 |
sv_defines.ys
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Add support for SystemVerilog-style `define to Verilog frontend
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2020-03-27 16:08:26 +00:00 |
sv_defines_dup.ys
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Add support for SystemVerilog-style `define to Verilog frontend
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2020-03-27 16:08:26 +00:00 |
sv_defines_mismatch.ys
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Add support for SystemVerilog-style `define to Verilog frontend
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2020-03-27 16:08:26 +00:00 |
sv_defines_too_few.ys
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Add support for SystemVerilog-style `define to Verilog frontend
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2020-03-27 16:08:26 +00:00 |
sv_implicit_ports.sh
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sv: More tests for wildcard port connections
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2020-02-02 16:12:33 +00:00 |
svalways.sh
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sv: Add tests for SV always types
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2019-11-21 21:06:28 +00:00 |
wreduce.ys
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Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
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2019-08-12 12:06:45 -07:00 |
write_gzip.ys
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Do not use Verific in tests/various/write_gzip.ys
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2019-08-16 14:22:46 +02:00 |
xaiger.ys
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xaiger: add testcase
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2020-05-24 08:48:23 -07:00 |