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Zachary Snow 4b2f977331 genrtlil: fix signed port connection codegen failures 
This fixes binding signed memory reads, signed unary expressions, and
signed complex SigSpecs to ports. This also sets `is_signed` for wires
generated from signed params when -pwires is used. Though not necessary
for any of the current usages, `is_signed` is now appropriately set when
the `extendWidth` helper is used.
 		2021-02-05 19:51:30 -05:00
..
dynamic_part_select Adding latch tests for shift&mask AST dynamic part-select enhancements 2020-06-09 15:17:01 -05:00
.gitignore Add plugin.so.dSYM to .gitignore 2021-01-18 11:13:21 -07:00
abc9.v Another sloppy mistake! 2019-11-21 16:33:20 -08:00
abc9.ys abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ 2020-05-29 17:17:40 -07:00
async.sh Improve tests/various/async, disable failing ffl test 2019-07-09 22:21:25 +02:00
async.v Fix tests/various/async FFL test 2019-07-09 22:44:39 +02:00
attrib05_port_conn.v Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog. 2019-06-04 10:42:42 +02:00
attrib05_port_conn.ys Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog. 2019-06-04 10:42:42 +02:00
attrib07_func_call.v tests: fix some test warnings 2020-05-25 10:07:58 -07:00
attrib07_func_call.ys Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog. 2019-06-04 10:42:42 +02:00
autoname.ys autoname: add testcase with $-prefix-ed port 2020-01-14 10:13:03 -08:00
bug1496.ys Fix #1496. 2019-11-18 04:16:48 +01:00
bug1531.ys Add testcase 2019-12-11 16:52:37 -08:00
bug1614.ys add testcase for #1614 2020-02-03 21:29:54 +01:00
bug1710.ys ast: fixes #1710; do not generate RTLIL for unreachable ternary 2020-02-27 16:55:55 -08:00
bug1745.ys Add regression tests for new handling of comments in constants 2020-03-14 11:41:09 +01:00
bug1781.ys fsm_extract: Initialize celltypes with full design. 2020-03-19 18:51:21 +01:00
bug1876.ys tests: add testcases from #1876 2020-04-14 12:39:10 -07:00
bug2014.ys test: add test for #2014 2020-05-02 14:22:37 -07:00
chparam.sh Add tests/various/chparam.sh 2019-05-06 16:03:15 +02:00
const_arg_loop.v Fix constants bound to redeclared function args 2020-12-26 08:48:01 -07:00
const_arg_loop.ys Avoid generating wires for function args which are constant 2020-07-24 21:18:24 -06:00
const_func.v Allow reals as constant function parameters 2020-07-19 20:27:09 -06:00
const_func.ys Allow constant function calls in for loops and generate if and case 2020-06-29 16:06:17 -06:00
const_func_block_var.v Allow localparams in constant functions 2020-08-20 20:10:24 -04:00
const_func_block_var.ys Allow blocks with declarations within constant functions 2020-07-25 10:16:12 -06:00
constcomment.ys Add regression tests for new handling of comments in constants 2020-03-14 11:41:09 +01:00
constmsk_test.v Added tests/various/constmsk_test.ys 2014-09-04 15:07:30 +02:00
constmsk_test.ys Added tests/various/constmsk_test.ys 2014-09-04 15:07:30 +02:00
constmsk_testmap.v tests: fix some test warnings 2020-05-25 10:07:58 -07:00
deminout_unused.ys deminout: Don't demote inouts with unused bits 2020-03-04 18:44:38 +00:00
design.ys design: add test 2020-04-16 12:48:40 -07:00
design1.ys design: add test 2020-04-16 12:48:40 -07:00
design2.ys tests: add design -delete tests 2020-04-16 08:05:18 -07:00
dynamic_part_select.ys Removing trailing whitespace 2020-06-10 10:35:40 -05:00
elab_sys_tasks.sv Initial implementation of elaboration system tasks 2019-05-03 03:10:43 +03:00
elab_sys_tasks.ys Initial implementation of elaboration system tasks 2019-05-03 03:10:43 +03:00
equiv_opt_multiclock.ys Add equiv_opt -multiclock 2019-09-11 13:55:59 +01:00
equiv_opt_undef.ys equiv_induct: Fix up assumption for $equiv cells in -undef mode. 2020-07-27 18:36:13 +02:00
exec.ys Add test for `exec` command. 2020-03-16 07:52:58 +00:00
fib.v verilog: improved support for recursive functions 2020-12-31 18:33:59 -07:00
fib.ys verilog: improved support for recursive functions 2020-12-31 18:33:59 -07:00
func_port_implied_dir.sv sv: complete support for implied task/function port directions 2020-12-31 16:17:13 -07:00
func_port_implied_dir.ys sv: complete support for implied task/function port directions 2020-12-31 16:17:13 -07:00
gen_if_null.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
gen_if_null.ys verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
global_scope.ys ast: Fix handling of identifiers in the global scope 2020-04-16 10:30:07 +01:00
gzip_verilog.v.gz Add support for reading gzip'd input files 2019-07-26 10:23:58 +01:00
gzip_verilog.ys Add support for reading gzip'd input files 2019-07-26 10:23:58 +01:00
help.ys Add "help -all" and "help -celltypes" sanity test 2020-01-28 18:11:34 -08:00
hierarchy.sh Fix tests 2019-04-21 11:40:20 +02:00
hierarchy_defer.ys Expand test with `hierarchy' without -auto-top 2019-09-03 12:17:26 -07:00
hierarchy_param.ys hierarchy: Convert positional parameters to named. 2020-04-21 19:09:00 +02:00
ice40_mince_abc9.ys Add test for abc9+mince issue 2020-03-20 20:35:28 +00:00
integer_range_bad_syntax.ys Revert "Revert PRs #2203 and #2244." 2020-07-10 09:59:48 +02:00
integer_real_bad_syntax.ys Revert "Revert PRs #2203 and #2244." 2020-07-10 09:59:48 +02:00
logger_error.ys Added back tests for logger 2020-03-13 15:00:18 +01:00
logger_nowarning.ys Added back tests for logger 2020-03-13 15:00:18 +01:00
logger_warn.ys Added back tests for logger 2020-03-13 15:00:18 +01:00
logger_warning.ys Added back tests for logger 2020-03-13 15:00:18 +01:00
logic_param_simple.ys Revert "Revert PRs #2203 and #2244." 2020-07-10 09:59:48 +02:00
mem2reg.ys Change attribute search value to specify precise location instead of simple line number. 2020-02-24 01:39:36 +00:00
memory_word_as_index.data Fix elaboration of whole memory words used as indices 2020-12-26 21:47:38 -07:00
memory_word_as_index.v Fix elaboration of whole memory words used as indices 2020-12-26 21:47:38 -07:00
memory_word_as_index.ys Fix elaboration of whole memory words used as indices 2020-12-26 21:47:38 -07:00
muxcover.ys Merge origin/master 2019-06-27 11:20:15 -07:00
muxpack.v Add more tests 2019-06-21 12:31:04 -07:00
muxpack.ys Removal of more `stat` calls from tests 2019-08-18 21:28:45 -07:00
peepopt.ys peepopt: Remove now-redundant dffmux pattern. 2020-08-07 13:21:34 +02:00
plugin.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
plugin.sh tests: use `yosys-config --datdir` instead of hard-coded 2020-04-22 08:29:45 -07:00
pmgen_reduce.ys Add test for pmtest_test "reduce" demo pattern 2019-08-17 14:05:10 +02:00
pmux2shiftx.v Cleanup tests 2020-02-27 10:17:29 -08:00
pmux2shiftx.ys Add #1135 testcase 2019-06-27 11:02:52 -07:00
port_sign_extend.v genrtlil: fix signed port connection codegen failures 2021-02-05 19:51:30 -05:00
port_sign_extend.ys genrtlil: fix signed port connection codegen failures 2021-02-05 19:51:30 -05:00
primitives.ys tests: add tests for primitives' src 2020-05-04 10:21:47 -07:00
printattr.ys printattrs: Add test. 2020-05-27 08:00:00 +00:00
rand_const.sv Allow combination of rand and const modifiers 2021-01-21 08:42:05 -07:00
rand_const.ys Allow combination of rand and const modifiers 2021-01-21 08:42:05 -07:00
reg_wire_error.sv Modified errors into warnings 2018-06-05 18:03:22 +03:00
reg_wire_error.ys reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files 2018-06-05 18:00:06 +03:00
run-test.sh tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
scratchpad.ys add assert option to scratchpad command 2019-12-16 14:00:21 +01:00
script.ys Update test for Pass::call_on_module() 2019-07-02 08:22:31 -07:00
sformatf.ys ast: Add support for $sformatf system function 2020-01-19 21:20:17 +00:00
shregmap.v tests: fix some test warnings 2020-05-25 10:07:58 -07:00
shregmap.ys Remove Xilinx test 2019-08-22 16:18:07 -07:00
signed.ys Revert "Revert PRs #2203 and #2244." 2020-07-10 09:59:48 +02:00
signext.ys Extend sign extension tests 2019-06-20 12:43:59 -07:00
sim_const.ys sim: Fix handling of constant-connected cell inputs at startup 2020-04-21 08:58:52 +01:00
specify.v verilog: ignore ranges too without -specify 2020-02-13 17:58:43 -08:00
specify.ys verilog: fix specify src attribute 2020-05-04 10:53:06 -07:00
src.ys verilog: add test 2020-03-11 06:51:03 -07:00
submod.ys Remove submod changes 2019-12-30 14:56:14 -08:00
submod_extract.ys Added tests/various/submod_extract.ys 2014-07-26 17:22:18 +02:00
sv_defines.ys Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
sv_defines_dup.ys Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
sv_defines_mismatch.ys Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
sv_defines_too_few.ys Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
sv_implicit_ports.sh sv: More tests for wildcard port connections 2020-02-02 16:12:33 +00:00
svalways.sh sv: Add tests for SV always types 2019-11-21 21:06:28 +00:00
wreduce.ys Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 2019-08-12 12:06:45 -07:00
write_gzip.ys Do not use Verific in tests/various/write_gzip.ys 2019-08-16 14:22:46 +02:00
xaiger.ys xaiger: add testcase 2020-05-24 08:48:23 -07:00