Henner Zeller
1a60126a34
Provide source-location logging.
...
o Provide log_file_warning() and log_file_error() that prefix the log
message with <filename>:<lineno>: to be easily picked up by IDEs that
need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
2018-07-19 10:22:02 -07:00
Benedikt Tutzer
0371519c39
Added Monitor class that can monitor all changes in a Design or in a Module
2018-07-10 12:51:02 +02:00
Benedikt Tutzer
e7d3f3cd46
added destructors for wires and cells
2018-07-10 08:52:36 +02:00
Benedikt Tutzer
55df7fff19
removed debug output
2018-07-09 16:02:10 +02:00
Benedikt Tutzer
da8083dbd0
commands can now be run on arbitrary designs, not only on the active one
2018-07-09 16:01:56 +02:00
Benedikt Tutzer
8ebaeecd83
multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues
2018-07-09 15:48:06 +02:00
Benedikt Tutzer
7911379d4a
Introduced namespace and removed class-prefixes to increase readability
2018-06-28 15:07:21 +02:00
Benedikt Tutzer
ccb4dcd013
changed references from hash-ids to IdString names
2018-06-28 14:44:28 +02:00
Benedikt Tutzer
a27fa1833e
added wrappers for Design, Modules, Cells and Wires
2018-06-25 17:08:29 +02:00
Robert Ou
0abe7c6c77
Modify emscripten main to mount nodefs and to run arg as a script
2018-05-18 22:53:52 -07:00
Robert Ou
bd87462b47
Fix reading techlibs under emscripten
2018-05-18 22:42:33 -07:00
Christian Krämer
c1ecb1b2f1
Add "#ifdef __FreeBSD__"
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(Re-commit e3575a8
with corrected author field)
2018-05-13 13:08:26 +02:00
Clifford Wolf
1167538d26
Revert "Add "#ifdef __FreeBSD__""
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This reverts commit e3575a86c5
.
2018-05-13 13:06:36 +02:00
Johnny Sorocil
e3575a86c5
Add "#ifdef __FreeBSD__"
2018-05-05 13:02:44 +02:00
Clifford Wolf
5c03aeac60
Add "yosys -e regex" for turning warnings into errors
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-04 15:27:28 +02:00
Clifford Wolf
0acea3548b
Set stack size to at least 128 MB (large stack needed for parsing huge expressions)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-27 15:04:10 +02:00
Edmond Cote
64ea55056a
Rename rename to renames
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Create TCL alias for rename command. Using renames. Following the same convention as proc -> procs.
2018-03-20 15:50:50 -07:00
Larry Doolittle
82fecc98c0
Harmonize uses of _WIN32 macro
2018-03-11 16:01:30 +01:00
Clifford Wolf
e5534a080e
Improve handling of warning messages
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 22:35:59 +01:00
Clifford Wolf
2935e8ea41
Update copyright header
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 21:31:10 +01:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Clifford Wolf
82c436587c
Do not create deep backtraces unless in ENABLE_DEBUG mode
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-03 15:04:39 +01:00
Clifford Wolf
a96c775a73
Add support for "yosys -E"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-07 16:36:13 +01:00
Clifford Wolf
c80315cea4
Bugfix in hierarchy handling of blackbox module ports
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-05 13:28:45 +01:00
Clifford Wolf
76afff7ef6
Add RTLIL::Const::is_fully_ones()
2017-12-14 02:06:39 +01:00
Clifford Wolf
96ad688849
Add SigSpec::is_fully_ones()
2017-12-14 01:29:09 +01:00
Kevin Kiningham
7350f7692a
Use quote includes for yosys.h
2017-12-13 13:27:52 -08:00
Clifford Wolf
9ae25039fb
Add support for editline as replacement for readline
2017-11-08 02:55:00 +01:00
Clifford Wolf
13eb47c692
Add src arguments to all cell creator helper functions
2017-09-09 10:16:48 +02:00
Clifford Wolf
8a66bd30c6
Update more stuff to use get_src_attribute() and set_src_attribute()
2017-09-01 12:26:55 +02:00
Jason Lowdermilk
71d43cfc08
Merge remote-tracking branch 'upstream/master'
2017-08-30 11:47:06 -06:00
Jason Lowdermilk
271e8ba7cd
fix indent level
2017-08-30 11:46:41 -06:00
Clifford Wolf
8530333439
Add {get,set}_src_attribute() methods on RTLIL::AttrObject
2017-08-30 11:39:11 +02:00
Jason Lowdermilk
32c0f1193e
Add support for source line tracking through synthesis phase
2017-08-29 14:46:35 -06:00
Clifford Wolf
d3b3dd8e88
Add hashlib support for hashing of pools
2017-08-22 13:04:33 +02:00
Clifford Wolf
bce0bb6e43
Add consteval support for $_ANDNOT_ and $_ORNOT_
2017-08-22 13:04:05 +02:00
Clifford Wolf
4ba5bd12c6
Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef()
2017-08-18 11:40:08 +02:00
Clifford Wolf
159701962a
Auto-detect JSON front-end
2017-08-09 13:28:52 +02:00
Clifford Wolf
2336d5508b
Add log_warning_noprefix() API, Use for Verific warnings and errors
2017-07-27 12:17:04 +02:00
Clifford Wolf
493fedbaf9
Add "using std::get" to yosys.h
2017-07-25 14:52:34 +02:00
Clifford Wolf
c251e3a576
Change intptr_t to uintptr_t in hashlib.h
2017-07-18 17:38:19 +02:00
Robert Ou
f0741698fa
Fix build warnings for win64
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Win64 has a 32-bit long. Use intptr_t to work on any data model.
2017-07-17 12:36:43 -07:00
Clifford Wolf
1f517d2b96
Fix history namespace collision
2017-06-20 05:26:12 +02:00
Clifford Wolf
c0ca99483c
Store command history when terminating with an error
2017-06-20 04:41:58 +02:00
Clifford Wolf
05df3dbee4
Add "setundef -anyseq"
2017-05-28 11:59:05 +02:00
Clifford Wolf
662a047815
Enable readline and tcl in mxe builds
2017-05-17 20:46:22 +02:00
Clifford Wolf
6934b862d3
Add missing AndnotGate() and OrnotGate() declarations to rtlil.h
2017-05-17 19:10:57 +02:00
Clifford Wolf
05cdd58c8d
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
Clifford Wolf
fcb274a564
Add ConstEval defaultval feature
2017-04-05 11:25:22 +02:00
Clifford Wolf
b8d7f57f61
Add front-end detection for *.tcl files
2017-03-28 12:13:58 +02:00
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Clifford Wolf
c6d8d70109
Fix mingw compile issue (2nd attempt)
2017-02-23 14:21:02 +01:00
Clifford Wolf
0822b21844
Fix mingw compile issue (maybe.. I can't test it)
2017-02-23 13:59:02 +01:00
Clifford Wolf
e6d56d23b5
Fix eval implementation of $_NOR_
2017-02-16 12:17:03 +01:00
Clifford Wolf
828303791b
Add "yosys -w" for suppressing warnings
2017-02-12 11:11:00 +01:00
Clifford Wolf
63dfdb5d7f
Add log_wire() API
2017-02-11 11:08:36 +01:00
Clifford Wolf
aab58045a8
Fix undef propagation bug in $pmux SAT model
2017-02-05 22:43:33 +01:00
Clifford Wolf
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
Clifford Wolf
b54972c112
Fix RTLIL::Memory::start_offset initialization
2017-01-25 17:00:59 +01:00
Clifford Wolf
6b2c23c721
Bugfix in RTLIL::SigSpec::remove2()
2016-12-31 16:14:42 +01:00
Clifford Wolf
33a22f8768
Simplified log_spacer() code
2016-12-23 02:06:46 +01:00
Clifford Wolf
a0dff87a57
Added "yosys -W regex"
2016-12-22 23:41:44 +01:00
Clifford Wolf
f144adec58
Added AIGER back-end to automatic back-end detection
2016-12-21 10:16:47 +01:00
Clifford Wolf
00761de1b7
Bugfix in comment handling
2016-12-13 13:48:09 +01:00
Clifford Wolf
a926a6afc2
Remember global declarations and defines accross read_verilog calls
2016-11-15 12:42:43 +01:00
Clifford Wolf
fa535c0b00
Some minor build fixes for Visual C
2016-10-14 18:36:02 +02:00
Clifford Wolf
bdc316db50
Added $anyseq cell type
2016-10-14 15:24:03 +02:00
Clifford Wolf
53655d173b
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
Clifford Wolf
8ebba8a35f
Added $ff and $_FF_ cell types
2016-10-12 01:18:39 +02:00
Clifford Wolf
59508c99b4
define PATH_MAX if not defined by limits.h
2016-10-11 12:12:09 +02:00
Clifford Wolf
cb7dbf4070
Improvements in assertpmux
2016-09-07 12:42:16 +02:00
Clifford Wolf
6f41e5277d
Removed $aconst cell type
2016-08-30 19:09:56 +02:00
Clifford Wolf
eae390ae17
Removed $predict again
2016-08-28 21:35:33 +02:00
Clifford Wolf
23afeadb5e
Fixed handling of transparent bram rd ports on ROMs
2016-08-27 17:06:22 +02:00
Clifford Wolf
f8a77abfac
Added glob support to all front-ends
2016-08-22 15:05:57 +02:00
William D. Jones
5299b17056
Add MSYS2-compatible build.
2016-08-16 14:41:59 -04:00
Clifford Wolf
5767e4bc4d
Use _Exit(0) on win32, always use _Exit(1) in log_error()
2016-08-16 09:38:54 +02:00
Clifford Wolf
39da8eddae
Added log_const() API
2016-08-09 19:56:10 +02:00
Yury Gribov
f7730d43bb
Use /proc/self/exe on Cygwin as well.
2016-08-08 12:00:27 +02:00
Clifford Wolf
8d88fcb270
Added SatGen support for $anyconst
2016-07-27 15:52:20 +02:00
Clifford Wolf
9540be1d45
Removed $predict support from SatGen
2016-07-27 15:44:11 +02:00
Clifford Wolf
4056312987
Added $anyconst and $aconst
2016-07-27 15:41:22 +02:00
Clifford Wolf
a7b0769623
Added "read_verilog -dump_rtlil"
2016-07-27 15:40:17 +02:00
Clifford Wolf
8537c4d206
Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()
2016-07-25 16:39:25 +02:00
Clifford Wolf
b1c432af56
Improvements in CellEdgesDatabase
2016-07-24 17:21:53 +02:00
Clifford Wolf
f162b858f2
Added CellEdgesDatabase API
2016-07-24 13:59:57 +02:00
Clifford Wolf
89deb412c6
Added satgen initstate support
2016-07-22 10:28:45 +02:00
Clifford Wolf
5c166e76e5
Added $initstate cell type and vlog function
2016-07-21 14:23:22 +02:00
Clifford Wolf
d7763634b6
After reading the SV spec, using non-standard predict() instead of expect()
2016-07-21 13:34:33 +02:00
Clifford Wolf
721f1f5ecf
Added basic support for $expect cells
2016-07-13 16:56:17 +02:00
Ruben Undheim
a8200a773f
A few modifications after pull request comments
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- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
2016-06-18 14:23:38 +02:00
Ruben Undheim
178ff3e7f6
Added support for SystemVerilog packages with localparam definitions
2016-06-18 10:53:55 +02:00
Clifford Wolf
ebece2b8d5
Added $sop SAT model
2016-06-17 17:47:30 +02:00
Clifford Wolf
95757efb25
Improved support for $sop cells
2016-06-17 16:31:16 +02:00
Clifford Wolf
52bb1b968d
Added $sop cell type and "abc -sop"
2016-06-17 13:50:09 +02:00
Clifford Wolf
864eeadcd9
Added missing "#define HASHLIB_H"
2016-05-14 11:43:20 +02:00
Clifford Wolf
570014800a
Include <cmath> in yosys.h
2016-05-08 10:50:39 +02:00
Clifford Wolf
f103bfb9ba
Fixes for MXE build
2016-05-07 10:53:18 +02:00
Clifford Wolf
9aa4b3309c
Added "yosys -D ALL"
2016-04-24 17:12:34 +02:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
a07f893a5f
Minor hashlib bugfix
2016-04-16 23:20:11 +02:00
Clifford Wolf
ace462237f
Hashlib indenting fix
2016-04-05 13:25:23 +02:00
Clifford Wolf
2553319081
Added ScriptPass helper class for script-like passes
2016-03-31 11:16:34 +02:00
Clifford Wolf
6f1b6dc322
Added log_dump() support for dict<> and pool<> containers
2016-03-31 09:57:44 +02:00
Clifford Wolf
0db53284fd
We have 2016 for a while now
2016-03-30 13:52:26 +02:00
Clifford Wolf
48dbc75bed
Added .vhd file extension support
2016-03-30 13:24:49 +02:00
Clifford Wolf
95784437ac
Merge pull request #137 from ravenexp/master
...
Embed DATDIR make variable value into yosys binary.
2016-03-28 16:54:23 +02:00
Sebastian Kuzminsky
73870c1edf
fix a cut-n-paste error in the -h help
2016-03-26 11:15:35 -06:00
Sergey Kvachonok
963c0d2525
Embed DATDIR make variable value into yosys binary.
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Use it as the last resort in the share/ directory location search.
2016-03-26 11:16:53 +03:00
Clifford Wolf
45af4a4acf
Use easyer-to-read unoptimized ceil_log2()
...
see here for details on the optimized version:
http://svn.clifford.at/handicraft/2016/esbmc/ceilog2.c
2016-02-15 23:06:18 +01:00
Clifford Wolf
0c4b311242
Fixed more visual studio warnings
2016-02-14 09:35:25 +01:00
Clifford Wolf
bcc873b805
Fixed some visual studio warnings
2016-02-13 17:31:24 +01:00
Clifford Wolf
0d7fd2585e
Added "int ceil_log2(int)" function
2016-02-13 16:52:16 +01:00
Clifford Wolf
ba407da187
Added addBufGate module method
2016-02-02 11:26:07 +01:00
Clifford Wolf
01bcc5663f
SigMap performance improvement
2016-02-01 10:10:20 +01:00
Clifford Wolf
ea492abcf0
hashlib mfp<> performance improvements
2016-02-01 10:03:03 +01:00
Clifford Wolf
13e15a24a2
Added reserve() method to haslib classes and
...
calculate hashtable size based on entries capacity, not size
2016-01-31 22:50:34 +01:00
Rick Altherr
3c48de8e21
rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)
...
Converting to a pool<SigBit> is fairly expensive due to inserts somewhat
frequently causing rehashing. Instead, walk through the pattern SigSpec
directly on a chunk-by-chunk basis and apply it to this SigSpec's
individual bits. Using chunks for the pattern minimizes the number of
iterations in the outer loop.
2016-01-31 09:20:16 -08:00
Rick Altherr
0265d7b100
rtlil: speed up SigSpec::sort_and_unify()
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std::set<> internally is often a red-black tree which is fairly
expensive to create but fast to lookup. In the case of
sort_and_unify(), a set<> is constructed as a temporary object to
attempt to speed up lookups. Being a temporarily, however, the cost of
creation far outweights the lookup improvement and is a net performance
loss. Instead, sort the vector<> that already exists and then apply
std::unique().
2016-01-31 09:20:16 -08:00
Rick Altherr
89dc40f162
rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)
2016-01-31 09:20:16 -08:00
Rick Altherr
cd3e1095b0
rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)
2016-01-31 09:20:16 -08:00
Clifford Wolf
5462399c88
Meaningless coding style change
2016-01-31 16:12:35 +01:00
Rick Altherr
43756559d8
rtlil: rewrite remove2() to avoid copying
2016-01-30 00:28:07 -08:00
Rick Altherr
12ebdef17c
rtlil: duplicate remove2() for std::set<>
2016-01-29 23:06:40 -08:00
Rick Altherr
9e26147ccd
rtlil: change IdString comparison operators to take references instead of copies
2016-01-29 23:06:40 -08:00
Clifford Wolf
33a5b28e25
Added default values for hashlib at() methods
2015-12-02 20:41:57 +01:00
Clifford Wolf
276101f032
Re-added SigMap::allbits()
2015-11-30 19:43:52 +01:00
Clifford Wolf
6459e3ac39
Removed dangling ';' in rtlil.h
2015-11-26 18:11:34 +01:00
Clifford Wolf
1e32e4bdae
Improved SigMap performance
2015-10-28 11:21:55 +01:00
Clifford Wolf
e69efec588
Improvements in new SigMap
2015-10-28 00:39:53 +01:00
Clifford Wolf
f3db70d2f3
Removed old SigMap implementation
2015-10-27 15:09:44 +01:00
Clifford Wolf
09b4050f2e
Added hashlib::mfp and new SigMap
2015-10-27 15:04:47 +01:00
Clifford Wolf
d014ba2d0e
Major refactoring of equiv_struct
2015-10-25 19:31:29 +01:00
Clifford Wolf
207736b4ee
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
Clifford Wolf
da923c198e
Added "equiv_add -cell"
2015-10-25 14:35:40 +01:00
Clifford Wolf
7f110e7018
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
2015-10-24 22:56:40 +02:00
Clifford Wolf
a1c3df7fe4
Fixed driver conflict handling (various cmds)
2015-10-24 19:23:30 +02:00
Clifford Wolf
6fe48cf41e
equiv_purge bugfix, using SigChunk in Yosys namespace
2015-10-24 19:09:45 +02:00
Clifford Wolf
2a0f577f83
Fixed handling of driver-driver conflicts in wreduce
2015-10-24 13:44:35 +02:00
Clifford Wolf
281a033e92
Added support for ":" as comment symbol after ;-parsing
2015-10-23 20:08:33 +02:00
Clifford Wolf
5d1c0ce7c0
Progress on cell help messages
2015-10-17 02:35:19 +02:00
Clifford Wolf
7d3a3a3173
Added first help messages for cell types
2015-10-14 16:27:42 +02:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
Clifford Wolf
d212d4d0c1
Cosmetic fix in Module::addLut()
2015-09-18 21:55:12 +02:00
Andrei Errapart
522176c946
Removed unnecessary cast.
2015-09-01 12:40:36 +02:00
Andrei Errapart
09176bcf3f
Microsoft Visual C++ fixes in hashlib; template specializations on int32_t and int64_t.
2015-09-01 12:40:24 +02:00
Andrei Errapart
744a5333f5
Microsoft Visual C++ fix for log.h.
2015-09-01 12:40:12 +02:00
Clifford Wolf
ee8f6f31f4
Added SigMap::allbits()
2015-08-31 16:42:19 +02:00
Clifford Wolf
ff50bc2ac3
Added $tribuf and $_TBUF_ cell types
2015-08-16 12:54:52 +02:00
Clifford Wolf
84bf862f7c
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00