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7,467 Commits 84 Branches 48 Tags 64 MiB
Commit Graph

80 Commits

Author SHA1 Message Date
Eddie Hung a67af3d5e5 Use new port() overload once more 2019-09-23 13:00:44 -07:00
Eddie Hung 53817b8575 Use new port/param overload in pmg 2019-09-20 14:21:22 -07:00
Eddie Hung d88903e610 Cleanup xilinx_dsp 2019-09-20 12:03:25 -07:00
Eddie Hung ed187ef1cf Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT 2019-09-20 10:00:09 -07:00
Eddie Hung 8a94ce7aa5 Add an index 2019-09-19 20:04:44 -07:00
Eddie Hung 64a72ed51e Do not perform width-checks for DSP48E1 which is much more complicated 2019-09-19 14:50:11 -07:00
Eddie Hung ea5e5a212e Cleanup xilinx_dsp too 2019-09-19 14:34:06 -07:00
Eddie Hung 29d446d758 Cleanup 2019-09-19 10:39:00 -07:00
Eddie Hung 347cbf59bd Check overflow condition is power of 2 without using int32 2019-09-18 12:16:03 -07:00
Eddie Hung 1f18736d20 Add support for overflow using pattern detector 2019-09-18 09:39:59 -07:00
Eddie Hung 0932e23dff Separate dffrstmux from dffcemux, fix typos 2019-09-18 09:34:42 -07:00
Eddie Hung f3081c20e7 Add support for A1 and B1 registers 2019-09-11 17:16:46 -07:00
Eddie Hung 6fa6bf483c Rename {A,B} -> {A2,B2} 2019-09-11 16:21:24 -07:00
Eddie Hung e9eb855d38 Make unextend a udata 2019-09-11 13:06:49 -07:00
Eddie Hung 0d709d2bb5 Add support for A/B/C/D/AD reset 2019-09-11 10:15:19 -07:00
Eddie Hung ded805ae5d Add support for RSTM 2019-09-11 07:34:14 -07:00
Eddie Hung b08797da6b Only pack out registers if \init is zero or x; then remove \init from PREG 2019-09-10 21:33:14 -07:00
Eddie Hung af147d1430 Add support for RSTP 2019-09-10 20:51:48 -07:00
Eddie Hung c6df55a9e7 enpol -> cepol 2019-09-10 18:59:03 -07:00
Eddie Hung 86700c2bea d?ffmux -> d?ffcemux 2019-09-10 18:52:54 -07:00
Eddie Hung 8b8a68b38a Refactor MREG and PREG to out_dffe subpattern 2019-09-10 18:27:05 -07:00
Eddie Hung 2c04430445 Only trim sigM if USE_MULT; only look for ffM then too 2019-09-09 20:57:03 -07:00
Eddie Hung 6348f9512c Rename 2019-09-09 16:45:38 -07:00
Eddie Hung 1df9c5d277 Oops 2019-09-09 16:07:40 -07:00
Eddie Hung 5f8f0e1383 Tidy up 2019-09-09 15:59:10 -07:00
Eddie Hung 04bc287271 Refactor using subpattern in_dffe 2019-09-09 15:51:14 -07:00
Eddie Hung 74a5c802f7 Pack CREG 2019-09-06 21:01:36 -07:00
Eddie Hung 6a9205280f Use unextend lambda 2019-09-06 18:40:11 -07:00
Eddie Hung b69512a5b9 Fix ffP just like ffPmux 2019-09-06 15:51:21 -07:00
Eddie Hung 5344bfe637 Perform D replacement properly 2019-09-06 15:46:15 -07:00
Eddie Hung 74eac76699 Add support for DREG 2019-09-06 15:32:26 -07:00
Eddie Hung ef56f8596f Fine tune nusers when postAdd 2019-09-06 15:11:41 -07:00
Eddie Hung 0d1d8b4d24 Fix macc and mul tests 2019-09-06 14:57:36 -07:00
Eddie Hung 8246062acf Fix enable polarity 2019-09-06 14:36:10 -07:00
Eddie Hung e926f2973e Add support for pre-adder and AD register 2019-09-06 14:06:57 -07:00
Eddie Hung 776d769941 Use more index patterns 2019-09-06 12:07:35 -07:00
Eddie Hung a945f6c7ef Fix ffPmux to cope with offset 2019-09-06 11:58:56 -07:00
Eddie Hung fbf1b74946 Simplify filter expressions 2019-09-06 11:39:20 -07:00
Eddie Hung 39a5d046ea Fix nusers condition in ffP 2019-09-06 11:38:19 -07:00
Eddie Hung cdc1e1f5c2 Check adder is <= 48 bits before packing 2019-09-06 10:35:06 -07:00
Eddie Hung 91f68c4de2 Check nusers for M and P enable muxes 2019-09-06 09:59:35 -07:00
Eddie Hung 4fe24b20f9 More nusers() checks for A and B enable muxes 2019-09-06 09:47:32 -07:00
Eddie Hung 174edbcb96 Sensitive to CEB CEM CEP polarity 2019-09-05 21:38:35 -07:00
Eddie Hung 53ca536d67 ffAmuxAB -> ffAenpol 2019-09-05 21:28:28 -07:00
Eddie Hung a32b14a55f Do not check signedness of post-adder (assume taken care of by DSP) 2019-09-05 12:38:47 -07:00
Eddie Hung 7bd55f379c Use filter instead of index; support wide enable muxes 2019-09-05 11:55:14 -07:00
Eddie Hung fe5a1324c9 Do not make ff[MP]mux semioptional, use sigmap 2019-09-05 11:46:38 -07:00
Eddie Hung 447a31e75d Add support for CEP 2019-09-05 11:00:27 -07:00
Eddie Hung 05282afc25 Add support for CEB, remove check on nusers 2019-09-05 10:46:33 -07:00
Eddie Hung 0166e02e78 Cleanup 2019-09-05 10:07:56 -07:00