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8024 Commits

Author SHA1 Message Date
Miodrag Milanović 7c074ef844
Merge pull request #1436 from YosysHQ/mmicko/msvc_fix 
Fixes for MSVC build
 2019-10-05 07:48:30 +02:00
Eddie Hung 6c5e1234e1 Add comment on why partial multipliers are 18x18 2019-10-04 22:31:04 -07:00
Eddie Hung 792cd31052 Add comments for xilinx_dsp_cascade 2019-10-04 22:31:04 -07:00
Eddie Hung 12fd2ec4f0 Improve comments for xilinx_dsp_CREG 2019-10-04 22:31:04 -07:00
Eddie Hung 14e4aeece6 Fix comment 2019-10-04 22:31:04 -07:00
Eddie Hung 8027ebf05b Restore optimisation for sigM.empty() 2019-10-04 22:31:04 -07:00
Eddie Hung 77d7a5c14a Retry on fixing TODOs 2019-10-04 22:31:04 -07:00
Eddie Hung 52583ecff8 Revert "Fix TODOs" 
This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
 2019-10-04 22:31:04 -07:00
Eddie Hung 6d68972619 More comments, cleanup 2019-10-04 22:31:04 -07:00
Eddie Hung 7de9c33931 Fix TODOs 2019-10-04 22:31:04 -07:00
Eddie Hung 983068103e Consistency 2019-10-04 22:31:04 -07:00
Eddie Hung cf82b38478 Add comments for xilinx_dsp 2019-10-04 22:31:04 -07:00
Eddie Hung b47bb5c810 Fix typo in check_label() 2019-10-04 21:43:50 -07:00
Eddie Hung a2ef93f03a abc -> abc9 2019-10-04 17:56:38 -07:00
Eddie Hung a5ac33f230 Merge branch 'master' into eddie/abc_to_abc9 2019-10-04 17:53:20 -07:00
Eddie Hung f0cadb0de8 Fix from merge 2019-10-04 17:52:19 -07:00
Eddie Hung bbc0e06af3 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-04 17:39:08 -07:00
Eddie Hung 0acc51c3d8 Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` 2019-10-04 17:35:43 -07:00
Eddie Hung d4212d128b Use read_args for read_verilog 2019-10-04 17:27:05 -07:00
Eddie Hung 9c23811839 Remove DSP48E1 from *_cells_xtra.v 2019-10-04 17:26:42 -07:00
Eddie Hung 7959e9d6b2 Fix merge issues 2019-10-04 17:21:14 -07:00
Eddie Hung 7a45cd5856 Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff 2019-10-04 16:58:55 -07:00
Eddie Hung 74ef8feeaf Fix xilinx_dsp for unsigned extensions 2019-10-04 16:46:15 -07:00
Eddie Hung 6bf7114bbd Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again 2019-10-04 16:45:36 -07:00
Eddie Hung 279fd22ddf Add Const::{begin,end,empty}() 2019-10-04 15:00:57 -07:00
Eddie Hung aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
Eddie Hung 9fef1df3c1 Panic over. Model was elsewhere. Re-arrange for consistency 2019-10-04 10:48:44 -07:00
Eddie Hung 4e11782cde Oops 2019-10-04 10:36:02 -07:00
Eddie Hung c0f54d3fd5 Ohmilord this wasn't added all this time!?! 2019-10-04 10:34:16 -07:00
Eddie Hung 84f978bdc2 Add -async2sync to help text as per @daveshah1 2019-10-04 10:17:46 -07:00
Miodrag Milanovic c0b14cfea7 Fixes for MSVC build 2019-10-04 16:29:46 +02:00
Miodrag Milanovic 44c3472b9f FF should be initialized to 0 2019-10-04 13:27:10 +02:00
Miodrag Milanovic c0fa6f3e1a Split mux tests per type 2019-10-04 13:05:16 +02:00
Miodrag Milanovic 1b80489486 Split latch check 2019-10-04 13:00:09 +02:00
Miodrag Milanovic 77d557d00b Add missing latch mapping 2019-10-04 12:58:11 +02:00
Miodrag Milanovic 2c3e140246 split rest od ff's 2019-10-04 12:51:45 +02:00
Miodrag Milanovic 3de7889d08 Separate check for ff's types 2019-10-04 12:48:27 +02:00
Miodrag Milanovic 286a272872 Cleaned tests 2019-10-04 12:42:06 +02:00
Miodrag Milanovic f94dc2c072 Remove not needed tests 2019-10-04 12:41:41 +02:00
Miodrag Milanovic ef417fb1b3 Merge branch 'SergeyDegtyar/efinix' of https://github.com/SergeyDegtyar/yosys into mmicko/efinix 2019-10-04 12:20:49 +02:00
Miodrag Milanovic 03a3deec43 Cleanup and formating 2019-10-04 11:09:59 +02:00
Miodrag Milanovic a5844e3ceb split latches into separate checks 2019-10-04 11:08:42 +02:00
Miodrag Milanovic 3238ee7d35 check muxes per type 2019-10-04 11:04:18 +02:00
Miodrag Milanovic 91ad3ab717 check ff's separately 2019-10-04 11:00:49 +02:00
Miodrag Milanovic 3d3479b0af Cleanup top modules and not used defines 2019-10-04 10:57:47 +02:00
Miodrag Milanovic 1435b9bf97 remove alu test 2019-10-04 10:55:13 +02:00
Miodrag Milanovic b932654964 Merge branch 'SergeyDegtyar/anlogic' of https://github.com/SergeyDegtyar/yosys into mmicko/anlogic 2019-10-04 10:52:16 +02:00
Miodrag Milanovic 7785f23719 Check latches type one by one 2019-10-04 10:31:51 +02:00
Miodrag Milanovic 3358b2f185 Removed top module where not needed 2019-10-04 09:53:54 +02:00
Miodrag Milanovic 3c40c81030 Test muxes synth one by one 2019-10-04 08:52:54 +02:00