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487 Commits

Author SHA1 Message Date
Eddie Hung 723815b384 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-30 13:26:19 -07:00
Eddie Hung 295c18bd6b Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-30 09:50:20 -07:00
Eddie Hung 6e475484b2 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-30 09:37:32 -07:00
David Shah 6919c0f9b0 Merge branch 'master' into xc7dsp 2019-08-30 13:57:15 +01:00
Eddie Hung 9314a0a42e Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor 2019-08-28 10:51:39 -07:00
Eddie Hung ba5d81c7f1 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-28 09:21:03 -07:00
Marcin Kościelnicki d361f5ab79 xilinx: Add SRLC16E primitive. 
Fixes #1331.
 2019-08-27 20:27:12 +02:00
Eddie Hung 1ba09c4ab7 Merge branch 'master' into eddie/xilinx_srl 2019-08-26 13:56:31 -07:00
Eddie Hung a098205479 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-26 13:25:17 -07:00
Eddie Hung d7051b90de Add undocumented feature 2019-08-23 16:41:32 -07:00
Eddie Hung 08139aa53a xilinx_srl now copes with word-level flops $dff{,e} 2019-08-23 12:22:46 -07:00
Eddie Hung 78b7d8f531 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-23 11:32:44 -07:00
Eddie Hung 20f4d191b5 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-23 11:24:19 -07:00
Eddie Hung 509c353fe9 Forgot one 2019-08-23 11:23:50 -07:00
Eddie Hung 0d0ad15898 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-23 11:23:31 -07:00
Eddie Hung a270af00cc Put abc_* attributes above port 2019-08-23 11:21:44 -07:00
Eddie Hung 6872805a3e Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap 2019-08-23 10:00:50 -07:00
Eddie Hung 15188033da Add variable length support to xilinx_srl 2019-08-21 17:34:40 -07:00
Eddie Hung edec73fec1 abc9 to perform new 'map_ffs' before 'map_luts' 2019-08-21 15:37:55 -07:00
Eddie Hung 5ce0c31d0e Add init support 2019-08-21 13:05:10 -07:00
Eddie Hung b7a48e3e0f Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-20 20:18:17 -07:00
Eddie Hung 33960dd3d8
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx 
[WIP] synth xilinx renaming, as per #1184
 2019-08-20 12:55:26 -07:00
Eddie Hung d9fe4cccbf Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx 2019-08-20 11:57:52 -07:00
Eddie Hung d81a090d89 Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro 2019-08-19 09:56:17 -07:00
Eddie Hung 562c9e3624 Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules 2019-08-16 15:40:53 -07:00
Eddie Hung 261daffd9d Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-15 12:19:47 -07:00
Marcin Kościelnicki 3c75a72feb move attributes to wires 2019-08-13 19:36:59 +00:00
Eddie Hung ed4b2834ef Add assign PCOUT = P to DSP48E1 2019-08-13 12:19:26 -07:00
Marcin Kościelnicki 49765ec19e minor review fixes 2019-08-13 18:05:49 +00:00
Eddie Hung 2a1b98d478 Add DSP_A_MAXWIDTH_PARTIAL, refactor 2019-08-13 10:21:24 -07:00
David Shah edff79a25a xilinx: Rework labels for faster Verilator testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-13 10:29:42 +01:00
Marcin Kościelnicki c6d5b97b98 review fixes 2019-08-13 00:35:54 +00:00
Marcin Kościelnicki f4c62f33ac Add clock buffer insertion pass, improve iopadmap. 
A few new attributes are defined for use in cell libraries:

- iopad_external_pin: marks PAD cell's external-facing pin.  Pad
  insertion will be skipped for ports that are already connected
  to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
  buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
  Clock buffer insertion will be skipped for nets that are already
  driven by such a pin.

All three are module attributes that should be set to a comma-separeted
list of pin names.

Clock buffer insertion itself works as follows:

1. All cell ports, starting from bottom up, can be marked as clock sinks
   (requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
   buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
   contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
   also connected to a clock sink port in a contained cell, a clock
   buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
   connected to clock sinks, optionally with a special kind of input
   PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
   attribute is set on it.
 2019-08-13 00:16:38 +02:00
Eddie Hung f890cfb63b Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-12 11:32:10 -07:00
Eddie Hung 0b5b56c1ec Pack partial-product adder DSP48E1 packing 2019-08-09 15:19:33 -07:00
Eddie Hung 1f722b3500 Remove signed from ports in +/xilinx/dsp_map.v 2019-08-08 16:33:20 -07:00
Eddie Hung 162eab6b74 Combine techmap calls 2019-08-08 10:55:48 -07:00
Eddie Hung 7160243874 Move xilinx_dsp to before alumacc 2019-08-08 10:45:56 -07:00
Eddie Hung 57b2e4b9c1 INMODE is 5 bits 2019-08-08 10:44:35 -07:00
Eddie Hung 13cc106cf7 Fix copy-pasta typo 2019-08-08 10:44:26 -07:00
David Shah b8cd4ad64a DSP48E1 sim model: add SIMD tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:39:35 +01:00
David Shah 57aeb4cc01 DSP48E1 model: test CE inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:32:43 +01:00
David Shah d60b3c0dc8 DSP48E1 sim model: fix seq tests and add preadder tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:18:37 +01:00
David Shah e7dbe7bb3d DSP48E1 sim model: seq test working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:52:04 +01:00
David Shah f6605c7dc0 DSP48E1 sim model: Comb, no pre-adder, mode working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:26:44 +01:00
David Shah f0f352e971 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:05:11 +01:00
David Shah ccfb4ff2a9 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 09:31:34 +01:00
Eddie Hung 48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
David Shah fe95807f16 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 13:09:12 +01:00
David Shah c43b0c4b49 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 18:47:18 +01:00