Commit Graph

1046 Commits

Author SHA1 Message Date
Claire Wolf 27506d2aeb Improve net priorities in EDIF back-end
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-21 12:35:25 +02:00
whitequark abc8f1fcb6
Merge pull request #1961 from whitequark/paramod-original-name
ast, rpc: record original name of $paramod\* as \hdlname attribute
2020-04-21 01:43:20 +00:00
Claire Wolf ee5067e864 Ignore conflicting keep attributes, unless asked not to. Fixes #1733
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-20 16:00:37 +02:00
whitequark bf0f96b847 cxxrtl: provide attributes to black box factories, too.
Both parameters and attributes are necessary because the parameters
have to be the same between every instantiation of the cell, but
attributes may well vary. For example, for an UART PHY, the type
of the PHY (tty, pty, socket) would be a parameter, but configuration
of the implementation specified by the type (socket address) would
be an attribute.
2020-04-19 16:30:54 +00:00
whitequark 63d2a30857 cxxrtl: add templated black box support. 2020-04-18 08:04:57 +00:00
whitequark ab4297c326 cxxrtl: make eval() and commit() inline in blackboxes.
This change is a preparation for template blackboxes. It has no
effect on current generated code.
2020-04-18 04:38:50 +00:00
whitequark 2b88d9a3fe cxxrtl: add simple black box support.
This commit adds support for replacing RTLIL modules with CXXRTL
black boxes. Black box port widths may not depend on the parameters
with which it is instantiated (yet); the parameters may only be used
to change the behavior of the black box.
2020-04-18 04:35:10 +00:00
whitequark 8bc3cd30dc cxxrtl: use ID::X instead of ID(X). NFC. 2020-04-18 04:35:10 +00:00
whitequark 41421f5dca ast, rpc: record original name of $paramod\* as \hdlname attribute.
The $paramod name mangling is not invertible (the \ character, which
separates the module name from the parameters, is valid in the module
name itself), which does not stop people from trying to invert it.

This commit makes it easy to invert the name mangling by storing
the original name explicitly, and fixes the firrtl backend to use
the newly introduced attribute.
2020-04-18 03:47:28 +00:00
whitequark e7ad209b15 cxxrtl: correctly handle `sync always` rules.
Fixes #1948.
2020-04-17 09:43:13 +00:00
whitequark b4b2345a10
Merge pull request #1947 from whitequark/cxxrtl-usability
cxxrtl: minor documentation and usability improvements
2020-04-16 21:28:13 +00:00
Claire Wolf 7a434cdd7b
Merge pull request #1797 from epfl-vlsc/firrtl_backend_fileinfo
Keep file information when emitting firrtl
2020-04-16 18:50:43 +02:00
whitequark 06c0338f2c cxxrtl: make ROMs writable, document memory::operator[].
There is no practical benefit from using `const memory` for ROMs;
it uses an std::vector internally, which prevents contemporary
compilers from constant-propagating ROM contents. (It is not clear
whether they are permitted to do so.)

However, there is a major benefit from using non-const `memory` for
ROMs, which is the ability to dynamically fill the ROM for each
individual simulation.
2020-04-16 16:45:54 +00:00
whitequark 9043632dcc cxxrtl: fix misleading example, caution about race conditions.
Fixes #1944.
2020-04-16 16:45:54 +00:00
whitequark 58e89cd368 cxxrtl: remove inaccurate comment. NFC. 2020-04-16 16:45:54 +00:00
N. Engelhardt 0b7a5879e5
Merge pull request #1830 from boqwxp/qbfsat
Add `qbfsat` command to integrate exists-forall solving and specialization
2020-04-15 17:33:50 +02:00
Marcelina Kościelnicka 3611e7c864 json: Update format documentation.
Fixes #1693.
2020-04-15 16:12:14 +02:00
David Shah 3b85b7c57a cxxrtl: Fix handling of unclocked memory read ports
Signed-off-by: David Shah <dave@ds0.me>
2020-04-14 20:39:13 +01:00
whitequark d8f2a1fda0
Merge pull request #1922 from whitequark/write_cxxrtl-disconnected-outputs
write_cxxrtl: ignore disconnected module ports
2020-04-14 14:37:48 +00:00
whitequark 7025881a5e
Merge pull request #1921 from whitequark/write_cxxrtl-separate-compilation
write_cxxrtl: enable separate compilation
2020-04-14 13:53:52 +00:00
whitequark 0d0bf9c4a2 write_cxxrtl: ignore disconnected module ports.
E.g. port `q` in `submod x(.p(p), .q());`.

Fixes #1920.
2020-04-14 12:36:20 +00:00
whitequark 9c64d37a4c write_verilog: fix precondition check. 2020-04-14 12:12:50 +00:00
whitequark 102fb5424f write_cxxrtl: enable separate compilation.
This commit makes it possible to use several cxxrtl-generated files
in one application, as well as compiling cxxrtl-generated code as
a separate compilation unit.
2020-04-14 12:07:58 +00:00
Eddie Hung 0808318d55 xaiger: add check for $__ABC9_DELAY model 2020-04-13 19:11:23 -07:00
Miodrag Milanovic 0d789c5a3b Support custom PROGRAM_PREFIX 2020-04-10 10:38:40 +02:00
Sahand Kashani 959a00a46f Fix indentation 2020-04-09 21:16:02 +02:00
whitequark 4737f426ff write_cxxrtl: add basic documentation. 2020-04-09 04:08:36 +00:00
whitequark 753e34007d write_cxxrtl: add support for $dlatch and $dlatchsr cells.
Also, fix codegen for $dffe and $adff.
2020-04-09 04:08:36 +00:00
whitequark 711df56ad0 write_cxxrtl: add support for $sr cell.
Also, fix the semantics of SET/CLR inputs of the $dffsr cell, and
fix the scheduling of async FF cells to consider ARST/SET/CLR->Q
as a forward combinatorial arc.
2020-04-09 04:08:36 +00:00
whitequark 9534b51277 write_cxxrtl: add support for $slice and $concat cells. 2020-04-09 04:08:36 +00:00
whitequark 01e6850bd3 write_cxxrtl: improve writable memory handling.
This commit reduces space and time overhead for writable memories
to O(write port count) in both cases; implements handling for write
port priorities; and simplifies runtime representation of memories.
2020-04-09 04:08:36 +00:00
whitequark fb0270b752 write_cxxrtl: add support for hierarchical designs.
Hierarchical design simulations are generally much slower, but this
comes with a major increase in flexibility:
 1. Since the `flatten` pass currently does not support flattening
    of designs with processes, this is the only way to simulate such
    designs with cxxrtl.
 2. Support for hierarchy paves way for simulation black boxes,
    which are necessary for e.g. replacing PHYs with C++ code that
    integrates with the host system.
2020-04-09 04:08:36 +00:00
whitequark 3376dcf37c write_cxxrtl: avoid undefined behavior on out-of-bounds memory access.
After this commit, if NDEBUG is not defined, out-of-bounds accesses
cause assertion failures for reads and writes. If NDEBUG is defined,
out-of-bounds reads return zeroes, and out-of-bounds writes are
ignored.

This commit also adds support for memories that start with a non-zero
index (`Memory::start_offset` in RTLIL).
2020-04-09 04:08:36 +00:00
whitequark 5157691f0e write_cxxrtl: statically schedule comb logic and localize wires.
This results in further massive gains in performance, modest decrease
in compile time, and, for designs without feedback arcs, makes it
possible to run eval() once per clock edge in certain conditions.
2020-04-09 04:08:36 +00:00
whitequark d6d7273421 write_cxxrtl: elide wires for results of comb cells used once.
This results in massive gains in performance, equally massive
reduction in compile time, and improved readability.
2020-04-09 04:08:36 +00:00
whitequark d20e971725 write_cxxrtl: new backend.
This commit adds a basic implementation that isn't very performant
but implements most of the planned features.
2020-04-09 04:08:36 +00:00
Sahand Kashani ac388859e3 Remove dependency on ilang backend since we no longer use it 2020-04-08 23:59:22 +02:00
Sahand Kashani 9edf8869c1 Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfo 2020-04-08 23:50:37 +02:00
Sahand Kashani 820e3d1dad Remove unnecessary pruning of double-quoting
In the past I was calling the ILANG_BACKEND::dump_const() to dump
values to an output stream. When these values were strings, the
function used to add quotes around them. The firrtl compiler, in turn,
escaped these quotes and the result was double-quoted strings which
were hard to read.

However I'm now calling design_entity->get_src_attribute() directly
and there is no additional quote being put around it, so we can
safely remove the unnecessary call to str.erase() here.
2020-04-08 23:20:56 +02:00
Alberto Gonzalez 437afa1f0c
Updated `yosys-smtbmc` to optionally dump raw bit strings, and fixed hole value recovery using that mode. 2020-04-04 22:13:25 +00:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung dde3dfd72e Update backends/btor/btor.cc; credit @boqwxp
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-04-02 07:14:08 -07:00
Eddie Hung fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
Claire Wolf d1fc4321f0
Merge pull request #1770 from YosysHQ/claire/btor_symbols
Improve write_btor symbol handling
2020-04-02 15:38:47 +02:00
Claire Wolf 104c004e6d
Merge pull request #1765 from YosysHQ/claire/btor_info
Add info-file and cover features to write_btor
2020-04-02 15:38:27 +02:00
Alberto Gonzalez c23c2c59c1
Update `RTLIL::id2cstr()` usage to `log_id`. 2020-04-01 06:53:28 +00:00
Alberto Gonzalez cdb14652be
Clean up pseudo-private member usage in `backends/intersynth/intersynth.cc`. 2020-04-01 06:32:09 +00:00
Alberto Gonzalez 24ef73904f
Clean up pseudo-private member usage in `backends/blif/blif.cc`. 2020-04-01 05:50:48 +00:00
Alberto Gonzalez f657fed24c
Clean up pseudo-private member usage in `backends/verilog/verilog_backend.cc`. 2020-04-01 05:25:10 +00:00
Alberto Gonzalez 68c0e3562e
Clean up pseudo-private member usage in `backends/spice/spice.cc`. 2020-04-01 04:56:52 +00:00
Alberto Gonzalez 057976c323
Clean up pseudo-private member usage in `backends/edif/edif.cc`. 2020-04-01 04:37:07 +00:00
Alberto Gonzalez 68fef4ca7f
Clean up pseudo-private member usage in `backends/ilang/ilang_backend.cc`. 2020-04-01 03:08:39 +00:00
Alberto Gonzalez d72cb8ea2a
Do not change solver output parsing for non-exists-forall problems. 2020-03-26 23:00:00 +00:00
Alberto Gonzalez 5accf08ef9
Skip reading stdout from the solver that if it isn't a line reading only "sat", "unsat", or "unknown". 2020-03-26 01:21:01 +00:00
Sahand Kashani 6c2b220af5 Remove use of auto for simple types + simplify src attribute computation 2020-03-24 21:07:08 +01:00
Claire Wolf c9555c9ade Revert part of 0fda8308 from #1746 that broke other smtbmc flows
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-24 17:33:46 +01:00
Sahand Kashani 018116e478 Refactor to directly call ILANG_BACKEND::dump_const() + directly lookup src attribute 2020-03-24 10:55:21 +01:00
Teguh Hofstee b08932cb81 fix typo in `write_smt2` help 2020-03-23 02:14:26 -07:00
Sahand Kashani f48fb26c0f Indentation conventions 2020-03-23 09:01:17 +01:00
Sahand Kashani-Akhavan 566e08485a
Const parameter in function (backends/firrtl/firrtl.cc)
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-03-23 08:56:28 +01:00
Sahand Kashani 21492914a2 Strip quotes around fileinfo strings
Yosys puts quotes around the string that represents the fileinfo whereas
firrtl does not. So when firrtl sees quotes, it escapes them with an extra
backslash which makes it hard to read afterwards.
2020-03-21 15:57:53 +01:00
Sahand Kashani c0b2a9af2e Add fileinfo to firrtl backend for assignments and non-instance cells 2020-03-21 12:54:23 +01:00
Sahand Kashani 3e04e29dec Refactor fileinfo emission characters to single location 2020-03-20 18:31:12 +01:00
Sahand Kashani ed9f8bfe6e Add fileinfo to firrtl backend for instances 2020-03-19 16:24:18 +01:00
Sahand Kashani 59236314f8 Add fileinfo to firrtl backend for modules and wires 2020-03-19 14:59:05 +01:00
Sahand Kashani bdce9c28c2 Add fileinfo to firrtl backend for top-level circuit 2020-03-19 00:14:27 +01:00
N. Engelhardt 020f6d167a
Merge pull request #1768 from boqwxp/smt2_cleanup
Clean up pseudo-private member usage in `backends/smt2/smt2.cc`.
2020-03-16 13:49:10 +01:00
N. Engelhardt a2e340de43
Merge pull request #1746 from boqwxp/optimization
Add support for optimizing exists-forall problems.
2020-03-16 12:23:14 +01:00
Claire Wolf bf018b184d Improve write_btor symbol handling
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-14 15:49:43 +01:00
Alberto Gonzalez 07f0874779 Clean up pseudo-private member usage in `backends/smt2/smt2.cc`. 2020-03-13 21:49:12 +00:00
Alberto Gonzalez 0fda8308bc Add support for optimizing exists-forall problems.
Modifies smt2 backend to recognize `$anyconst` etc. assigned to a wire with the `maximize` or `minimize` attribute and emit `; yosys-smt2-maximize` or `; yosys-smt2-minimize` directives as appropriate.
Modifies `backends/smt2/smtbmc.py` and `smtio.py` to recognize those directives and emit a `(maximize ...)` or `(minimize ...)` command at the end of `smt_forall_assert()`, as described in the paper "νZ - An Optimizing SMT Solver" by Nikolaj Bjørner et al.
Adds an example `examples/smtbmc/demo9.v` to show how it can be used.
2020-03-13 17:10:29 +00:00
Miodrag Milanovic 746629f18d remove include where not used 2020-03-13 14:55:53 +01:00
Claire Wolf 29e2b2dc05 Add info-file and cover features to write_btor
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-13 13:46:32 +01:00
Eddie Hung 3be7784d0e xaiger: remove some unnecessary operations ...
... since they can not be triggered by (* keep *) anymore
(but could still be triggered by (* abc9_scc *) !?!)
2020-03-06 10:51:47 -08:00
Eddie Hung 91a7a74ac4 abc9: (* keep *) wires to be PO only, not PI as well; fix scc handling 2020-03-06 10:20:30 -08:00
Eddie Hung 6bb3d9f9c0 Make TimingInfo::TimingInfo(SigBit) constructor explicit 2020-02-27 10:17:29 -08:00
Eddie Hung 5ff60d2057 write_xaiger: add comment about arrival times of flop outputs 2020-02-27 10:17:29 -08:00
Eddie Hung 1ef1ca812b Get rid of (* abc9_{arrival,required} *) entirely 2020-02-27 10:17:29 -08:00
Eddie Hung e22fee6cdd abc9_ops: ignore (* abc9_flop *) if not '-dff' 2020-02-27 10:17:29 -08:00
Eddie Hung 12d70ca8fb xilinx: improve specify functionality 2020-02-27 10:17:29 -08:00
Eddie Hung 760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve
Improve specify parser
2020-02-21 09:15:17 -08:00
Eddie Hung f9f86fd758 Revert "abc9: fix abc9_arrival for flops"
This reverts commit f7c0dbecee.
2020-02-14 16:08:04 -08:00
Eddie Hung b523ecf2f4 specify: system timing checks to accept min:typ:max triple 2020-02-13 12:42:15 -08:00
Eddie Hung f5cc8cfa79 write_xaiger: default value for abc9_init 2020-02-13 12:37:17 -08:00
Eddie Hung f7c0dbecee abc9: fix abc9_arrival for flops 2020-02-13 12:34:09 -08:00
R. Ou 20ce4118da json: Change compat mode to directly emit ints <= 32 bits
This increases compatibility with certain older parsers in some cases
that worked before commit 15fae357 but do not work with the current
compat-int mode
2020-02-09 01:01:18 -08:00
whitequark 6f67dd8df5
Merge pull request #1683 from whitequark/write_verilog-memattrs
write_verilog: dump $mem cell attributes
2020-02-07 02:54:04 +00:00
Marcin Kościelnicki 8f559b070a edif: more resilience to mismatched port connection sizes.
Fixes #1653.
2020-02-06 18:45:03 +01:00
whitequark e95a8ba763 write_verilog: dump $mem cell attributes.
The Verilog backend already dumps attributes on RTLIL::Memory objects
but not on `$mem` cells.
2020-02-06 16:22:42 +00:00
Eddie Hung 0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required
abc9: add support for required times
2020-02-05 18:59:40 +01:00
Marcin Kościelnicki 00fba62711 json: remove the 32-bit parameter special case
Before, the rules for encoding parameters in JSON were as follows:

- if the parameter is not a string:

  - if it is exactly 32 bits long and there are no z or x bits, emit it
    as an int
  - otherwise, emit it as a string made of 0/1/x/z characters

- if the parameter is a string:

  - if it contains only 0/1/x/z characters, append a space at the end
    to distinguish it from a non-string
  - otherwise, emit it directly

However, this caused a problem in the json11 parser used in nextpnr:
yosys emits unsigned ints, and nextpnr parses them as signed, using
the value of INT_MIN for values that overflow the signed int range.
This caused destruction of LUT5 initialization values.  Since both
nextpnr and yosys parser can also accept 32-bit parameters in the
same encoding as other widths, let's just remove that special case.
The old behavior is still left behind a `-compat-int` flag, in case
someone relies on it.
2020-02-01 16:16:26 +01:00
Claire Wolf 50d70288d0 Preserve wires with keep attribute in EDIF back-end
Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-29 14:07:11 +01:00
Eddie Hung 48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
Refactor `abc9` pass
2020-01-27 13:29:15 -08:00
Eddie Hung f2576c096c Merge branch 'eddie/abc9_refactor' into eddie/abc9_required 2020-01-27 12:29:28 -08:00
Claire Wolf 485f31f681 Improve yosys-smtbmc "solver not found" handling
Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-27 17:48:56 +01:00
Eddie Hung 3d9737c1bd Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-21 16:27:40 -08:00
Eddie Hung cd8f55a911 write_xaiger: fix for (* keep *) on flop output 2020-01-21 09:43:04 -08:00
Claire Wolf 30642e9570
Merge pull request #1629 from YosysHQ/mwk/edif-z
edif: Just ignore connections to 'z
2020-01-21 18:35:15 +01:00
Eddie Hung 38aa248385 Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required 2020-01-15 11:26:11 -08:00
Eddie Hung d6da9c0c0f write_xaiger: skip abc9_flop only if abc_box_seq present 2020-01-15 11:25:20 -08:00