mirror of https://github.com/YosysHQ/yosys.git
cxxrtl: fix misleading example, caution about race conditions.
Fixes #1944.
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@ -1640,21 +1640,30 @@ struct CxxrtlBackend : public Backend {
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log("\n");
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log(" write_cxxrtl [options] [filename]\n");
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log("\n");
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log("Write C++ code for simulating the design. The generated code requires a driver;\n");
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log("the following simple driver is provided as an example:\n");
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log("Write C++ code for simulating the design. The generated code requires a driver\n");
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log("that instantiates the design, toggles its clock, and interacts with its ports.\n");
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log("\n");
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log("The following driver may be used as an example for a design with a single clock\n");
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log("driving rising edge triggered flip-flops:\n");
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log("\n");
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log(" #include \"top.cc\"\n");
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log("\n");
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log(" int main() {\n");
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log(" cxxrtl_design::p_top top;\n");
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log(" top.step();\n");
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log(" while (1) {\n");
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log(" top.p_clk.next = value<1> {1u};\n");
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log(" top.step();\n");
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log(" /* user logic */\n");
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log(" top.p_clk.next = value<1> {0u};\n");
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log(" top.step();\n");
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log(" top.p_clk.next = value<1> {1u};\n");
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log(" top.step();\n");
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log(" }\n");
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log(" }\n");
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log("\n");
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log("Note that CXXRTL simulations, just like the hardware they are simulating, are\n");
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log("subject to race conditions. If, in then example above, the user logic would run\n");
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log("simultaneously with the rising edge of the clock, the design would malfunction.\n");
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log("\n");
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log("The following options are supported by this backend:\n");
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log("\n");
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log(" -header\n");
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