mirror of https://github.com/YosysHQ/yosys.git
Ignore conflicting keep attributes, unless asked not to. Fixes #1733
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
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ae115fa3aa
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ee5067e864
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@ -113,6 +113,9 @@ struct EdifBackend : public Backend {
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log(" -attrprop\n");
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log(" create EDIF properties for cell attributes\n");
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log("\n");
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log(" -keep\n");
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log(" create extra KEEP nets by allowing a cell to drive multiple nets.\n");
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log("\n");
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log(" -pvector {par|bra|ang}\n");
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log(" sets the delimiting character for module port rename clauses to\n");
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log(" parentheses, square brackets, or angle brackets.\n");
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@ -130,7 +133,7 @@ struct EdifBackend : public Backend {
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bool port_rename = false;
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bool attr_properties = false;
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std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
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bool nogndvcc = false, gndvccy = false;
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bool nogndvcc = false, gndvccy = false, keepmode = false;
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CellTypes ct(design);
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EdifNames edif_names;
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@ -153,6 +156,10 @@ struct EdifBackend : public Backend {
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attr_properties = true;
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continue;
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}
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if (args[argidx] == "-keep") {
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keepmode = true;
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continue;
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}
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if (args[argidx] == "-pvector" && argidx+1 < args.size()) {
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std::string parray;
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port_rename = true;
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@ -337,6 +344,7 @@ struct EdifBackend : public Backend {
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*f << stringf(" (view VIEW_NETLIST\n");
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*f << stringf(" (viewType NETLIST)\n");
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*f << stringf(" (interface\n");
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for (auto wire : module->wires()) {
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if (wire->port_id == 0)
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continue;
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@ -369,12 +377,15 @@ struct EdifBackend : public Backend {
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}
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}
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}
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*f << stringf(" )\n");
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*f << stringf(" (contents\n");
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if (!nogndvcc) {
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*f << stringf(" (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
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*f << stringf(" (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
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}
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for (auto cell : module->cells()) {
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*f << stringf(" (instance %s\n", EDIF_DEF(cell->name));
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*f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
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@ -412,6 +423,7 @@ struct EdifBackend : public Backend {
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}
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}
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}
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for (auto &it : net_join_db) {
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RTLIL::SigBit sig = it.first;
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if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) {
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@ -440,7 +452,7 @@ struct EdifBackend : public Backend {
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}
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*f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
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for (auto &ref : it.second)
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*f << stringf(" %s\n", ref.first.c_str());
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*f << stringf(" %s\n", ref.first.c_str());
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if (sig.wire == NULL) {
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if (nogndvcc)
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log_error("Design contains constant nodes (map with \"hilomap\" first).\n");
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@ -455,30 +467,48 @@ struct EdifBackend : public Backend {
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add_prop(p.first, p.second);
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*f << stringf("\n )\n");
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}
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for (auto wire : module->wires()) {
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for (auto wire : module->wires())
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{
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if (!wire->get_bool_attribute(ID::keep))
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continue;
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for(int i = 0; i < wire->width; i++) {
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for(int i = 0; i < wire->width; i++)
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{
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SigBit raw_sig = RTLIL::SigSpec(wire, i);
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SigBit mapped_sig = sigmap(raw_sig);
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if (raw_sig == mapped_sig || net_join_db.count(mapped_sig) == 0)
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continue;
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std::string netname = log_signal(raw_sig);
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for (size_t i = 0; i < netname.size(); i++)
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if (netname[i] == ' ' || netname[i] == '\\')
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netname.erase(netname.begin() + i--);
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*f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
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auto &refs = net_join_db.at(mapped_sig);
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for (auto &ref : refs)
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if (ref.second)
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*f << stringf(" %s\n", ref.first.c_str());
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*f << stringf(" )");
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if (attr_properties && raw_sig.wire != NULL)
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for (auto &p : raw_sig.wire->attributes)
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add_prop(p.first, p.second);
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*f << stringf("\n )\n");
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if (keepmode)
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{
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*f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
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auto &refs = net_join_db.at(mapped_sig);
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for (auto &ref : refs)
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if (ref.second)
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*f << stringf(" %s\n", ref.first.c_str());
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*f << stringf(" )");
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if (attr_properties && raw_sig.wire != NULL)
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for (auto &p : raw_sig.wire->attributes)
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add_prop(p.first, p.second);
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*f << stringf("\n )\n");
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}
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else
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{
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log_warning("Ignoring conflicting 'keep' property on net %s. Use -keep to generate the extra net nevertheless.\n", EDIF_DEF(netname));
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}
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}
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}
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*f << stringf(" )\n");
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*f << stringf(" )\n");
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*f << stringf(" )\n");
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