mirror of https://github.com/YosysHQ/yosys.git
write_cxxrtl: add support for $dlatch and $dlatchsr cells.
Also, fix codegen for $dffe and $adff.
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@ -202,7 +202,7 @@ static bool is_sync_ff_cell(RTLIL::IdString type)
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static bool is_ff_cell(RTLIL::IdString type)
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{
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return is_sync_ff_cell(type) || type.in(
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ID($adff), ID($dffsr), ID($sr));
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ID($adff), ID($dffsr), ID($dlatch), ID($dlatchsr), ID($sr));
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}
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static bool is_internal_cell(RTLIL::IdString type)
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@ -786,7 +786,7 @@ struct CxxrtlWorker {
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if (cell->type == ID($dffe)) {
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f << indent << "if (";
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dump_sigspec_rhs(cell->getPort(ID(EN)));
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f << " == value<1> {" << cell->getParam(ID(EN_POLARITY)).as_bool() << "}) {\n";
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f << " == value<1> {" << cell->getParam(ID(EN_POLARITY)).as_bool() << "u}) {\n";
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inc_indent();
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}
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f << indent;
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@ -800,12 +800,25 @@ struct CxxrtlWorker {
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}
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dec_indent();
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f << indent << "}\n";
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} else if (cell->hasPort(ID(EN))) {
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// Level-sensitive logic
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f << indent << "if (";
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dump_sigspec_rhs(cell->getPort(ID(EN)));
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f << " == value<1> {" << cell->getParam(ID(EN_POLARITY)).as_bool() << "u}) {\n";
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inc_indent();
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f << indent;
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dump_sigspec_lhs(cell->getPort(ID(Q)));
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f << " = ";
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dump_sigspec_rhs(cell->getPort(ID(D)));
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f << ";\n";
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dec_indent();
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f << indent << "}\n";
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}
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if (cell->hasPort(ID(ARST))) {
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// Asynchronous reset (entire coarse cell at once)
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f << indent << "if (";
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dump_sigspec_rhs(cell->getPort(ID(ARST)));
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f << " == value<1> {" << cell->getParam(ID(ARST_POLARITY)).as_bool() << "}) {\n";
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f << " == value<1> {" << cell->getParam(ID(ARST_POLARITY)).as_bool() << "u}) {\n";
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inc_indent();
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f << indent;
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dump_sigspec_lhs(cell->getPort(ID(Q)));
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