mirror of https://github.com/YosysHQ/yosys.git
cxxrtl: Fix handling of unclocked memory read ports
Signed-off-by: David Shah <dave@ds0.me>
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7a36728b2f
commit
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@ -871,7 +871,8 @@ struct CxxrtlWorker {
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dump_sigspec_rhs(cell->getPort(ID(ADDR)));
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f << ", " << memory->start_offset << ", " << memory->size << ");\n";
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if (cell->type == ID($memrd)) {
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if (!cell->getPort(ID(EN)).is_fully_ones()) {
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bool has_enable = cell->getParam(ID(CLK_ENABLE)).as_bool() && !cell->getPort(ID(EN)).is_fully_ones();
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if (has_enable) {
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f << indent << "if (";
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dump_sigspec_rhs(cell->getPort(ID(EN)));
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f << ") {\n";
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@ -930,7 +931,7 @@ struct CxxrtlWorker {
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f << " = value<" << memory->width << "> {};\n";
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dec_indent();
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f << indent << "}\n";
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if (!cell->getPort(ID(EN)).is_fully_ones()) {
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if (has_enable) {
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dec_indent();
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f << indent << "}\n";
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}
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