mirror of https://github.com/YosysHQ/yosys.git
write_cxxrtl: elide wires for results of comb cells used once.
This results in massive gains in performance, equally massive reduction in compile time, and improved readability.
This commit is contained in:
whitequark
parent
d20e971725
commit
d6d7273421
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@ -26,7 +26,175 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static bool is_unary_cell(RTLIL::IdString type)
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{
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return type.in(
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ID($not), ID($logic_not), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
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ID($pos), ID($neg));
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}
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static bool is_binary_cell(RTLIL::IdString type)
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{
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return type.in(
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ID($and), ID($or), ID($xor), ID($xnor), ID($logic_and), ID($logic_or),
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ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
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ID($eq), ID($ne), ID($eqx), ID($nex), ID($gt), ID($ge), ID($lt), ID($le),
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ID($add), ID($sub), ID($mul), ID($div), ID($mod));
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}
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static bool is_elidable_cell(RTLIL::IdString type)
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{
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return is_unary_cell(type) || is_binary_cell(type) || type == ID($mux);
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}
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static bool is_ff_cell(RTLIL::IdString type)
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{
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return type.in(
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ID($dff), ID($dffe), ID($adff), ID($dffsr));
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}
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struct FlowGraph {
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struct Node {
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enum class Type {
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CONNECT,
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CELL,
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PROCESS
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};
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Type type;
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RTLIL::SigSig connect = {};
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const RTLIL::Cell *cell = NULL;
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const RTLIL::Process *process = NULL;
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};
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std::vector<Node*> nodes;
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dict<const RTLIL::Wire*, pool<Node*, hash_ptr_ops>> wire_defs, wire_uses;
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dict<const RTLIL::Wire*, bool> wire_def_elidable, wire_use_elidable;
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~FlowGraph()
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{
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for (auto node : nodes)
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delete node;
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}
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void add_defs(Node *node, const RTLIL::SigSpec &sig, bool elidable)
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{
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for (auto chunk : sig.chunks())
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if (chunk.wire)
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wire_defs[chunk.wire].insert(node);
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// Only defs of an entire wire in the right order can be elided.
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if (sig.is_wire())
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wire_def_elidable[sig.as_wire()] = elidable;
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}
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void add_uses(Node *node, const RTLIL::SigSpec &sig)
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{
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for (auto chunk : sig.chunks())
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if (chunk.wire) {
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wire_uses[chunk.wire].insert(node);
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// Only a single use of an entire wire in the right order can be elided.
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// (But the use can include other chunks.)
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if (!wire_use_elidable.count(chunk.wire))
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wire_use_elidable[chunk.wire] = true;
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else
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wire_use_elidable[chunk.wire] = false;
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}
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}
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bool is_elidable(const RTLIL::Wire *wire) const
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{
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if (wire_def_elidable.count(wire) && wire_use_elidable.count(wire))
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return wire_def_elidable.at(wire) && wire_use_elidable.at(wire);
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return false;
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}
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// Connections
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void add_connect_defs_uses(Node *node, const RTLIL::SigSig &conn)
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{
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add_defs(node, conn.first, /*elidable=*/true);
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add_uses(node, conn.second);
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}
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void add_node(const RTLIL::SigSig &conn)
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{
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Node *node = new Node;
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node->type = Node::Type::CONNECT;
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node->connect = conn;
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nodes.push_back(node);
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add_connect_defs_uses(node, conn);
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}
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// Cells
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void add_cell_defs_uses(Node *node, const RTLIL::Cell *cell)
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{
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log_assert(cell->known());
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for (auto conn : cell->connections()) {
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if (cell->output(conn.first)) {
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if (is_ff_cell(cell->type))
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/* non-combinatorial outputs do not introduce defs */;
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else if (is_elidable_cell(cell->type))
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add_defs(node, conn.second, /*elidable=*/true);
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else
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add_defs(node, conn.second, /*elidable=*/false);
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}
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if (cell->input(conn.first))
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add_uses(node, conn.second);
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}
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}
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void add_node(const RTLIL::Cell *cell)
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{
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Node *node = new Node;
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node->type = Node::Type::CELL;
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node->cell = cell;
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nodes.push_back(node);
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add_cell_defs_uses(node, cell);
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}
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// Processes
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void add_case_defs_uses(Node *node, const RTLIL::CaseRule *case_)
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{
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for (auto &action : case_->actions) {
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add_defs(node, action.first, /*elidable=*/false);
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add_uses(node, action.second);
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}
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for (auto sub_switch : case_->switches) {
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add_uses(node, sub_switch->signal);
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for (auto sub_case : sub_switch->cases) {
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for (auto &compare : sub_case->compare)
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add_uses(node, compare);
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add_case_defs_uses(node, sub_case);
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}
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}
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}
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void add_process_defs_uses(Node *node, const RTLIL::Process *process)
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{
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add_case_defs_uses(node, &process->root_case);
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for (auto sync : process->syncs)
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for (auto action : sync->actions) {
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if (sync->type == RTLIL::STp || sync->type == RTLIL::STn || sync->type == RTLIL::STe)
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/* sync actions do not introduce feedback */;
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else
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add_defs(node, action.first, /*elidable=*/false);
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add_uses(node, action.second);
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}
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}
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void add_node(const RTLIL::Process *process)
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{
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Node *node = new Node;
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node->type = Node::Type::PROCESS;
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node->process = process;
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nodes.push_back(node);
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add_process_defs_uses(node, process);
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}
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};
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struct CxxrtlWorker {
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bool elide_internal = false;
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bool elide_public = false;
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std::ostream &f;
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std::string indent;
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int temporary = 0;
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@ -35,6 +203,7 @@ struct CxxrtlWorker {
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pool<const RTLIL::Wire*> sync_wires;
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dict<RTLIL::SigBit, RTLIL::SyncType> sync_types;
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pool<const RTLIL::Memory*> writable_memories;
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dict<const RTLIL::Wire*, FlowGraph::Node> elided_wires;
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CxxrtlWorker(std::ostream &f) : f(f) {}
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@ -183,7 +352,21 @@ struct CxxrtlWorker {
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dump_const(chunk.data, chunk.width, chunk.offset);
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return false;
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} else {
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f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr");
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if (!is_lhs && elided_wires.count(chunk.wire)) {
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const FlowGraph::Node &node = elided_wires[chunk.wire];
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switch (node.type) {
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case FlowGraph::Node::Type::CONNECT:
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dump_connect_elided(node.connect);
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break;
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case FlowGraph::Node::Type::CELL:
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dump_cell_elided(node.cell);
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break;
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default:
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log_assert(false);
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}
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} else {
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f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr");
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}
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if (chunk.width == chunk.wire->width && chunk.offset == 0)
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return false;
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else if (chunk.width == 1)
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@ -228,56 +411,134 @@ struct CxxrtlWorker {
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f << ".val()";
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}
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void dump_assign(const RTLIL::SigSig &sigsig)
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void collect_sigspec_rhs(const RTLIL::SigSpec &sig, std::vector<RTLIL::IdString> &cells)
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{
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for (auto chunk : sig.chunks()) {
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if (!chunk.wire || !elided_wires.count(chunk.wire))
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continue;
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const FlowGraph::Node &node = elided_wires[chunk.wire];
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switch (node.type) {
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case FlowGraph::Node::Type::CONNECT:
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collect_connect(node.connect, cells);
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break;
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case FlowGraph::Node::Type::CELL:
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collect_cell(node.cell, cells);
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break;
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default:
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log_assert(false);
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}
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}
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}
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void dump_connect_elided(const RTLIL::SigSig &conn)
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{
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dump_sigspec_rhs(conn.second);
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}
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bool is_connect_elided(const RTLIL::SigSig &conn)
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{
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return conn.first.is_wire() && elided_wires.count(conn.first.as_wire());
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}
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void collect_connect(const RTLIL::SigSig &conn, std::vector<RTLIL::IdString> &cells)
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{
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if (!is_connect_elided(conn))
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return;
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collect_sigspec_rhs(conn.second, cells);
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}
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void dump_connect(const RTLIL::SigSig &conn)
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{
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if (is_connect_elided(conn))
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return;
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f << indent;
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dump_sigspec_lhs(sigsig.first);
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dump_sigspec_lhs(conn.first);
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f << " = ";
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dump_sigspec_rhs(sigsig.second);
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dump_connect_elided(conn);
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f << ";\n";
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}
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void dump_cell(const RTLIL::Cell *cell)
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void dump_cell_elided(const RTLIL::Cell *cell)
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{
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dump_attrs(cell);
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f << indent << "// cell " << cell->name.str() << "\n";
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// Unary cells
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if (cell->type.in(
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ID($not), ID($logic_not), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
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ID($pos), ID($neg))) {
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f << indent;
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dump_sigspec_lhs(cell->getPort(ID(Y)));
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f << " = " << cell->type.substr(1) << '_' <<
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if (is_unary_cell(cell->type)) {
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f << cell->type.substr(1) << '_' <<
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(cell->getParam(ID(A_SIGNED)).as_bool() ? 's' : 'u') <<
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"<" << cell->getParam(ID(Y_WIDTH)).as_int() << ">(";
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dump_sigspec_rhs(cell->getPort(ID(A)));
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f << ");\n";
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f << ")";
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// Binary cells
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} else if (cell->type.in(
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ID($and), ID($or), ID($xor), ID($xnor), ID($logic_and), ID($logic_or),
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ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
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ID($eq), ID($ne), ID($eqx), ID($nex), ID($gt), ID($ge), ID($lt), ID($le),
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ID($add), ID($sub), ID($mul), ID($div), ID($mod))) {
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f << indent;
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dump_sigspec_lhs(cell->getPort(ID(Y)));
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f << " = " << cell->type.substr(1) << '_' <<
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} else if (is_binary_cell(cell->type)) {
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f << cell->type.substr(1) << '_' <<
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(cell->getParam(ID(A_SIGNED)).as_bool() ? 's' : 'u') <<
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(cell->getParam(ID(B_SIGNED)).as_bool() ? 's' : 'u') <<
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"<" << cell->getParam(ID(Y_WIDTH)).as_int() << ">(";
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dump_sigspec_rhs(cell->getPort(ID(A)));
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f << ", ";
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dump_sigspec_rhs(cell->getPort(ID(B)));
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f << ");\n";
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f << ")";
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// Muxes
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} else if (cell->type == ID($mux)) {
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f << indent;
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dump_sigspec_lhs(cell->getPort(ID(Y)));
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f << " = ";
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f << "(";
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dump_sigspec_rhs(cell->getPort(ID(S)));
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f << " ? ";
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dump_sigspec_rhs(cell->getPort(ID(B)));
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f << " : ";
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dump_sigspec_rhs(cell->getPort(ID(A)));
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f << ")";
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} else {
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log_assert(false);
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}
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}
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bool is_cell_elided(const RTLIL::Cell *cell)
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{
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return cell->hasPort(ID(Y)) && cell->getPort(ID(Y)).is_wire() && elided_wires.count(cell->getPort(ID(Y)).as_wire());
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}
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void collect_cell(const RTLIL::Cell *cell, std::vector<RTLIL::IdString> &cells)
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{
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if (!is_cell_elided(cell))
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return;
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cells.push_back(cell->name);
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for (auto port : cell->connections())
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if (port.first != ID(Y))
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collect_sigspec_rhs(port.second, cells);
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}
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void dump_cell(const RTLIL::Cell *cell)
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{
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if (is_cell_elided(cell))
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return;
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if (cell->type == ID($meminit))
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return; // Handled elsewhere.
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std::vector<RTLIL::IdString> elided_cells;
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if (is_elidable_cell(cell->type)) {
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for (auto port : cell->connections())
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if (port.first != ID(Y))
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collect_sigspec_rhs(port.second, elided_cells);
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}
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if (elided_cells.empty()) {
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dump_attrs(cell);
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f << indent << "// cell " << cell->name.str() << "\n";
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} else {
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f << indent << "// cells";
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for (auto elided_cell : elided_cells)
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f << " " << elided_cell.str();
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f << "\n";
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}
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// Elidable cells
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if (is_elidable_cell(cell->type)) {
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f << indent;
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dump_sigspec_lhs(cell->getPort(ID(Y)));
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f << " = ";
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dump_cell_elided(cell);
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f << ";\n";
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// Parallel (one-hot) muxes
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} else if (cell->type == ID($pmux)) {
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@ -309,7 +570,7 @@ struct CxxrtlWorker {
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dec_indent();
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f << indent << "}\n";
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// Flip-flops
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} else if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($dffsr))) {
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} else if (is_ff_cell(cell->type)) {
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if (cell->getPort(ID(CLK)).is_wire()) {
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// Edge-sensitive logic
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RTLIL::SigBit clk_bit = cell->getPort(ID(CLK))[0];
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@ -437,8 +698,6 @@ struct CxxrtlWorker {
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f << indent << "}\n";
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}
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// Memory initializers
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} else if (cell->type == ID($meminit)) {
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// Handled elsewhere.
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} else if (cell->type[0] == '$') {
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log_cmd_error("Unsupported internal cell `%s'.\n", cell->type.c_str());
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} else {
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@ -446,6 +705,15 @@ struct CxxrtlWorker {
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}
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}
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void dump_assign(const RTLIL::SigSig &sigsig)
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{
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f << indent;
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dump_sigspec_lhs(sigsig.first);
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f << " = ";
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dump_sigspec_rhs(sigsig.second);
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f << ";\n";
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}
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void dump_case_rule(const RTLIL::CaseRule *rule)
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{
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for (auto action : rule->actions)
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@ -571,6 +839,9 @@ struct CxxrtlWorker {
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void dump_wire(const RTLIL::Wire *wire)
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{
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if (elided_wires.count(wire))
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return;
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dump_attrs(wire);
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f << indent << "wire<" << wire->width << "> " << mangle(wire);
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if (wire->attributes.count(ID(init))) {
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@ -661,7 +932,7 @@ struct CxxrtlWorker {
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dump_cell(cell);
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f << indent << "// connections\n";
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for (auto conn : module->connections())
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dump_assign(conn);
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dump_connect(conn);
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for (auto proc : module->processes)
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dump_process(proc.second);
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for (auto sync_type : sync_types) {
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@ -680,6 +951,8 @@ struct CxxrtlWorker {
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inc_indent();
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f << indent << "bool changed = false;\n";
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for (auto wire : module->wires()) {
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if (elided_wires.count(wire))
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continue;
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if (sync_wires[wire]) {
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std::string wire_prev = mangle(wire) + "_prev";
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std::string wire_curr = mangle(wire) + ".curr";
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@ -773,10 +1046,16 @@ struct CxxrtlWorker {
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void analyze_design(RTLIL::Design *design)
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{
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for (auto module : design->modules()) {
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FlowGraph flow;
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SigMap &sigmap = sigmaps[module];
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sigmap.set(module);
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for (auto conn : module->connections())
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flow.add_node(conn);
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for (auto cell : module->cells()) {
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flow.add_node(cell);
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// Various DFF cells are treated like posedge/negedge processes, see above for details.
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if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($dffsr))) {
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if (cell->getPort(ID(CLK)).is_wire())
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|
|
@ -802,7 +1081,9 @@ struct CxxrtlWorker {
|
|||
log_assert(false);
|
||||
}
|
||||
|
||||
for (auto proc : module->processes)
|
||||
for (auto proc : module->processes) {
|
||||
flow.add_node(proc.second);
|
||||
|
||||
for (auto sync : proc.second->syncs)
|
||||
switch (sync->type) {
|
||||
// Edge-type sync rules require pre-registration.
|
||||
|
|
@ -826,6 +1107,18 @@ struct CxxrtlWorker {
|
|||
case RTLIL::STg:
|
||||
log_cmd_error("Global clock is not supported.\n");
|
||||
}
|
||||
}
|
||||
|
||||
for (auto wire : module->wires()) {
|
||||
if (!flow.is_elidable(wire)) continue;
|
||||
if (wire->port_id != 0) continue;
|
||||
if (wire->get_bool_attribute(ID(keep))) continue;
|
||||
if (wire->name.begins_with("$") && !elide_internal) continue;
|
||||
if (wire->name.begins_with("\\") && !elide_public) continue;
|
||||
if (sync_wires[wire]) continue;
|
||||
log_assert(flow.wire_defs[wire].size() == 1);
|
||||
elided_wires[wire] = **flow.wire_defs[wire].begin();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -879,23 +1172,54 @@ struct CxxrtlBackend : public Backend {
|
|||
log("\n");
|
||||
log("Write C++ code for simulating the design.\n");
|
||||
log("\n");
|
||||
// -O2 (and not -O1) is the default because wire elision results in dramatic (>10x) decrease in compile- and run-time,
|
||||
// which is well worth the need to manually drop to -O1 or to mark interesting wires with (*keep*).
|
||||
log(" -O <level>\n");
|
||||
log(" set the optimization level. the default is -O2.\n");
|
||||
log("\n");
|
||||
log(" -O0\n");
|
||||
log(" no optimization.\n");
|
||||
log("\n");
|
||||
log(" -O1\n");
|
||||
log(" elide internal wires if possible.\n");
|
||||
log("\n");
|
||||
log(" -O2\n");
|
||||
log(" like -O1, and elide public wires not marked (*keep*) if possible.\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
int opt_level = 2;
|
||||
|
||||
log_header(design, "Executing CXXRTL backend.\n");
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
{
|
||||
// if (args[argidx] == "-top" && argidx+1 < args.size()) {
|
||||
// top_module_name = args[++argidx];
|
||||
// continue;
|
||||
// }
|
||||
if (args[argidx] == "-O" && argidx+1 < args.size()) {
|
||||
opt_level = std::stoi(args[++argidx]);
|
||||
continue;
|
||||
}
|
||||
if (args[argidx].substr(0, 2) == "-O" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
|
||||
opt_level = std::stoi(args[argidx].substr(2));
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(f, filename, args, argidx);
|
||||
|
||||
CxxrtlWorker worker(*f);
|
||||
switch (opt_level) {
|
||||
case 2:
|
||||
worker.elide_public = true;
|
||||
case 1:
|
||||
worker.elide_internal = true;
|
||||
case 0:
|
||||
break;
|
||||
default:
|
||||
log_cmd_error("Invalid optimization level %d.\n", opt_level);
|
||||
}
|
||||
|
||||
worker.prepare_design(design);
|
||||
worker.dump_design(design);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue