2013-01-05 04:13:26 -06:00
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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2021-06-07 17:39:36 -05:00
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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2015-07-02 04:14:30 -05:00
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*
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2013-01-05 04:13:26 -06:00
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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2015-07-02 04:14:30 -05:00
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*
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2013-01-05 04:13:26 -06:00
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* This is the AST frontend library.
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*
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* The AST frontend library is not a frontend on it's own but provides a
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* generic abstract syntax tree (AST) abstraction for HDL code and can be
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* used by HDL frontends. See "ast.h" for an overview of the API and the
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* Verilog frontend for an usage example.
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*
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*/
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#include "kernel/log.h"
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2013-02-27 02:32:19 -06:00
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#include "libs/sha1/sha1.h"
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2014-10-26 14:33:10 -05:00
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#include "frontends/verilog/verilog_frontend.h"
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2013-01-05 04:13:26 -06:00
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#include "ast.h"
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#include <sstream>
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#include <stdarg.h>
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2014-10-26 14:33:10 -05:00
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#include <stdlib.h>
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2014-06-14 01:51:22 -05:00
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#include <math.h>
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2023-08-04 16:45:47 -05:00
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// For std::gcd in C++17
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// #include <numeric>
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2013-01-05 04:13:26 -06:00
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2014-07-31 06:19:47 -05:00
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YOSYS_NAMESPACE_BEGIN
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2013-01-05 04:13:26 -06:00
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using namespace AST;
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using namespace AST_INTERNAL;
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2023-08-04 16:45:47 -05:00
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// gcd computed by Euclidian division.
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// To be replaced by C++17 std::gcd
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template<class I> I gcd(I a, I b) {
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while (b != 0) {
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I tmp = b;
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b = a%b;
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a = tmp;
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}
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return std::abs(a);
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}
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2023-04-05 04:00:07 -05:00
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void AstNode::set_in_lvalue_flag(bool flag, bool no_descend)
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{
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if (flag != in_lvalue_from_above) {
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in_lvalue_from_above = flag;
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if (!no_descend)
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fixup_hierarchy_flags();
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}
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}
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void AstNode::set_in_param_flag(bool flag, bool no_descend)
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{
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if (flag != in_param_from_above) {
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in_param_from_above = flag;
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if (!no_descend)
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fixup_hierarchy_flags();
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}
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}
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void AstNode::fixup_hierarchy_flags(bool force_descend)
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{
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// With forced descend, we disable the implicit
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// descend from within the set_* functions, instead
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// we do an explicit descend at the end of this function
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in_param = in_param_from_above;
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switch (type) {
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case AST_PARAMETER:
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case AST_LOCALPARAM:
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case AST_DEFPARAM:
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case AST_PARASET:
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case AST_PREFIX:
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in_param = true;
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for (auto child : children)
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child->set_in_param_flag(true, force_descend);
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break;
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case AST_REPLICATE:
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case AST_WIRE:
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case AST_GENIF:
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case AST_GENCASE:
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for (auto child : children)
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child->set_in_param_flag(in_param, force_descend);
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if (children.size() >= 1)
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children[0]->set_in_param_flag(true, force_descend);
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break;
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case AST_GENFOR:
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case AST_FOR:
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for (auto child : children)
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child->set_in_param_flag(in_param, force_descend);
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if (children.size() >= 2)
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children[1]->set_in_param_flag(true, force_descend);
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break;
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default:
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in_param = in_param_from_above;
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for (auto child : children)
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child->set_in_param_flag(in_param, force_descend);
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}
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for (auto attr : attributes)
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attr.second->set_in_param_flag(true, force_descend);
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in_lvalue = in_lvalue_from_above;
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switch (type) {
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case AST_ASSIGN:
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case AST_ASSIGN_EQ:
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case AST_ASSIGN_LE:
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if (children.size() >= 1)
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children[0]->set_in_lvalue_flag(true, force_descend);
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if (children.size() >= 2)
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children[1]->set_in_lvalue_flag(in_lvalue, force_descend);
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break;
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default:
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for (auto child : children)
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child->set_in_lvalue_flag(in_lvalue, force_descend);
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}
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if (force_descend) {
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for (auto child : children)
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child->fixup_hierarchy_flags(true);
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for (auto attr : attributes)
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attr.second->fixup_hierarchy_flags(true);
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}
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}
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2020-01-19 15:15:51 -06:00
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// Process a format string and arguments for $display, $write, $sprintf, etc
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2023-09-22 10:56:34 -05:00
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Fmt AstNode::processFormat(int stage, bool sformat_like, int default_base, size_t first_arg_at, bool may_fail) {
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2020-11-29 02:57:07 -06:00
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std::vector<VerilogFmtArg> args;
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for (size_t index = first_arg_at; index < children.size(); index++) {
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AstNode *node_arg = children[index];
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2023-04-04 15:59:44 -05:00
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while (node_arg->simplify(true, stage, -1, false)) { }
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2020-11-29 02:57:07 -06:00
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VerilogFmtArg arg = {};
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arg.filename = filename;
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arg.first_line = location.first_line;
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2023-06-27 20:51:22 -05:00
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if (node_arg->type == AST_CONSTANT && node_arg->is_string) {
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2020-11-29 02:57:07 -06:00
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arg.type = VerilogFmtArg::STRING;
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arg.str = node_arg->bitsAsConst().decode_string();
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// and in case this will be used as an argument...
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arg.sig = node_arg->bitsAsConst();
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arg.signed_ = false;
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2023-06-27 20:51:22 -05:00
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} else if (node_arg->type == AST_IDENTIFIER && node_arg->str == "$time") {
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arg.type = VerilogFmtArg::TIME;
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} else if (node_arg->type == AST_IDENTIFIER && node_arg->str == "$realtime") {
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arg.type = VerilogFmtArg::TIME;
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arg.realtime = true;
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} else if (node_arg->type == AST_CONSTANT) {
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2020-11-29 02:57:07 -06:00
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arg.type = VerilogFmtArg::INTEGER;
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arg.sig = node_arg->bitsAsConst();
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arg.signed_ = node_arg->is_signed;
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2023-09-22 10:56:34 -05:00
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} else if (may_fail) {
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log_file_info(filename, location.first_line, "Skipping system task `%s' with non-constant argument at position %zu.\n", str.c_str(), index + 1);
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return Fmt();
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2023-06-27 20:51:22 -05:00
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} else {
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log_file_error(filename, location.first_line, "Failed to evaluate system task `%s' with non-constant argument at position %zu.\n", str.c_str(), index + 1);
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2020-01-19 15:15:51 -06:00
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}
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2020-11-29 02:57:07 -06:00
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args.push_back(arg);
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2020-01-19 15:15:51 -06:00
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}
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2024-01-11 03:39:28 -06:00
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Fmt fmt;
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2020-11-29 02:57:07 -06:00
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fmt.parse_verilog(args, sformat_like, default_base, /*task_name=*/str, current_module->name);
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return fmt;
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}
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2020-01-19 15:15:51 -06:00
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2020-05-08 08:40:49 -05:00
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void AstNode::annotateTypedEnums(AstNode *template_node)
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{
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//check if enum
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if (template_node->attributes.count(ID::enum_type)) {
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//get reference to enum node:
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std::string enum_type = template_node->attributes[ID::enum_type]->str.c_str();
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// log("enum_type=%s (count=%lu)\n", enum_type.c_str(), current_scope.count(enum_type));
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// log("current scope:\n");
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// for (auto &it : current_scope)
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// log(" %s\n", it.first.c_str());
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log_assert(current_scope.count(enum_type) == 1);
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AstNode *enum_node = current_scope.at(enum_type);
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log_assert(enum_node->type == AST_ENUM);
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2023-04-04 15:59:44 -05:00
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while (enum_node->simplify(true, 1, -1, false)) { }
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2020-05-08 08:40:49 -05:00
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//get width from 1st enum item:
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log_assert(enum_node->children.size() >= 1);
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AstNode *enum_item0 = enum_node->children[0];
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log_assert(enum_item0->type == AST_ENUM_ITEM);
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int width;
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if (!enum_item0->range_valid)
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width = 1;
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else if (enum_item0->range_swapped)
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width = enum_item0->range_right - enum_item0->range_left + 1;
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else
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width = enum_item0->range_left - enum_item0->range_right + 1;
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log_assert(width > 0);
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//add declared enum items:
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for (auto enum_item : enum_node->children){
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log_assert(enum_item->type == AST_ENUM_ITEM);
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//get is_signed
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bool is_signed;
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if (enum_item->children.size() == 1){
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is_signed = false;
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} else if (enum_item->children.size() == 2){
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log_assert(enum_item->children[1]->type == AST_RANGE);
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is_signed = enum_item->children[1]->is_signed;
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} else {
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2023-11-11 08:29:43 -06:00
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log_error("enum_item children size==%zu, expected 1 or 2 for %s (%s)\n",
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(size_t) enum_item->children.size(),
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2020-05-08 08:40:49 -05:00
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enum_item->str.c_str(), enum_node->str.c_str()
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);
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}
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//start building attribute string
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std::string enum_item_str = "\\enum_value_";
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//get enum item value
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if(enum_item->children[0]->type != AST_CONSTANT){
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log_error("expected const, got %s for %s (%s)\n",
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type2str(enum_item->children[0]->type).c_str(),
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enum_item->str.c_str(), enum_node->str.c_str()
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);
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}
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RTLIL::Const val = enum_item->children[0]->bitsAsConst(width, is_signed);
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enum_item_str.append(val.as_string());
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//set attribute for available val to enum item name mappings
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2023-04-05 04:00:07 -05:00
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set_attribute(enum_item_str.c_str(), mkconst_str(enum_item->str));
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2020-05-08 08:40:49 -05:00
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}
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}
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}
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static AstNode *make_range(int left, int right, bool is_signed = false)
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{
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// generate a pre-validated range node for a fixed signal range.
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auto range = new AstNode(AST_RANGE);
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range->range_left = left;
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range->range_right = right;
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range->range_valid = true;
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range->children.push_back(AstNode::mkconst_int(left, true));
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range->children.push_back(AstNode::mkconst_int(right, true));
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range->is_signed = is_signed;
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return range;
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}
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2020-06-07 12:28:45 -05:00
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static int range_width(AstNode *node, AstNode *rnode)
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{
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log_assert(rnode->type==AST_RANGE);
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if (!rnode->range_valid) {
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2024-01-25 00:28:15 -06:00
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node->input_error("Non-constant range in declaration of %s\n", node->str.c_str());
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2020-06-07 12:28:45 -05:00
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}
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// note: range swapping has already been checked for
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return rnode->range_left - rnode->range_right + 1;
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}
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2024-01-25 00:28:15 -06:00
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static int add_dimension(AstNode *node, AstNode *rnode)
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2022-11-12 01:48:25 -06:00
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{
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2024-01-25 00:28:15 -06:00
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int width = range_width(node, rnode);
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node->dimensions.push_back({ rnode->range_right, width, rnode->range_swapped });
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return width;
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2023-02-05 04:01:37 -06:00
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}
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2022-11-12 01:48:25 -06:00
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2024-01-25 00:28:15 -06:00
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[[noreturn]] static void struct_array_packing_error(AstNode *node)
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2023-02-05 04:01:37 -06:00
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{
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2024-01-25 00:28:15 -06:00
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node->input_error("Unpacked array in packed struct/union member %s\n", node->str.c_str());
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2022-11-12 01:48:25 -06:00
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}
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2020-06-07 12:28:45 -05:00
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static int size_packed_struct(AstNode *snode, int base_offset)
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2020-05-12 08:25:33 -05:00
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{
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// Struct members will be laid out in the structure contiguously from left to right.
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// Union members all have zero offset from the start of the union.
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// Determine total packed size and assign offsets. Store these in the member node.
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bool is_union = (snode->type == AST_UNION);
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int offset = 0;
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int packed_width = -1;
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// examine members from last to first
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for (auto it = snode->children.rbegin(); it != snode->children.rend(); ++it) {
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auto node = *it;
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int width;
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if (node->type == AST_STRUCT || node->type == AST_UNION) {
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// embedded struct or union
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width = size_packed_struct(node, base_offset + offset);
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}
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else {
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log_assert(node->type == AST_STRUCT_ITEM);
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2020-06-07 12:28:45 -05:00
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if (node->children.size() > 0 && node->children[0]->type == AST_RANGE) {
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// member width e.g. bit [7:0] a
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width = range_width(node, node->children[0]);
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if (node->children.size() == 2) {
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2022-11-30 13:04:45 -06:00
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// Unpacked array. Note that this is a Yosys extension; only packed data types
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// and integer data types are allowed in packed structs / unions in SystemVerilog.
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2020-06-07 12:28:45 -05:00
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if (node->children[1]->type == AST_RANGE) {
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2022-11-30 13:04:45 -06:00
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|
|
// Unpacked array, e.g. bit [63:0] a [0:3]
|
2024-01-25 00:28:15 -06:00
|
|
|
// Pretend it's declared as a packed array, e.g. bit [0:3][63:0] a
|
2020-06-07 12:28:45 -05:00
|
|
|
auto rnode = node->children[1];
|
2023-02-05 04:01:37 -06:00
|
|
|
if (rnode->children.size() == 1) {
|
|
|
|
// C-style array size, e.g. bit [63:0] a [4]
|
2024-01-25 00:28:15 -06:00
|
|
|
node->dimensions.push_back({ 0, rnode->range_left, true });
|
2023-02-05 04:01:37 -06:00
|
|
|
width *= rnode->range_left;
|
|
|
|
} else {
|
2024-01-25 00:28:15 -06:00
|
|
|
width *= add_dimension(node, rnode);
|
2023-02-05 04:01:37 -06:00
|
|
|
}
|
2024-01-25 00:28:15 -06:00
|
|
|
add_dimension(node, node->children[0]);
|
2020-06-07 12:28:45 -05:00
|
|
|
}
|
|
|
|
else {
|
2022-12-03 12:54:47 -06:00
|
|
|
// The Yosys extension for unpacked arrays in packed structs / unions
|
|
|
|
// only supports memories, i.e. e.g. logic [7:0] a [256] - see above.
|
|
|
|
struct_array_packing_error(node);
|
2020-06-07 12:28:45 -05:00
|
|
|
}
|
2022-11-12 01:48:25 -06:00
|
|
|
} else {
|
2022-12-03 12:54:47 -06:00
|
|
|
// Vector
|
2024-01-25 00:28:15 -06:00
|
|
|
add_dimension(node, node->children[0]);
|
2020-06-07 12:28:45 -05:00
|
|
|
}
|
|
|
|
// range nodes are now redundant
|
2021-06-17 14:59:59 -05:00
|
|
|
for (AstNode *child : node->children)
|
|
|
|
delete child;
|
2020-06-07 12:28:45 -05:00
|
|
|
node->children.clear();
|
|
|
|
}
|
2022-11-30 13:04:45 -06:00
|
|
|
else if (node->children.size() > 0 && node->children[0]->type == AST_MULTIRANGE) {
|
2022-12-03 12:54:47 -06:00
|
|
|
// Packed array, e.g. bit [3:0][63:0] a
|
|
|
|
if (node->children.size() != 1) {
|
|
|
|
// The Yosys extension for unpacked arrays in packed structs / unions
|
|
|
|
// only supports memories, i.e. e.g. logic [7:0] a [256] - see above.
|
|
|
|
struct_array_packing_error(node);
|
|
|
|
}
|
|
|
|
width = 1;
|
|
|
|
for (auto rnode : node->children[0]->children) {
|
2024-01-25 00:28:15 -06:00
|
|
|
width *= add_dimension(node, rnode);
|
2020-06-07 12:28:45 -05:00
|
|
|
}
|
2020-05-12 08:25:33 -05:00
|
|
|
// range nodes are now redundant
|
2021-06-17 14:59:59 -05:00
|
|
|
for (AstNode *child : node->children)
|
|
|
|
delete child;
|
2020-05-12 08:25:33 -05:00
|
|
|
node->children.clear();
|
|
|
|
}
|
|
|
|
else if (node->range_left < 0) {
|
|
|
|
// 1 bit signal: bit, logic or reg
|
|
|
|
width = 1;
|
2024-01-25 00:28:15 -06:00
|
|
|
node->dimensions.push_back({ 0, width, false });
|
2020-05-12 08:25:33 -05:00
|
|
|
}
|
|
|
|
else {
|
|
|
|
// already resolved and compacted
|
|
|
|
width = node->range_left - node->range_right + 1;
|
|
|
|
}
|
|
|
|
if (is_union) {
|
|
|
|
node->range_right = base_offset;
|
|
|
|
node->range_left = base_offset + width - 1;
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
node->range_right = base_offset + offset;
|
|
|
|
node->range_left = base_offset + offset + width - 1;
|
|
|
|
}
|
|
|
|
node->range_valid = true;
|
|
|
|
}
|
|
|
|
if (is_union) {
|
|
|
|
// check that all members have the same size
|
|
|
|
if (packed_width == -1) {
|
|
|
|
// first member
|
|
|
|
packed_width = width;
|
|
|
|
}
|
|
|
|
else {
|
2023-04-04 04:53:50 -05:00
|
|
|
if (packed_width != width)
|
|
|
|
node->input_error("member %s of a packed union has %d bits, expecting %d\n", node->str.c_str(), width, packed_width);
|
2020-05-12 08:25:33 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
offset += width;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
int width = is_union ? packed_width : offset;
|
|
|
|
|
|
|
|
snode->range_right = base_offset;
|
|
|
|
snode->range_left = base_offset + width - 1;
|
|
|
|
snode->range_valid = true;
|
2024-01-05 12:29:06 -06:00
|
|
|
snode->dimensions.push_back({ 0, width, false });
|
2024-01-25 00:28:15 -06:00
|
|
|
|
|
|
|
return width;
|
2020-06-07 12:28:45 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
static AstNode *node_int(int ival)
|
|
|
|
{
|
2020-06-08 14:34:52 -05:00
|
|
|
return AstNode::mkconst_int(ival, true);
|
2020-06-07 12:28:45 -05:00
|
|
|
}
|
|
|
|
|
2020-06-08 14:34:52 -05:00
|
|
|
static AstNode *multiply_by_const(AstNode *expr_node, int stride)
|
|
|
|
{
|
2020-06-09 07:52:09 -05:00
|
|
|
return new AstNode(AST_MUL, expr_node, node_int(stride));
|
2020-06-08 14:34:52 -05:00
|
|
|
}
|
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
static AstNode *normalize_index(AstNode *expr, AstNode *decl_node, int dimension)
|
2020-06-08 14:34:52 -05:00
|
|
|
{
|
2022-12-03 23:54:22 -06:00
|
|
|
expr = expr->clone();
|
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
int offset = decl_node->dimensions[dimension].range_right;
|
2023-02-05 04:01:37 -06:00
|
|
|
if (offset) {
|
|
|
|
expr = new AstNode(AST_SUB, expr, node_int(offset));
|
|
|
|
}
|
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
// Packed dimensions are normally indexed by lsb, while unpacked dimensions are normally indexed by msb.
|
|
|
|
if ((dimension < decl_node->unpacked_dimensions) ^ decl_node->dimensions[dimension].range_swapped) {
|
|
|
|
// Swap the index if the dimension is declared the "wrong" way.
|
|
|
|
int left = decl_node->dimensions[dimension].range_width - 1;
|
|
|
|
expr = new AstNode(AST_SUB, node_int(left), expr);
|
2022-11-12 01:48:25 -06:00
|
|
|
}
|
2022-12-03 23:54:22 -06:00
|
|
|
|
|
|
|
return expr;
|
2022-12-03 12:54:47 -06:00
|
|
|
}
|
2022-11-12 01:48:25 -06:00
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
static AstNode *index_offset(AstNode *offset, AstNode *rnode, AstNode *decl_node, int dimension, int &stride)
|
2022-12-03 12:54:47 -06:00
|
|
|
{
|
2024-01-25 00:28:15 -06:00
|
|
|
stride /= decl_node->dimensions[dimension].range_width;
|
|
|
|
auto right = normalize_index(rnode->children.back(), decl_node, dimension);
|
|
|
|
auto add_offset = stride > 1 ? multiply_by_const(right, stride) : right;
|
|
|
|
return offset ? new AstNode(AST_ADD, offset, add_offset) : add_offset;
|
2020-06-08 14:34:52 -05:00
|
|
|
}
|
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
static AstNode *index_msb_offset(AstNode *lsb_offset, AstNode *rnode, AstNode *decl_node, int dimension, int stride)
|
2020-06-08 14:34:52 -05:00
|
|
|
{
|
2022-12-03 12:54:47 -06:00
|
|
|
log_assert(rnode->children.size() <= 2);
|
|
|
|
|
|
|
|
// Offset to add to LSB
|
2024-01-25 00:28:15 -06:00
|
|
|
AstNode *add_offset;
|
2022-12-03 12:54:47 -06:00
|
|
|
if (rnode->children.size() == 1) {
|
|
|
|
// Index, e.g. s.a[i]
|
2024-01-25 00:28:15 -06:00
|
|
|
add_offset = node_int(stride - 1);
|
2022-12-03 12:54:47 -06:00
|
|
|
}
|
|
|
|
else {
|
|
|
|
// rnode->children.size() == 2
|
|
|
|
// Slice, e.g. s.a[i:j]
|
2024-01-25 00:28:15 -06:00
|
|
|
auto left = normalize_index(rnode->children[0], decl_node, dimension);
|
|
|
|
auto right = normalize_index(rnode->children[1], decl_node, dimension);
|
|
|
|
add_offset = new AstNode(AST_SUB, left, right);
|
2022-12-03 23:54:22 -06:00
|
|
|
if (stride > 1) {
|
2022-12-03 12:54:47 -06:00
|
|
|
// offset = (msb - lsb + 1)*stride - 1
|
2024-01-25 00:28:15 -06:00
|
|
|
auto slice_width = new AstNode(AST_ADD, add_offset, node_int(1));
|
|
|
|
add_offset = new AstNode(AST_SUB, multiply_by_const(slice_width, stride), node_int(1));
|
2022-11-23 09:31:08 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
return new AstNode(AST_ADD, lsb_offset, add_offset);
|
2020-06-07 12:28:45 -05:00
|
|
|
}
|
|
|
|
|
2020-06-08 14:34:52 -05:00
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
AstNode *AstNode::make_index_range(AstNode *decl_node, bool unpacked_range)
|
2020-06-07 12:28:45 -05:00
|
|
|
{
|
|
|
|
// Work out the range in the packed array that corresponds to a struct member
|
|
|
|
// taking into account any range operations applicable to the current node
|
|
|
|
// such as array indexing or slicing
|
2024-01-25 00:28:15 -06:00
|
|
|
if (children.empty()) {
|
2020-06-07 12:28:45 -05:00
|
|
|
// no range operations apply, return the whole width
|
2024-01-25 00:28:15 -06:00
|
|
|
return make_range(decl_node->range_left - decl_node->range_right, 0);
|
2020-06-07 12:28:45 -05:00
|
|
|
}
|
2022-12-03 12:54:47 -06:00
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
log_assert(children.size() == 1);
|
2022-12-03 12:54:47 -06:00
|
|
|
|
|
|
|
// Range operations
|
2024-01-25 00:28:15 -06:00
|
|
|
AstNode *rnode = children[0];
|
|
|
|
AstNode *offset = NULL;
|
|
|
|
int dim = unpacked_range ? 0 : decl_node->unpacked_dimensions;
|
|
|
|
int max_dim = unpacked_range ? decl_node->unpacked_dimensions : GetSize(decl_node->dimensions);
|
|
|
|
|
|
|
|
int stride = 1;
|
|
|
|
for (int i = dim; i < max_dim; i++) {
|
|
|
|
stride *= decl_node->dimensions[i].range_width;
|
|
|
|
}
|
2022-12-03 12:54:47 -06:00
|
|
|
|
|
|
|
// Calculate LSB offset for the final index / slice
|
|
|
|
if (rnode->type == AST_RANGE) {
|
2024-01-25 00:28:15 -06:00
|
|
|
offset = index_offset(offset, rnode, decl_node, dim, stride);
|
2020-06-08 14:34:52 -05:00
|
|
|
}
|
2022-12-03 12:54:47 -06:00
|
|
|
else if (rnode->type == AST_MULTIRANGE) {
|
|
|
|
// Add offset for each dimension
|
2024-01-25 00:28:15 -06:00
|
|
|
AstNode *mrnode = rnode;
|
|
|
|
int stop_dim = std::min(GetSize(mrnode->children), max_dim);
|
|
|
|
for (; dim < stop_dim; dim++) {
|
|
|
|
rnode = mrnode->children[dim];
|
|
|
|
offset = index_offset(offset, rnode, decl_node, dim, stride);
|
2022-12-03 12:54:47 -06:00
|
|
|
}
|
2024-01-25 00:28:15 -06:00
|
|
|
dim--; // Step back to the final index / slice
|
2020-06-07 12:28:45 -05:00
|
|
|
}
|
|
|
|
else {
|
2024-01-25 00:28:15 -06:00
|
|
|
input_error("Unsupported range operation for %s\n", str.c_str());
|
|
|
|
}
|
|
|
|
|
|
|
|
AstNode *index_range = new AstNode(AST_RANGE);
|
|
|
|
|
|
|
|
if (!unpacked_range && (stride > 1 || GetSize(rnode->children) == 2)) {
|
|
|
|
// Calculate MSB offset for the final index / slice of packed dimensions.
|
|
|
|
AstNode *msb_offset = index_msb_offset(offset->clone(), rnode, decl_node, dim, stride);
|
|
|
|
index_range->children.push_back(msb_offset);
|
2020-06-07 12:28:45 -05:00
|
|
|
}
|
2022-12-03 12:54:47 -06:00
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
index_range->children.push_back(offset);
|
2022-12-03 12:54:47 -06:00
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
return index_range;
|
2020-06-07 12:28:45 -05:00
|
|
|
}
|
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
AstNode *AstNode::get_struct_member() const
|
2023-02-28 11:45:55 -06:00
|
|
|
{
|
2024-01-25 00:28:15 -06:00
|
|
|
AstNode *member_node;
|
|
|
|
if (attributes.count(ID::wiretype) && (member_node = attributes.at(ID::wiretype)) &&
|
2023-02-28 11:45:55 -06:00
|
|
|
(member_node->type == AST_STRUCT_ITEM || member_node->type == AST_STRUCT || member_node->type == AST_UNION))
|
|
|
|
{
|
|
|
|
return member_node;
|
|
|
|
}
|
2024-01-25 00:28:15 -06:00
|
|
|
return nullptr;
|
2023-02-28 11:45:55 -06:00
|
|
|
}
|
|
|
|
|
2020-05-12 08:25:33 -05:00
|
|
|
static void add_members_to_scope(AstNode *snode, std::string name)
|
|
|
|
{
|
|
|
|
// add all the members in a struct or union to local scope
|
|
|
|
// in case later referenced in assignments
|
|
|
|
log_assert(snode->type==AST_STRUCT || snode->type==AST_UNION);
|
|
|
|
for (auto *node : snode->children) {
|
2022-02-14 07:34:20 -06:00
|
|
|
auto member_name = name + "." + node->str;
|
|
|
|
current_scope[member_name] = node;
|
2020-05-12 08:25:33 -05:00
|
|
|
if (node->type != AST_STRUCT_ITEM) {
|
|
|
|
// embedded struct or union
|
|
|
|
add_members_to_scope(node, name + "." + node->str);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
Handling of attributes for struct / union variables
(* nowrshmsk *) on a struct / union variable now affects dynamic
bit slice assignments to members of the struct / union.
(* nowrshmsk *) can in some cases yield significant resource savings; the
combination of pipeline shifting and indexed writes is an example of this.
Constructs similar to the one below can benefit from (* nowrshmsk *), and
in addition it is no longer necessary to split out the shift assignments
on separate lines in order to avoid the error message "ERROR: incompatible
mix of lookahead and non-lookahead IDs in LHS expression."
always_ff @(posedge clk) begin
if (rotate) begin
{ v5, v4, v3, v2, v1, v0 } <= { v4, v3, v2, v1, v0, v5 };
if (res) begin
v0.bytes <= '0;
end else if (w) begin
v0.bytes[addr] <= data;
end
end
end
2023-03-02 12:02:30 -06:00
|
|
|
static AstNode *make_packed_struct(AstNode *template_node, std::string &name, decltype(AstNode::attributes) &attributes)
|
2020-05-08 08:40:49 -05:00
|
|
|
{
|
|
|
|
// create a wire for the packed struct
|
2024-01-25 00:28:15 -06:00
|
|
|
auto wnode = new AstNode(AST_WIRE, make_range(template_node->range_left, 0));
|
2020-05-08 08:40:49 -05:00
|
|
|
wnode->str = name;
|
|
|
|
wnode->is_logic = true;
|
|
|
|
wnode->range_valid = true;
|
2020-05-12 08:25:33 -05:00
|
|
|
wnode->is_signed = template_node->is_signed;
|
Handling of attributes for struct / union variables
(* nowrshmsk *) on a struct / union variable now affects dynamic
bit slice assignments to members of the struct / union.
(* nowrshmsk *) can in some cases yield significant resource savings; the
combination of pipeline shifting and indexed writes is an example of this.
Constructs similar to the one below can benefit from (* nowrshmsk *), and
in addition it is no longer necessary to split out the shift assignments
on separate lines in order to avoid the error message "ERROR: incompatible
mix of lookahead and non-lookahead IDs in LHS expression."
always_ff @(posedge clk) begin
if (rotate) begin
{ v5, v4, v3, v2, v1, v0 } <= { v4, v3, v2, v1, v0, v5 };
if (res) begin
v0.bytes <= '0;
end else if (w) begin
v0.bytes[addr] <= data;
end
end
end
2023-03-02 12:02:30 -06:00
|
|
|
for (auto &pair : attributes) {
|
2023-04-05 04:00:07 -05:00
|
|
|
wnode->set_attribute(pair.first, pair.second->clone());
|
Handling of attributes for struct / union variables
(* nowrshmsk *) on a struct / union variable now affects dynamic
bit slice assignments to members of the struct / union.
(* nowrshmsk *) can in some cases yield significant resource savings; the
combination of pipeline shifting and indexed writes is an example of this.
Constructs similar to the one below can benefit from (* nowrshmsk *), and
in addition it is no longer necessary to split out the shift assignments
on separate lines in order to avoid the error message "ERROR: incompatible
mix of lookahead and non-lookahead IDs in LHS expression."
always_ff @(posedge clk) begin
if (rotate) begin
{ v5, v4, v3, v2, v1, v0 } <= { v4, v3, v2, v1, v0, v5 };
if (res) begin
v0.bytes <= '0;
end else if (w) begin
v0.bytes[addr] <= data;
end
end
end
2023-03-02 12:02:30 -06:00
|
|
|
}
|
2024-01-25 00:28:15 -06:00
|
|
|
// resolve packed dimension
|
|
|
|
while (wnode->simplify(true, 1, -1, false)) {}
|
2020-05-08 08:40:49 -05:00
|
|
|
// make sure this node is the one in scope for this name
|
|
|
|
current_scope[name] = wnode;
|
2020-05-12 08:25:33 -05:00
|
|
|
// add all the struct members to scope under the wire's name
|
|
|
|
add_members_to_scope(template_node, name);
|
2020-05-08 08:40:49 -05:00
|
|
|
return wnode;
|
|
|
|
}
|
|
|
|
|
2023-12-31 18:18:00 -06:00
|
|
|
static void prepend_ranges(AstNode *&range, AstNode *range_add)
|
|
|
|
{
|
|
|
|
// Convert range to multirange.
|
|
|
|
if (range->type == AST_RANGE)
|
|
|
|
range = new AstNode(AST_MULTIRANGE, range);
|
|
|
|
|
|
|
|
// Add range or ranges.
|
|
|
|
if (range_add->type == AST_RANGE)
|
|
|
|
range->children.insert(range->children.begin(), range_add->clone());
|
|
|
|
else {
|
|
|
|
int i = 0;
|
|
|
|
for (auto child : range_add->children)
|
|
|
|
range->children.insert(range->children.begin() + i++, child->clone());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-07-24 22:18:24 -05:00
|
|
|
// check if a node or its children contains an assignment to the given variable
|
|
|
|
static bool node_contains_assignment_to(const AstNode* node, const AstNode* var)
|
|
|
|
{
|
|
|
|
if (node->type == AST_ASSIGN_EQ || node->type == AST_ASSIGN_LE) {
|
|
|
|
// current node is iteslf an assignment
|
|
|
|
log_assert(node->children.size() >= 2);
|
|
|
|
const AstNode* lhs = node->children[0];
|
|
|
|
if (lhs->type == AST_IDENTIFIER && lhs->str == var->str)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
for (const AstNode* child : node->children) {
|
|
|
|
// if this child shadows the given variable
|
|
|
|
if (child != var && child->str == var->str && child->type == AST_WIRE)
|
|
|
|
break; // skip the remainder of this block/scope
|
|
|
|
// depth-first short circuit
|
|
|
|
if (!node_contains_assignment_to(child, var))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
static std::string prefix_id(const std::string &prefix, const std::string &str)
|
|
|
|
{
|
|
|
|
log_assert(!prefix.empty() && (prefix.front() == '$' || prefix.front() == '\\'));
|
|
|
|
log_assert(!str.empty() && (str.front() == '$' || str.front() == '\\'));
|
|
|
|
log_assert(prefix.back() == '.');
|
|
|
|
if (str.front() == '\\')
|
|
|
|
return prefix + str.substr(1);
|
|
|
|
return prefix + str;
|
|
|
|
}
|
|
|
|
|
2021-10-19 19:46:26 -05:00
|
|
|
// direct access to this global should be limited to the following two functions
|
|
|
|
static const RTLIL::Design *simplify_design_context = nullptr;
|
|
|
|
|
|
|
|
void AST::set_simplify_design_context(const RTLIL::Design *design)
|
|
|
|
{
|
|
|
|
log_assert(!simplify_design_context || !design);
|
|
|
|
simplify_design_context = design;
|
|
|
|
}
|
|
|
|
|
|
|
|
// lookup the module with the given name in the current design context
|
|
|
|
static const RTLIL::Module* lookup_module(const std::string &name)
|
|
|
|
{
|
|
|
|
return simplify_design_context->module(name);
|
|
|
|
}
|
|
|
|
|
|
|
|
const RTLIL::Module* AstNode::lookup_cell_module()
|
|
|
|
{
|
|
|
|
log_assert(type == AST_CELL);
|
|
|
|
|
|
|
|
auto reprocess_after = [this] (const std::string &modname) {
|
|
|
|
if (!attributes.count(ID::reprocess_after))
|
2023-04-05 04:00:07 -05:00
|
|
|
set_attribute(ID::reprocess_after, AstNode::mkconst_str(modname));
|
2021-10-19 19:46:26 -05:00
|
|
|
};
|
|
|
|
|
|
|
|
const AstNode *celltype = nullptr;
|
|
|
|
for (const AstNode *child : children)
|
|
|
|
if (child->type == AST_CELLTYPE) {
|
|
|
|
celltype = child;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
log_assert(celltype != nullptr);
|
|
|
|
|
|
|
|
const RTLIL::Module *module = lookup_module(celltype->str);
|
|
|
|
if (!module)
|
|
|
|
module = lookup_module("$abstract" + celltype->str);
|
|
|
|
if (!module) {
|
|
|
|
if (celltype->str.at(0) != '$')
|
|
|
|
reprocess_after(celltype->str);
|
|
|
|
return nullptr;
|
|
|
|
}
|
|
|
|
|
|
|
|
// build a mapping from true param name to param value
|
|
|
|
size_t para_counter = 0;
|
|
|
|
dict<RTLIL::IdString, RTLIL::Const> cell_params_map;
|
|
|
|
for (AstNode *child : children) {
|
|
|
|
if (child->type != AST_PARASET)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (child->str.empty() && para_counter >= module->avail_parameters.size())
|
|
|
|
return nullptr; // let hierarchy handle this error
|
|
|
|
IdString paraname = child->str.empty() ? module->avail_parameters[para_counter++] : child->str;
|
|
|
|
|
|
|
|
const AstNode *value = child->children[0];
|
|
|
|
if (value->type != AST_REALVALUE && value->type != AST_CONSTANT)
|
|
|
|
return nullptr; // let genrtlil handle this error
|
|
|
|
cell_params_map[paraname] = value->asParaConst();
|
|
|
|
}
|
|
|
|
|
|
|
|
// put the parameters in order and generate the derived module name
|
|
|
|
std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> named_parameters;
|
|
|
|
for (RTLIL::IdString param : module->avail_parameters) {
|
|
|
|
auto it = cell_params_map.find(param);
|
|
|
|
if (it != cell_params_map.end())
|
|
|
|
named_parameters.emplace_back(it->first, it->second);
|
|
|
|
}
|
|
|
|
std::string modname = celltype->str;
|
|
|
|
if (cell_params_map.size()) // not named_parameters to cover hierarchical defparams
|
|
|
|
modname = derived_module_name(celltype->str, named_parameters);
|
|
|
|
|
|
|
|
// try to find the resolved module
|
|
|
|
module = lookup_module(modname);
|
|
|
|
if (!module) {
|
|
|
|
reprocess_after(modname);
|
|
|
|
return nullptr;
|
|
|
|
}
|
|
|
|
return module;
|
|
|
|
}
|
|
|
|
|
|
|
|
// returns whether an expression contains an unbased unsized literal; does not
|
|
|
|
// check the literal exists in a self-determined context
|
|
|
|
static bool contains_unbased_unsized(const AstNode *node)
|
|
|
|
{
|
|
|
|
if (node->type == AST_CONSTANT)
|
|
|
|
return node->is_unsized;
|
|
|
|
for (const AstNode *child : node->children)
|
|
|
|
if (contains_unbased_unsized(child))
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// adds a wire to the current module with the given name that matches the
|
|
|
|
// dimensions of the given wire reference
|
|
|
|
void add_wire_for_ref(const RTLIL::Wire *ref, const std::string &str)
|
|
|
|
{
|
|
|
|
AstNode *left = AstNode::mkconst_int(ref->width - 1 + ref->start_offset, true);
|
|
|
|
AstNode *right = AstNode::mkconst_int(ref->start_offset, true);
|
|
|
|
if (ref->upto)
|
|
|
|
std::swap(left, right);
|
|
|
|
AstNode *range = new AstNode(AST_RANGE, left, right);
|
|
|
|
|
|
|
|
AstNode *wire = new AstNode(AST_WIRE, range);
|
|
|
|
wire->is_signed = ref->is_signed;
|
|
|
|
wire->is_logic = true;
|
|
|
|
wire->str = str;
|
|
|
|
|
|
|
|
current_ast_mod->children.push_back(wire);
|
|
|
|
current_scope[str] = wire;
|
|
|
|
}
|
|
|
|
|
2022-01-06 23:04:00 -06:00
|
|
|
enum class IdentUsage {
|
|
|
|
NotReferenced, // target variable is neither read or written in the block
|
|
|
|
Assigned, // target variable is always assigned before use
|
|
|
|
SyncRequired, // target variable may be used before it has been assigned
|
|
|
|
};
|
|
|
|
|
|
|
|
// determines whether a local variable a block is always assigned before it is
|
|
|
|
// used, meaning the nosync attribute can automatically be added to that
|
|
|
|
// variable
|
|
|
|
static IdentUsage always_asgn_before_use(const AstNode *node, const std::string &target)
|
|
|
|
{
|
|
|
|
// This variable has been referenced before it has necessarily been assigned
|
|
|
|
// a value in this procedure.
|
|
|
|
if (node->type == AST_IDENTIFIER && node->str == target)
|
|
|
|
return IdentUsage::SyncRequired;
|
|
|
|
|
|
|
|
// For case statements (which are also used for if/else), we check each
|
|
|
|
// possible branch. If the variable is assigned in all branches, then it is
|
|
|
|
// assigned, and a sync isn't required. If it used before assignment in any
|
|
|
|
// branch, then a sync is required.
|
|
|
|
if (node->type == AST_CASE) {
|
|
|
|
bool all_defined = true;
|
|
|
|
bool any_used = false;
|
|
|
|
bool has_default = false;
|
|
|
|
for (const AstNode *child : node->children) {
|
|
|
|
if (child->type == AST_COND && child->children.at(0)->type == AST_DEFAULT)
|
|
|
|
has_default = true;
|
|
|
|
IdentUsage nested = always_asgn_before_use(child, target);
|
|
|
|
if (nested != IdentUsage::Assigned && child->type == AST_COND)
|
|
|
|
all_defined = false;
|
|
|
|
if (nested == IdentUsage::SyncRequired)
|
|
|
|
any_used = true;
|
|
|
|
}
|
|
|
|
if (any_used)
|
|
|
|
return IdentUsage::SyncRequired;
|
|
|
|
else if (all_defined && has_default)
|
|
|
|
return IdentUsage::Assigned;
|
|
|
|
else
|
|
|
|
return IdentUsage::NotReferenced;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Check if this is an assignment to the target variable. For simplicity, we
|
|
|
|
// don't analyze sub-ranges of the variable.
|
|
|
|
if (node->type == AST_ASSIGN_EQ) {
|
|
|
|
const AstNode *ident = node->children.at(0);
|
|
|
|
if (ident->type == AST_IDENTIFIER && ident->str == target)
|
|
|
|
return IdentUsage::Assigned;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (const AstNode *child : node->children) {
|
|
|
|
IdentUsage nested = always_asgn_before_use(child, target);
|
|
|
|
if (nested != IdentUsage::NotReferenced)
|
|
|
|
return nested;
|
|
|
|
}
|
|
|
|
return IdentUsage::NotReferenced;
|
|
|
|
}
|
|
|
|
|
2023-06-21 06:45:42 -05:00
|
|
|
AstNode *AstNode::clone_at_zero()
|
|
|
|
{
|
|
|
|
int width_hint;
|
|
|
|
bool sign_hint;
|
|
|
|
AstNode *pointee;
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case AST_IDENTIFIER:
|
|
|
|
if (id2ast)
|
|
|
|
pointee = id2ast;
|
|
|
|
else if (current_scope.count(str))
|
|
|
|
pointee = current_scope[str];
|
|
|
|
else
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (pointee->type != AST_WIRE &&
|
|
|
|
pointee->type != AST_AUTOWIRE &&
|
|
|
|
pointee->type != AST_MEMORY)
|
|
|
|
break;
|
|
|
|
|
2024-01-11 03:39:28 -06:00
|
|
|
YS_FALLTHROUGH
|
2023-06-21 06:45:42 -05:00
|
|
|
case AST_MEMRD:
|
|
|
|
detectSignWidth(width_hint, sign_hint);
|
|
|
|
return mkconst_int(0, sign_hint, width_hint);
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
AstNode *that = new AstNode;
|
|
|
|
*that = *this;
|
|
|
|
for (auto &it : that->children)
|
|
|
|
it = it->clone_at_zero();
|
|
|
|
for (auto &it : that->attributes)
|
|
|
|
it.second = it.second->clone();
|
2023-04-05 04:00:07 -05:00
|
|
|
|
|
|
|
that->set_in_lvalue_flag(false);
|
|
|
|
that->set_in_param_flag(false);
|
|
|
|
that->fixup_hierarchy_flags();
|
|
|
|
|
2023-06-21 06:45:42 -05:00
|
|
|
return that;
|
|
|
|
}
|
|
|
|
|
2023-04-04 04:34:17 -05:00
|
|
|
static bool try_determine_range_width(AstNode *range, int &result_width)
|
|
|
|
{
|
|
|
|
log_assert(range->type == AST_RANGE);
|
|
|
|
|
|
|
|
if (range->children.size() == 1) {
|
|
|
|
result_width = 1;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2023-06-21 06:45:42 -05:00
|
|
|
AstNode *left_at_zero_ast = range->children[0]->clone_at_zero();
|
|
|
|
AstNode *right_at_zero_ast = range->children[1]->clone_at_zero();
|
2023-04-04 04:34:17 -05:00
|
|
|
|
2023-04-04 15:59:44 -05:00
|
|
|
while (left_at_zero_ast->simplify(true, 1, -1, false)) {}
|
|
|
|
while (right_at_zero_ast->simplify(true, 1, -1, false)) {}
|
2023-04-04 04:34:17 -05:00
|
|
|
|
|
|
|
bool ok = false;
|
|
|
|
if (left_at_zero_ast->type == AST_CONSTANT
|
|
|
|
&& right_at_zero_ast->type == AST_CONSTANT) {
|
|
|
|
ok = true;
|
|
|
|
result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
delete left_at_zero_ast;
|
|
|
|
delete right_at_zero_ast;
|
|
|
|
return ok;
|
|
|
|
}
|
|
|
|
|
2022-01-06 23:04:00 -06:00
|
|
|
static const std::string auto_nosync_prefix = "\\AutoNosync";
|
|
|
|
|
|
|
|
// mark a local variable in an always_comb block for automatic nosync
|
|
|
|
// consideration
|
|
|
|
static void mark_auto_nosync(AstNode *block, const AstNode *wire)
|
|
|
|
{
|
|
|
|
log_assert(block->type == AST_BLOCK);
|
|
|
|
log_assert(wire->type == AST_WIRE);
|
2023-04-05 04:00:07 -05:00
|
|
|
block->set_attribute(auto_nosync_prefix + wire->str, AstNode::mkconst_int(1, false));
|
2022-01-06 23:04:00 -06:00
|
|
|
}
|
|
|
|
|
2022-02-22 09:57:08 -06:00
|
|
|
// block names can be prefixed with an explicit scope during elaboration
|
|
|
|
static bool is_autonamed_block(const std::string &str) {
|
|
|
|
size_t last_dot = str.rfind('.');
|
|
|
|
// unprefixed names: autonamed if the first char is a dollar sign
|
|
|
|
if (last_dot == std::string::npos)
|
|
|
|
return str.at(0) == '$'; // e.g., `$fordecl_block$1`
|
|
|
|
// prefixed names: autonamed if the final chunk begins with a dollar sign
|
|
|
|
return str.rfind(".$") == last_dot; // e.g., `\foo.bar.$fordecl_block$1`
|
|
|
|
}
|
|
|
|
|
2022-01-06 23:04:00 -06:00
|
|
|
// check a procedural block for auto-nosync markings, remove them, and add
|
|
|
|
// nosync to local variables as necessary
|
|
|
|
static void check_auto_nosync(AstNode *node)
|
|
|
|
{
|
|
|
|
std::vector<RTLIL::IdString> attrs_to_drop;
|
|
|
|
for (const auto& elem : node->attributes) {
|
|
|
|
// skip attributes that don't begin with the prefix
|
|
|
|
if (elem.first.compare(0, auto_nosync_prefix.size(),
|
|
|
|
auto_nosync_prefix.c_str()))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// delete and remove the attribute once we're done iterating
|
|
|
|
attrs_to_drop.push_back(elem.first);
|
|
|
|
|
|
|
|
// find the wire based on the attribute
|
|
|
|
std::string wire_name = elem.first.substr(auto_nosync_prefix.size());
|
|
|
|
auto it = current_scope.find(wire_name);
|
|
|
|
if (it == current_scope.end())
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// analyze the usage of the local variable in this block
|
|
|
|
IdentUsage ident_usage = always_asgn_before_use(node, wire_name);
|
|
|
|
if (ident_usage != IdentUsage::Assigned)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// mark the wire with `nosync`
|
|
|
|
AstNode *wire = it->second;
|
|
|
|
log_assert(wire->type == AST_WIRE);
|
2023-04-05 04:00:07 -05:00
|
|
|
wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
|
2022-01-06 23:04:00 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
// remove the attributes we've "consumed"
|
|
|
|
for (const RTLIL::IdString &str : attrs_to_drop) {
|
|
|
|
auto it = node->attributes.find(str);
|
|
|
|
delete it->second;
|
|
|
|
node->attributes.erase(it);
|
|
|
|
}
|
|
|
|
|
|
|
|
// check local variables in any nested blocks
|
|
|
|
for (AstNode *child : node->children)
|
|
|
|
check_auto_nosync(child);
|
|
|
|
}
|
|
|
|
|
2015-08-14 03:56:05 -05:00
|
|
|
// convert the AST into a simpler AST that has all parameters substituted by their
|
2013-01-05 04:13:26 -06:00
|
|
|
// values, unrolled for-loops, expanded generate blocks, etc. when this function
|
|
|
|
// is done with an AST it can be converted into RTLIL using genRTLIL().
|
|
|
|
//
|
|
|
|
// this function also does all name resolving and sets the id2ast member of all
|
|
|
|
// nodes that link to a different node using names and lexical scoping.
|
2023-04-04 15:59:44 -05:00
|
|
|
bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hint)
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
2015-02-13 05:33:12 -06:00
|
|
|
static int recursion_counter = 0;
|
2015-02-20 03:33:20 -06:00
|
|
|
static bool deep_recursion_warning = false;
|
|
|
|
|
|
|
|
if (recursion_counter++ == 1000 && deep_recursion_warning) {
|
2021-02-25 15:02:55 -06:00
|
|
|
log_warning("Deep recursion in AST simplifier.\nDoes this design contain overly long or deeply nested expressions, or excessive recursion?\n");
|
2015-02-20 03:33:20 -06:00
|
|
|
deep_recursion_warning = false;
|
|
|
|
}
|
2015-02-13 05:33:12 -06:00
|
|
|
|
2021-02-12 13:25:34 -06:00
|
|
|
static bool unevaluated_tern_branch = false;
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
AstNode *newNode = NULL;
|
|
|
|
bool did_something = false;
|
|
|
|
|
2014-06-14 05:00:47 -05:00
|
|
|
#if 0
|
|
|
|
log("-------------\n");
|
2020-02-23 01:19:52 -06:00
|
|
|
log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, filename.c_str(), location.first_line, type2str(type).c_str(), this);
|
2023-04-04 15:59:44 -05:00
|
|
|
log("const_fold=%d, stage=%d, width_hint=%d, sign_hint=%d\n",
|
|
|
|
int(const_fold), int(stage), int(width_hint), int(sign_hint));
|
2015-02-20 03:21:36 -06:00
|
|
|
// dumpAst(NULL, "> ");
|
2014-06-14 05:00:47 -05:00
|
|
|
#endif
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
if (stage == 0)
|
|
|
|
{
|
2018-10-11 16:33:31 -05:00
|
|
|
log_assert(type == AST_MODULE || type == AST_INTERFACE);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2015-02-20 03:33:20 -06:00
|
|
|
deep_recursion_warning = true;
|
2023-04-04 15:59:44 -05:00
|
|
|
while (simplify(const_fold, 1, width_hint, sign_hint)) { }
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2020-04-02 11:51:32 -05:00
|
|
|
if (!flag_nomem2reg && !get_bool_attribute(ID::nomem2reg))
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
2014-12-28 20:11:50 -06:00
|
|
|
dict<AstNode*, pool<std::string>> mem2reg_places;
|
|
|
|
dict<AstNode*, uint32_t> mem2reg_candidates, dummy_proc_flags;
|
2013-11-21 06:49:00 -06:00
|
|
|
uint32_t flags = flag_mem2reg ? AstNode::MEM2REG_FL_ALL : 0;
|
|
|
|
mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, dummy_proc_flags, flags);
|
|
|
|
|
2014-12-28 20:11:50 -06:00
|
|
|
pool<AstNode*> mem2reg_set;
|
2013-11-21 06:49:00 -06:00
|
|
|
for (auto &it : mem2reg_candidates)
|
|
|
|
{
|
|
|
|
AstNode *mem = it.first;
|
|
|
|
uint32_t memflags = it.second;
|
2015-02-14 04:21:12 -06:00
|
|
|
bool this_nomeminit = flag_nomeminit;
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert((memflags & ~0x00ffff00) == 0);
|
2013-11-21 06:49:00 -06:00
|
|
|
|
2020-04-02 11:51:32 -05:00
|
|
|
if (mem->get_bool_attribute(ID::nomem2reg))
|
2013-11-21 06:49:00 -06:00
|
|
|
continue;
|
|
|
|
|
2020-04-02 11:51:32 -05:00
|
|
|
if (mem->get_bool_attribute(ID::nomeminit) || get_bool_attribute(ID::nomeminit))
|
2015-02-14 04:21:12 -06:00
|
|
|
this_nomeminit = true;
|
|
|
|
|
2013-11-21 06:49:00 -06:00
|
|
|
if (memflags & AstNode::MEM2REG_FL_FORCED)
|
|
|
|
goto silent_activate;
|
|
|
|
|
|
|
|
if (memflags & AstNode::MEM2REG_FL_EQ2)
|
|
|
|
goto verbose_activate;
|
|
|
|
|
2013-11-21 14:26:56 -06:00
|
|
|
if (memflags & AstNode::MEM2REG_FL_SET_ASYNC)
|
|
|
|
goto verbose_activate;
|
|
|
|
|
2015-02-14 04:21:12 -06:00
|
|
|
if ((memflags & AstNode::MEM2REG_FL_SET_INIT) && (memflags & AstNode::MEM2REG_FL_SET_ELSE) && this_nomeminit)
|
2013-11-21 06:49:00 -06:00
|
|
|
goto verbose_activate;
|
|
|
|
|
2014-06-17 14:39:25 -05:00
|
|
|
if (memflags & AstNode::MEM2REG_FL_CMPLX_LHS)
|
|
|
|
goto verbose_activate;
|
|
|
|
|
2019-03-01 15:35:09 -06:00
|
|
|
if ((memflags & AstNode::MEM2REG_FL_CONST_LHS) && !(memflags & AstNode::MEM2REG_FL_VAR_LHS))
|
|
|
|
goto verbose_activate;
|
|
|
|
|
2013-11-21 14:26:56 -06:00
|
|
|
// log("Note: Not replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str.c_str(), long(memflags));
|
2013-11-21 06:49:00 -06:00
|
|
|
continue;
|
|
|
|
|
|
|
|
verbose_activate:
|
|
|
|
if (mem2reg_set.count(mem) == 0) {
|
2014-12-26 20:26:30 -06:00
|
|
|
std::string message = stringf("Replacing memory %s with list of registers.", mem->str.c_str());
|
2013-11-21 06:49:00 -06:00
|
|
|
bool first_element = true;
|
|
|
|
for (auto &place : mem2reg_places[it.first]) {
|
2014-12-26 20:26:30 -06:00
|
|
|
message += stringf("%s%s", first_element ? " See " : ", ", place.c_str());
|
2013-11-21 06:49:00 -06:00
|
|
|
first_element = false;
|
|
|
|
}
|
2014-12-26 20:26:30 -06:00
|
|
|
log_warning("%s\n", message.c_str());
|
2013-11-21 06:49:00 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
silent_activate:
|
2013-11-21 14:26:56 -06:00
|
|
|
// log("Note: Replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str.c_str(), long(memflags));
|
2013-11-21 06:49:00 -06:00
|
|
|
mem2reg_set.insert(mem);
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
for (auto node : mem2reg_set)
|
|
|
|
{
|
|
|
|
int mem_width, mem_size, addr_bits;
|
|
|
|
node->meminfo(mem_width, mem_size, addr_bits);
|
|
|
|
|
2019-03-21 16:19:17 -05:00
|
|
|
int data_range_left = node->children[0]->range_left;
|
|
|
|
int data_range_right = node->children[0]->range_right;
|
|
|
|
|
|
|
|
if (node->children[0]->range_swapped)
|
|
|
|
std::swap(data_range_left, data_range_right);
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
for (int i = 0; i < mem_size; i++) {
|
|
|
|
AstNode *reg = new AstNode(AST_WIRE, new AstNode(AST_RANGE,
|
2019-03-21 16:19:17 -05:00
|
|
|
mkconst_int(data_range_left, true), mkconst_int(data_range_right, true)));
|
2013-01-05 04:13:26 -06:00
|
|
|
reg->str = stringf("%s[%d]", node->str.c_str(), i);
|
|
|
|
reg->is_reg = true;
|
|
|
|
reg->is_signed = node->is_signed;
|
2019-08-21 15:36:01 -05:00
|
|
|
for (auto &it : node->attributes)
|
2020-04-02 11:51:32 -05:00
|
|
|
if (it.first != ID::mem2reg)
|
2023-04-05 04:00:07 -05:00
|
|
|
reg->set_attribute(it.first, it.second->clone());
|
2019-08-21 15:36:01 -05:00
|
|
|
reg->filename = node->filename;
|
2020-02-23 01:19:52 -06:00
|
|
|
reg->location = node->location;
|
2013-01-05 04:13:26 -06:00
|
|
|
children.push_back(reg);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (reg->simplify(true, 1, -1, false)) { }
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-08-21 06:23:58 -05:00
|
|
|
AstNode *async_block = NULL;
|
|
|
|
while (mem2reg_as_needed_pass2(mem2reg_set, this, NULL, async_block)) { }
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2016-05-27 10:25:33 -05:00
|
|
|
vector<AstNode*> delnodes;
|
|
|
|
mem2reg_remove(mem2reg_set, delnodes);
|
|
|
|
|
|
|
|
for (auto node : delnodes)
|
|
|
|
delete node;
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
2023-04-04 15:59:44 -05:00
|
|
|
while (simplify(const_fold, 2, width_hint, sign_hint)) { }
|
2015-02-13 05:33:12 -06:00
|
|
|
recursion_counter--;
|
2013-01-05 04:13:26 -06:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
current_filename = filename;
|
|
|
|
|
|
|
|
// we do not look inside a task or function
|
2015-08-14 03:56:05 -05:00
|
|
|
// (but as soon as a task or function is instantiated we process the generated AST as usual)
|
2015-02-13 05:33:12 -06:00
|
|
|
if (type == AST_FUNCTION || type == AST_TASK) {
|
|
|
|
recursion_counter--;
|
2013-01-05 04:13:26 -06:00
|
|
|
return false;
|
2015-02-13 05:33:12 -06:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2015-08-14 03:56:05 -05:00
|
|
|
// deactivate all calls to non-synthesis system tasks
|
2016-03-21 10:19:51 -05:00
|
|
|
// note that $display, $finish, and $stop are used for synthesis-time DRC so they're not in this list
|
|
|
|
if ((type == AST_FCALL || type == AST_TCALL) && (str == "$strobe" || str == "$monitor" || str == "$time" ||
|
2015-01-15 06:08:19 -06:00
|
|
|
str == "$dumpfile" || str == "$dumpvars" || str == "$dumpon" || str == "$dumpoff" || str == "$dumpall")) {
|
2020-02-23 01:19:52 -06:00
|
|
|
log_file_warning(filename, location.first_line, "Ignoring call to system %s %s.\n", type == AST_FCALL ? "function" : "task", str.c_str());
|
2013-01-05 04:13:26 -06:00
|
|
|
delete_children();
|
|
|
|
str = std::string();
|
|
|
|
}
|
|
|
|
|
2020-11-29 02:57:07 -06:00
|
|
|
if ((type == AST_TCALL) &&
|
|
|
|
(str == "$display" || str == "$displayb" || str == "$displayh" || str == "$displayo" ||
|
|
|
|
str == "$write" || str == "$writeb" || str == "$writeh" || str == "$writeo"))
|
2015-09-17 22:34:56 -05:00
|
|
|
{
|
2020-11-29 08:34:17 -06:00
|
|
|
if (!current_always) {
|
|
|
|
log_file_warning(filename, location.first_line, "System task `%s' outside initial or always block is unsupported.\n", str.c_str());
|
2024-01-11 03:32:44 -06:00
|
|
|
delete_children();
|
|
|
|
str = std::string();
|
2020-11-29 08:34:17 -06:00
|
|
|
} else {
|
2024-01-11 03:32:44 -06:00
|
|
|
// simplify the expressions and convert them to a special cell later in genrtlil
|
2020-11-29 08:34:17 -06:00
|
|
|
for (auto node : children)
|
2023-04-04 15:59:44 -05:00
|
|
|
while (node->simplify(true, stage, -1, false)) {}
|
2024-01-11 03:32:44 -06:00
|
|
|
|
|
|
|
if (current_always->type == AST_INITIAL && !flag_nodisplay && stage == 2) {
|
|
|
|
int default_base = 10;
|
|
|
|
if (str.back() == 'b')
|
|
|
|
default_base = 2;
|
|
|
|
else if (str.back() == 'o')
|
|
|
|
default_base = 8;
|
|
|
|
else if (str.back() == 'h')
|
|
|
|
default_base = 16;
|
|
|
|
|
|
|
|
// when $display()/$write() functions are used in an initial block, print them during synthesis
|
|
|
|
Fmt fmt = processFormat(stage, /*sformat_like=*/false, default_base, /*first_arg_at=*/0, /*may_fail=*/true);
|
|
|
|
if (str.substr(0, 8) == "$display")
|
2024-03-28 01:30:16 -05:00
|
|
|
fmt.append_literal("\n");
|
2024-01-11 03:32:44 -06:00
|
|
|
log("%s", fmt.render().c_str());
|
|
|
|
}
|
|
|
|
|
2020-11-29 08:34:17 -06:00
|
|
|
return false;
|
|
|
|
}
|
2015-09-17 22:34:56 -05:00
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
// activate const folding if this is anything that must be evaluated statically (ranges, parameters, attributes, etc.)
|
2018-03-09 06:47:11 -06:00
|
|
|
if (type == AST_WIRE || type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_ENUM_ITEM || type == AST_DEFPARAM || type == AST_PARASET || type == AST_RANGE || type == AST_PREFIX || type == AST_TYPEDEF)
|
2014-02-14 13:45:30 -06:00
|
|
|
const_fold = true;
|
2018-03-09 06:47:11 -06:00
|
|
|
if (type == AST_IDENTIFIER && current_scope.count(str) > 0 && (current_scope[str]->type == AST_PARAMETER || current_scope[str]->type == AST_LOCALPARAM || current_scope[str]->type == AST_ENUM_ITEM))
|
2013-01-05 04:13:26 -06:00
|
|
|
const_fold = true;
|
|
|
|
|
|
|
|
std::map<std::string, AstNode*> backup_scope;
|
|
|
|
|
|
|
|
// create name resolution entries for all objects with names
|
|
|
|
// also merge multiple declarations for the same wire (e.g. "output foobar; reg foobar;")
|
2023-02-12 17:25:39 -06:00
|
|
|
if (type == AST_MODULE || type == AST_INTERFACE) {
|
2013-01-05 04:13:26 -06:00
|
|
|
current_scope.clear();
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
std::set<std::string> existing;
|
|
|
|
int counter = 0;
|
|
|
|
label_genblks(existing, counter);
|
2013-01-05 04:13:26 -06:00
|
|
|
std::map<std::string, AstNode*> this_wire_scope;
|
|
|
|
for (size_t i = 0; i < children.size(); i++) {
|
|
|
|
AstNode *node = children[i];
|
2019-09-19 14:43:13 -05:00
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
if (node->type == AST_WIRE) {
|
2019-03-02 14:36:46 -06:00
|
|
|
if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) {
|
|
|
|
for (auto c : node->children[0]->children) {
|
|
|
|
if (!c->is_simple_const_expr()) {
|
2020-04-02 11:51:32 -05:00
|
|
|
if (attributes.count(ID::dynports))
|
|
|
|
delete attributes.at(ID::dynports);
|
2023-04-05 04:00:07 -05:00
|
|
|
set_attribute(ID::dynports, AstNode::mkconst_int(1, true));
|
2019-03-02 14:36:46 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
if (this_wire_scope.count(node->str) > 0) {
|
|
|
|
AstNode *first_node = this_wire_scope[node->str];
|
2018-03-09 02:35:33 -06:00
|
|
|
if (first_node->is_input && node->is_reg)
|
|
|
|
goto wires_are_incompatible;
|
2013-03-23 12:54:31 -05:00
|
|
|
if (!node->is_input && !node->is_output && node->is_reg && node->children.size() == 0)
|
|
|
|
goto wires_are_compatible;
|
2015-01-15 05:53:12 -06:00
|
|
|
if (first_node->children.size() == 0 && node->children.size() == 1 && node->children[0]->type == AST_RANGE) {
|
|
|
|
AstNode *r = node->children[0];
|
|
|
|
if (r->range_valid && r->range_left == 0 && r->range_right == 0) {
|
|
|
|
delete r;
|
|
|
|
node->children.pop_back();
|
|
|
|
}
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
if (first_node->children.size() != node->children.size())
|
|
|
|
goto wires_are_incompatible;
|
|
|
|
for (size_t j = 0; j < node->children.size(); j++) {
|
|
|
|
AstNode *n1 = first_node->children[j], *n2 = node->children[j];
|
|
|
|
if (n1->type == AST_RANGE && n2->type == AST_RANGE && n1->range_valid && n2->range_valid) {
|
|
|
|
if (n1->range_left != n2->range_left)
|
|
|
|
goto wires_are_incompatible;
|
|
|
|
if (n1->range_right != n2->range_right)
|
|
|
|
goto wires_are_incompatible;
|
|
|
|
} else if (*n1 != *n2)
|
|
|
|
goto wires_are_incompatible;
|
|
|
|
}
|
|
|
|
if (first_node->range_left != node->range_left)
|
|
|
|
goto wires_are_incompatible;
|
|
|
|
if (first_node->range_right != node->range_right)
|
|
|
|
goto wires_are_incompatible;
|
|
|
|
if (first_node->port_id == 0 && (node->is_input || node->is_output))
|
|
|
|
goto wires_are_incompatible;
|
2013-03-23 12:54:31 -05:00
|
|
|
wires_are_compatible:
|
2013-01-05 04:13:26 -06:00
|
|
|
if (node->is_input)
|
|
|
|
first_node->is_input = true;
|
|
|
|
if (node->is_output)
|
|
|
|
first_node->is_output = true;
|
|
|
|
if (node->is_reg)
|
|
|
|
first_node->is_reg = true;
|
2018-03-09 02:35:33 -06:00
|
|
|
if (node->is_logic)
|
|
|
|
first_node->is_logic = true;
|
2013-01-05 04:13:26 -06:00
|
|
|
if (node->is_signed)
|
|
|
|
first_node->is_signed = true;
|
|
|
|
for (auto &it : node->attributes) {
|
|
|
|
if (first_node->attributes.count(it.first) > 0)
|
|
|
|
delete first_node->attributes[it.first];
|
2023-04-05 04:00:07 -05:00
|
|
|
first_node->set_attribute(it.first, it.second->clone());
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
children.erase(children.begin()+(i--));
|
|
|
|
did_something = true;
|
|
|
|
delete node;
|
|
|
|
continue;
|
2014-03-05 12:55:58 -06:00
|
|
|
wires_are_incompatible:
|
|
|
|
if (stage > 1)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Incompatible re-declaration of wire %s.\n", node->str.c_str());
|
2014-03-05 12:55:58 -06:00
|
|
|
continue;
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
this_wire_scope[node->str] = node;
|
|
|
|
}
|
2018-03-09 06:47:11 -06:00
|
|
|
// these nodes appear at the top level in a module and can define names
|
2013-01-05 04:13:26 -06:00
|
|
|
if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_GENVAR ||
|
2019-09-19 14:43:13 -05:00
|
|
|
node->type == AST_MEMORY || node->type == AST_FUNCTION || node->type == AST_TASK || node->type == AST_DPI_FUNCTION || node->type == AST_CELL ||
|
|
|
|
node->type == AST_TYPEDEF) {
|
2013-01-05 04:13:26 -06:00
|
|
|
backup_scope[node->str] = current_scope[node->str];
|
|
|
|
current_scope[node->str] = node;
|
|
|
|
}
|
2018-03-09 06:47:11 -06:00
|
|
|
if (node->type == AST_ENUM) {
|
2020-02-03 00:12:24 -06:00
|
|
|
current_scope[node->str] = node;
|
2018-03-09 06:47:11 -06:00
|
|
|
for (auto enode : node->children) {
|
|
|
|
log_assert(enode->type==AST_ENUM_ITEM);
|
2020-04-07 01:30:11 -05:00
|
|
|
if (current_scope.count(enode->str) == 0)
|
2018-03-09 06:47:11 -06:00
|
|
|
current_scope[enode->str] = enode;
|
2020-04-07 01:30:11 -05:00
|
|
|
else
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("enum item %s already exists\n", enode->str.c_str());
|
2018-03-09 06:47:11 -06:00
|
|
|
}
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
2013-11-24 12:40:23 -06:00
|
|
|
for (size_t i = 0; i < children.size(); i++) {
|
|
|
|
AstNode *node = children[i];
|
2019-09-19 14:43:13 -05:00
|
|
|
if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_MEMORY || node->type == AST_TYPEDEF)
|
2023-04-04 15:59:44 -05:00
|
|
|
while (node->simplify(true, 1, -1, false))
|
2014-03-05 12:45:33 -06:00
|
|
|
did_something = true;
|
2020-01-16 14:23:03 -06:00
|
|
|
if (node->type == AST_ENUM) {
|
2020-06-18 20:32:48 -05:00
|
|
|
for (auto enode : node->children){
|
2020-01-16 14:23:03 -06:00
|
|
|
log_assert(enode->type==AST_ENUM_ITEM);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (node->simplify(true, 1, -1, false))
|
2020-01-16 14:23:03 -06:00
|
|
|
did_something = true;
|
|
|
|
}
|
|
|
|
}
|
2013-11-24 12:40:23 -06:00
|
|
|
}
|
2022-01-06 23:04:00 -06:00
|
|
|
|
|
|
|
for (AstNode *child : children)
|
|
|
|
if (child->type == AST_ALWAYS &&
|
|
|
|
child->attributes.count(ID::always_comb))
|
|
|
|
check_auto_nosync(child);
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
2020-04-06 23:37:44 -05:00
|
|
|
// create name resolution entries for all objects with names
|
|
|
|
if (type == AST_PACKAGE) {
|
|
|
|
//add names to package scope
|
|
|
|
for (size_t i = 0; i < children.size(); i++) {
|
|
|
|
AstNode *node = children[i];
|
|
|
|
// these nodes appear at the top level in a package and can define names
|
2021-05-27 15:47:02 -05:00
|
|
|
if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_TYPEDEF || node->type == AST_FUNCTION || node->type == AST_TASK) {
|
2020-04-06 23:37:44 -05:00
|
|
|
current_scope[node->str] = node;
|
|
|
|
}
|
|
|
|
if (node->type == AST_ENUM) {
|
|
|
|
current_scope[node->str] = node;
|
|
|
|
for (auto enode : node->children) {
|
|
|
|
log_assert(enode->type==AST_ENUM_ITEM);
|
|
|
|
if (current_scope.count(enode->str) == 0)
|
|
|
|
current_scope[enode->str] = enode;
|
|
|
|
else
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("enum item %s already exists in package\n", enode->str.c_str());
|
2020-04-06 23:37:44 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
auto backup_current_block = current_block;
|
|
|
|
auto backup_current_block_child = current_block_child;
|
|
|
|
auto backup_current_top_block = current_top_block;
|
2015-02-14 03:49:30 -06:00
|
|
|
auto backup_current_always = current_always;
|
2016-09-06 10:34:42 -05:00
|
|
|
auto backup_current_always_clocked = current_always_clocked;
|
2015-02-14 03:49:30 -06:00
|
|
|
|
|
|
|
if (type == AST_ALWAYS || type == AST_INITIAL)
|
2016-09-06 10:34:42 -05:00
|
|
|
{
|
2017-12-02 11:52:05 -06:00
|
|
|
if (current_always != nullptr)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Invalid nesting of always blocks and/or initializations.\n");
|
2017-12-02 11:52:05 -06:00
|
|
|
|
2015-02-14 03:49:30 -06:00
|
|
|
current_always = this;
|
2016-09-06 10:34:42 -05:00
|
|
|
current_always_clocked = false;
|
|
|
|
|
|
|
|
if (type == AST_ALWAYS)
|
2017-10-10 04:59:32 -05:00
|
|
|
for (auto child : children) {
|
2016-09-06 10:34:42 -05:00
|
|
|
if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE)
|
|
|
|
current_always_clocked = true;
|
2017-10-10 04:59:32 -05:00
|
|
|
if (child->type == AST_EDGE && GetSize(child->children) == 1 &&
|
|
|
|
child->children[0]->type == AST_IDENTIFIER && child->children[0]->str == "\\$global_clock")
|
|
|
|
current_always_clocked = true;
|
|
|
|
}
|
2016-09-06 10:34:42 -05:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2021-10-19 19:46:26 -05:00
|
|
|
if (type == AST_CELL) {
|
|
|
|
bool lookup_suggested = false;
|
|
|
|
|
|
|
|
for (AstNode *child : children) {
|
|
|
|
// simplify any parameters to constants
|
|
|
|
if (child->type == AST_PARASET)
|
2023-04-04 15:59:44 -05:00
|
|
|
while (child->simplify(true, 1, -1, false)) { }
|
2021-10-19 19:46:26 -05:00
|
|
|
|
|
|
|
// look for patterns which _may_ indicate ambiguity requiring
|
|
|
|
// resolution of the underlying module
|
|
|
|
if (child->type == AST_ARGUMENT) {
|
|
|
|
if (child->children.size() != 1)
|
|
|
|
continue;
|
|
|
|
const AstNode *value = child->children[0];
|
|
|
|
if (value->type == AST_IDENTIFIER) {
|
|
|
|
const AstNode *elem = value->id2ast;
|
|
|
|
if (elem == nullptr) {
|
|
|
|
if (current_scope.count(value->str))
|
|
|
|
elem = current_scope.at(value->str);
|
|
|
|
else
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (elem->type == AST_MEMORY)
|
|
|
|
// need to determine is the is a read or wire
|
|
|
|
lookup_suggested = true;
|
|
|
|
else if (elem->type == AST_WIRE && elem->is_signed && !value->children.empty())
|
|
|
|
// this may be a fully sliced signed wire which needs
|
|
|
|
// to be indirected to produce an unsigned connection
|
|
|
|
lookup_suggested = true;
|
|
|
|
}
|
|
|
|
else if (contains_unbased_unsized(value))
|
|
|
|
// unbased unsized literals extend to width of the context
|
|
|
|
lookup_suggested = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
const RTLIL::Module *module = nullptr;
|
|
|
|
if (lookup_suggested)
|
|
|
|
module = lookup_cell_module();
|
|
|
|
if (module) {
|
|
|
|
size_t port_counter = 0;
|
|
|
|
for (AstNode *child : children) {
|
|
|
|
if (child->type != AST_ARGUMENT)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// determine the full name of port this argument is connected to
|
|
|
|
RTLIL::IdString port_name;
|
|
|
|
if (child->str.size())
|
|
|
|
port_name = child->str;
|
|
|
|
else {
|
|
|
|
if (port_counter >= module->ports.size())
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Cell instance has more ports than the module!\n");
|
2021-10-19 19:46:26 -05:00
|
|
|
port_name = module->ports[port_counter++];
|
|
|
|
}
|
|
|
|
|
|
|
|
// find the port's wire in the underlying module
|
|
|
|
const RTLIL::Wire *ref = module->wire(port_name);
|
|
|
|
if (ref == nullptr)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Cell instance refers to port %s which does not exist in module %s!.\n",
|
2021-10-19 19:46:26 -05:00
|
|
|
log_id(port_name), log_id(module->name));
|
|
|
|
|
|
|
|
// select the argument, if present
|
|
|
|
log_assert(child->children.size() <= 1);
|
|
|
|
if (child->children.empty())
|
|
|
|
continue;
|
|
|
|
AstNode *arg = child->children[0];
|
|
|
|
|
|
|
|
// plain identifiers never need indirection; this also prevents
|
|
|
|
// adding infinite levels of indirection
|
|
|
|
if (arg->type == AST_IDENTIFIER && arg->children.empty())
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// only add indirection for standard inputs or outputs
|
|
|
|
if (ref->port_input == ref->port_output)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
did_something = true;
|
|
|
|
|
|
|
|
// create the indirection wire
|
|
|
|
std::stringstream sstr;
|
2022-08-08 09:13:33 -05:00
|
|
|
sstr << "$indirect$" << ref->name.c_str() << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
|
2021-10-19 19:46:26 -05:00
|
|
|
std::string tmp_str = sstr.str();
|
|
|
|
add_wire_for_ref(ref, tmp_str);
|
|
|
|
|
|
|
|
AstNode *asgn = new AstNode(AST_ASSIGN);
|
|
|
|
current_ast_mod->children.push_back(asgn);
|
|
|
|
|
|
|
|
AstNode *ident = new AstNode(AST_IDENTIFIER);
|
|
|
|
ident->str = tmp_str;
|
|
|
|
child->children[0] = ident->clone();
|
|
|
|
|
|
|
|
if (ref->port_input && !ref->port_output) {
|
|
|
|
asgn->children.push_back(ident);
|
|
|
|
asgn->children.push_back(arg);
|
|
|
|
} else {
|
|
|
|
log_assert(!ref->port_input && ref->port_output);
|
|
|
|
asgn->children.push_back(arg);
|
|
|
|
asgn->children.push_back(ident);
|
|
|
|
}
|
2023-04-05 04:00:07 -05:00
|
|
|
asgn->fixup_hierarchy_flags();
|
2021-10-19 19:46:26 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2021-03-03 13:36:19 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-11-03 23:04:42 -06:00
|
|
|
int backup_width_hint = width_hint;
|
|
|
|
bool backup_sign_hint = sign_hint;
|
|
|
|
|
|
|
|
bool detect_width_simple = false;
|
|
|
|
bool child_0_is_self_determined = false;
|
|
|
|
bool child_1_is_self_determined = false;
|
2014-06-25 03:05:36 -05:00
|
|
|
bool child_2_is_self_determined = false;
|
2013-11-03 23:04:42 -06:00
|
|
|
bool children_are_self_determined = false;
|
|
|
|
bool reset_width_after_children = false;
|
|
|
|
|
|
|
|
switch (type)
|
|
|
|
{
|
|
|
|
case AST_ASSIGN_EQ:
|
|
|
|
case AST_ASSIGN_LE:
|
|
|
|
case AST_ASSIGN:
|
2023-04-04 15:59:44 -05:00
|
|
|
while (!children[0]->basic_prep && children[0]->simplify(false, stage, -1, false) == true)
|
2014-03-05 12:45:33 -06:00
|
|
|
did_something = true;
|
2023-04-04 15:59:44 -05:00
|
|
|
while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false) == true)
|
2014-03-05 12:45:33 -06:00
|
|
|
did_something = true;
|
2013-11-04 14:29:36 -06:00
|
|
|
children[0]->detectSignWidth(backup_width_hint, backup_sign_hint);
|
|
|
|
children[1]->detectSignWidth(width_hint, sign_hint);
|
2015-10-25 13:30:49 -05:00
|
|
|
width_hint = max(width_hint, backup_width_hint);
|
2013-11-03 23:04:42 -06:00
|
|
|
child_0_is_self_determined = true;
|
2018-06-05 09:44:24 -05:00
|
|
|
// test only once, before optimizations and memory mappings but after assignment LHS was mapped to an identifier
|
|
|
|
if (children[0]->id2ast && !children[0]->was_checked) {
|
|
|
|
if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && children[0]->id2ast->is_logic)
|
|
|
|
children[0]->id2ast->is_reg = true; // if logic type is used in a block asignment
|
|
|
|
if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && !children[0]->id2ast->is_reg)
|
2021-02-23 12:22:53 -06:00
|
|
|
log_warning("wire '%s' is assigned in a block at %s.\n", children[0]->str.c_str(), loc_string().c_str());
|
2018-11-01 09:25:24 -05:00
|
|
|
if (type == AST_ASSIGN && children[0]->id2ast->is_reg) {
|
|
|
|
bool is_rand_reg = false;
|
|
|
|
if (children[1]->type == AST_FCALL) {
|
|
|
|
if (children[1]->str == "\\$anyconst")
|
|
|
|
is_rand_reg = true;
|
|
|
|
if (children[1]->str == "\\$anyseq")
|
|
|
|
is_rand_reg = true;
|
|
|
|
if (children[1]->str == "\\$allconst")
|
|
|
|
is_rand_reg = true;
|
|
|
|
if (children[1]->str == "\\$allseq")
|
|
|
|
is_rand_reg = true;
|
|
|
|
}
|
|
|
|
if (!is_rand_reg)
|
2021-02-23 12:22:53 -06:00
|
|
|
log_warning("reg '%s' is assigned in a continuous assignment at %s.\n", children[0]->str.c_str(), loc_string().c_str());
|
2018-11-01 09:25:24 -05:00
|
|
|
}
|
2018-06-05 09:44:24 -05:00
|
|
|
children[0]->was_checked = true;
|
|
|
|
}
|
2013-11-03 23:04:42 -06:00
|
|
|
break;
|
|
|
|
|
2020-05-08 08:40:49 -05:00
|
|
|
case AST_STRUCT:
|
2020-05-12 08:25:33 -05:00
|
|
|
case AST_UNION:
|
2020-05-08 08:40:49 -05:00
|
|
|
if (!basic_prep) {
|
|
|
|
for (auto *node : children) {
|
|
|
|
// resolve any ranges
|
2023-04-04 15:59:44 -05:00
|
|
|
while (!node->basic_prep && node->simplify(true, stage, -1, false)) {
|
2020-05-08 08:40:49 -05:00
|
|
|
did_something = true;
|
|
|
|
}
|
|
|
|
}
|
2020-05-12 08:25:33 -05:00
|
|
|
// determine member offsets and widths
|
|
|
|
size_packed_struct(this, 0);
|
|
|
|
|
|
|
|
// instance rather than just a type in a typedef or outer struct?
|
|
|
|
if (!str.empty() && str[0] == '\\') {
|
|
|
|
// instance so add a wire for the packed structure
|
Handling of attributes for struct / union variables
(* nowrshmsk *) on a struct / union variable now affects dynamic
bit slice assignments to members of the struct / union.
(* nowrshmsk *) can in some cases yield significant resource savings; the
combination of pipeline shifting and indexed writes is an example of this.
Constructs similar to the one below can benefit from (* nowrshmsk *), and
in addition it is no longer necessary to split out the shift assignments
on separate lines in order to avoid the error message "ERROR: incompatible
mix of lookahead and non-lookahead IDs in LHS expression."
always_ff @(posedge clk) begin
if (rotate) begin
{ v5, v4, v3, v2, v1, v0 } <= { v4, v3, v2, v1, v0, v5 };
if (res) begin
v0.bytes <= '0;
end else if (w) begin
v0.bytes[addr] <= data;
end
end
end
2023-03-02 12:02:30 -06:00
|
|
|
auto wnode = make_packed_struct(this, str, attributes);
|
2020-05-12 08:25:33 -05:00
|
|
|
log_assert(current_ast_mod);
|
2020-05-08 08:40:49 -05:00
|
|
|
current_ast_mod->children.push_back(wnode);
|
|
|
|
}
|
2020-05-12 08:25:33 -05:00
|
|
|
basic_prep = true;
|
2020-05-08 08:40:49 -05:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_STRUCT_ITEM:
|
2023-01-29 13:22:00 -06:00
|
|
|
if (is_custom_type) {
|
2024-01-05 12:29:06 -06:00
|
|
|
log_assert(children.size() >= 1);
|
2023-01-29 13:22:00 -06:00
|
|
|
log_assert(children[0]->type == AST_WIRETYPE);
|
|
|
|
|
2024-01-05 12:29:06 -06:00
|
|
|
// Pretend it's just a wire in order to resolve the type.
|
|
|
|
type = AST_WIRE;
|
|
|
|
while (is_custom_type && simplify(const_fold, stage, width_hint, sign_hint)) {};
|
|
|
|
if (type == AST_WIRE)
|
2023-01-29 13:22:00 -06:00
|
|
|
type = AST_STRUCT_ITEM;
|
|
|
|
|
|
|
|
did_something = true;
|
|
|
|
}
|
|
|
|
log_assert(!is_custom_type);
|
2020-05-08 08:40:49 -05:00
|
|
|
break;
|
|
|
|
|
2018-03-09 06:47:11 -06:00
|
|
|
case AST_ENUM:
|
2020-02-03 00:08:16 -06:00
|
|
|
//log("\nENUM %s: %d child %d\n", str.c_str(), basic_prep, children[0]->basic_prep);
|
2018-03-09 06:47:11 -06:00
|
|
|
if (!basic_prep) {
|
|
|
|
for (auto item_node : children) {
|
2023-04-04 15:59:44 -05:00
|
|
|
while (!item_node->basic_prep && item_node->simplify(false, stage, -1, false))
|
2018-03-09 06:47:11 -06:00
|
|
|
did_something = true;
|
|
|
|
}
|
|
|
|
// allocate values (called more than once)
|
|
|
|
allocateDefaultEnumValues();
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2013-11-07 02:58:15 -06:00
|
|
|
case AST_PARAMETER:
|
|
|
|
case AST_LOCALPARAM:
|
2022-02-14 07:34:20 -06:00
|
|
|
// if parameter is implicit type which is the typename of a struct or union,
|
|
|
|
// save information about struct in wiretype attribute
|
|
|
|
if (children[0]->type == AST_IDENTIFIER && current_scope.count(children[0]->str) > 0) {
|
|
|
|
auto item_node = current_scope[children[0]->str];
|
|
|
|
if (item_node->type == AST_STRUCT || item_node->type == AST_UNION) {
|
2023-04-05 04:00:07 -05:00
|
|
|
set_attribute(ID::wiretype, item_node->clone());
|
2022-02-14 07:34:20 -06:00
|
|
|
size_packed_struct(attributes[ID::wiretype], 0);
|
|
|
|
add_members_to_scope(attributes[ID::wiretype], str);
|
|
|
|
}
|
|
|
|
}
|
2023-04-04 15:59:44 -05:00
|
|
|
while (!children[0]->basic_prep && children[0]->simplify(false, stage, -1, false) == true)
|
2014-03-05 12:45:33 -06:00
|
|
|
did_something = true;
|
2013-11-07 02:58:15 -06:00
|
|
|
children[0]->detectSignWidth(width_hint, sign_hint);
|
2014-06-14 05:00:47 -05:00
|
|
|
if (children.size() > 1 && children[1]->type == AST_RANGE) {
|
2023-04-04 15:59:44 -05:00
|
|
|
while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false) == true)
|
2014-03-05 12:45:33 -06:00
|
|
|
did_something = true;
|
2013-11-07 02:58:15 -06:00
|
|
|
if (!children[1]->range_valid)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Non-constant width range on parameter decl.\n");
|
2015-10-25 13:30:49 -05:00
|
|
|
width_hint = max(width_hint, children[1]->range_left - children[1]->range_right + 1);
|
2013-11-07 02:58:15 -06:00
|
|
|
}
|
|
|
|
break;
|
2020-02-03 00:08:16 -06:00
|
|
|
case AST_ENUM_ITEM:
|
2023-04-04 15:59:44 -05:00
|
|
|
while (!children[0]->basic_prep && children[0]->simplify(false, stage, -1, false))
|
2020-02-03 00:08:16 -06:00
|
|
|
did_something = true;
|
|
|
|
children[0]->detectSignWidth(width_hint, sign_hint);
|
|
|
|
if (children.size() > 1 && children[1]->type == AST_RANGE) {
|
2023-04-04 15:59:44 -05:00
|
|
|
while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false))
|
2020-02-03 00:08:16 -06:00
|
|
|
did_something = true;
|
|
|
|
if (!children[1]->range_valid)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Non-constant width range on enum item decl.\n");
|
2020-02-03 00:08:16 -06:00
|
|
|
width_hint = max(width_hint, children[1]->range_left - children[1]->range_right + 1);
|
|
|
|
}
|
|
|
|
break;
|
2013-11-07 02:58:15 -06:00
|
|
|
|
2014-02-01 06:50:23 -06:00
|
|
|
case AST_TO_BITS:
|
2013-11-03 23:04:42 -06:00
|
|
|
case AST_TO_SIGNED:
|
|
|
|
case AST_TO_UNSIGNED:
|
2020-04-29 07:28:04 -05:00
|
|
|
case AST_SELFSZ:
|
2020-06-14 17:15:59 -05:00
|
|
|
case AST_CAST_SIZE:
|
2013-11-03 23:04:42 -06:00
|
|
|
case AST_CONCAT:
|
|
|
|
case AST_REPLICATE:
|
|
|
|
case AST_REDUCE_AND:
|
|
|
|
case AST_REDUCE_OR:
|
|
|
|
case AST_REDUCE_XOR:
|
|
|
|
case AST_REDUCE_XNOR:
|
|
|
|
case AST_REDUCE_BOOL:
|
|
|
|
detect_width_simple = true;
|
|
|
|
children_are_self_determined = true;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_NEG:
|
|
|
|
case AST_BIT_NOT:
|
|
|
|
case AST_POS:
|
|
|
|
case AST_BIT_AND:
|
|
|
|
case AST_BIT_OR:
|
|
|
|
case AST_BIT_XOR:
|
|
|
|
case AST_BIT_XNOR:
|
|
|
|
case AST_ADD:
|
|
|
|
case AST_SUB:
|
|
|
|
case AST_MUL:
|
|
|
|
case AST_DIV:
|
|
|
|
case AST_MOD:
|
|
|
|
detect_width_simple = true;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_SHIFT_LEFT:
|
|
|
|
case AST_SHIFT_RIGHT:
|
|
|
|
case AST_SHIFT_SLEFT:
|
|
|
|
case AST_SHIFT_SRIGHT:
|
|
|
|
case AST_POW:
|
|
|
|
detect_width_simple = true;
|
|
|
|
child_1_is_self_determined = true;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_LT:
|
|
|
|
case AST_LE:
|
|
|
|
case AST_EQ:
|
|
|
|
case AST_NE:
|
2013-12-27 06:50:08 -06:00
|
|
|
case AST_EQX:
|
|
|
|
case AST_NEX:
|
2013-11-03 23:04:42 -06:00
|
|
|
case AST_GE:
|
|
|
|
case AST_GT:
|
|
|
|
width_hint = -1;
|
|
|
|
sign_hint = true;
|
|
|
|
for (auto child : children) {
|
2023-04-04 15:59:44 -05:00
|
|
|
while (!child->basic_prep && child->simplify(false, stage, -1, false) == true)
|
2014-03-05 12:45:33 -06:00
|
|
|
did_something = true;
|
2013-11-03 23:04:42 -06:00
|
|
|
child->detectSignWidthWorker(width_hint, sign_hint);
|
|
|
|
}
|
|
|
|
reset_width_after_children = true;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_LOGIC_AND:
|
|
|
|
case AST_LOGIC_OR:
|
|
|
|
case AST_LOGIC_NOT:
|
|
|
|
detect_width_simple = true;
|
|
|
|
children_are_self_determined = true;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_TERNARY:
|
|
|
|
child_0_is_self_determined = true;
|
|
|
|
break;
|
2015-07-02 04:14:30 -05:00
|
|
|
|
2013-11-03 23:04:42 -06:00
|
|
|
case AST_MEMRD:
|
|
|
|
detect_width_simple = true;
|
|
|
|
children_are_self_determined = true;
|
|
|
|
break;
|
|
|
|
|
2016-09-18 18:30:07 -05:00
|
|
|
case AST_FCALL:
|
|
|
|
case AST_TCALL:
|
|
|
|
children_are_self_determined = true;
|
|
|
|
break;
|
|
|
|
|
2013-11-03 23:04:42 -06:00
|
|
|
default:
|
2013-11-02 07:00:17 -05:00
|
|
|
width_hint = -1;
|
|
|
|
sign_hint = false;
|
|
|
|
}
|
2013-11-03 23:04:42 -06:00
|
|
|
|
|
|
|
if (detect_width_simple && width_hint < 0) {
|
2014-06-06 17:02:05 -05:00
|
|
|
if (type == AST_REPLICATE)
|
2023-04-04 15:59:44 -05:00
|
|
|
while (children[0]->simplify(true, stage, -1, false) == true)
|
2014-06-06 17:02:05 -05:00
|
|
|
did_something = true;
|
2013-11-03 23:04:42 -06:00
|
|
|
for (auto child : children)
|
2023-04-04 15:59:44 -05:00
|
|
|
while (!child->basic_prep && child->simplify(false, stage, -1, false) == true)
|
2014-03-05 12:45:33 -06:00
|
|
|
did_something = true;
|
2013-11-03 23:04:42 -06:00
|
|
|
detectSignWidth(width_hint, sign_hint);
|
2013-11-02 07:00:17 -05:00
|
|
|
}
|
|
|
|
|
2016-09-18 18:30:07 -05:00
|
|
|
if (type == AST_FCALL && str == "\\$past")
|
|
|
|
detectSignWidth(width_hint, sign_hint);
|
|
|
|
|
2014-06-25 03:05:36 -05:00
|
|
|
if (type == AST_TERNARY) {
|
2021-02-12 13:25:34 -06:00
|
|
|
if (width_hint < 0) {
|
2023-04-04 15:59:44 -05:00
|
|
|
while (!children[0]->basic_prep && children[0]->simplify(true, stage, -1, false))
|
2021-02-12 13:25:34 -06:00
|
|
|
did_something = true;
|
|
|
|
|
|
|
|
bool backup_unevaluated_tern_branch = unevaluated_tern_branch;
|
|
|
|
AstNode *chosen = get_tern_choice().first;
|
|
|
|
|
|
|
|
unevaluated_tern_branch = backup_unevaluated_tern_branch || chosen == children[2];
|
2023-04-04 15:59:44 -05:00
|
|
|
while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false))
|
2021-02-12 13:25:34 -06:00
|
|
|
did_something = true;
|
|
|
|
|
|
|
|
unevaluated_tern_branch = backup_unevaluated_tern_branch || chosen == children[1];
|
2023-04-04 15:59:44 -05:00
|
|
|
while (!children[2]->basic_prep && children[2]->simplify(false, stage, -1, false))
|
2021-02-12 13:25:34 -06:00
|
|
|
did_something = true;
|
|
|
|
|
|
|
|
unevaluated_tern_branch = backup_unevaluated_tern_branch;
|
|
|
|
detectSignWidth(width_hint, sign_hint);
|
|
|
|
}
|
2014-06-25 03:05:36 -05:00
|
|
|
int width_hint_left, width_hint_right;
|
|
|
|
bool sign_hint_left, sign_hint_right;
|
|
|
|
bool found_real_left, found_real_right;
|
|
|
|
children[1]->detectSignWidth(width_hint_left, sign_hint_left, &found_real_left);
|
|
|
|
children[2]->detectSignWidth(width_hint_right, sign_hint_right, &found_real_right);
|
|
|
|
if (found_real_left || found_real_right) {
|
|
|
|
child_1_is_self_determined = true;
|
|
|
|
child_2_is_self_determined = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-04-21 08:31:54 -05:00
|
|
|
if (type == AST_CONDX && children.size() > 0 && children.at(0)->type == AST_CONSTANT) {
|
|
|
|
for (auto &bit : children.at(0)->bits)
|
|
|
|
if (bit == State::Sz || bit == State::Sx)
|
|
|
|
bit = State::Sa;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (type == AST_CONDZ && children.size() > 0 && children.at(0)->type == AST_CONSTANT) {
|
|
|
|
for (auto &bit : children.at(0)->bits)
|
|
|
|
if (bit == State::Sz)
|
|
|
|
bit = State::Sa;
|
|
|
|
}
|
|
|
|
|
2014-10-29 02:29:51 -05:00
|
|
|
if (const_fold && type == AST_CASE)
|
|
|
|
{
|
2021-03-25 13:06:05 -05:00
|
|
|
detectSignWidth(width_hint, sign_hint);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (children[0]->simplify(const_fold, stage, width_hint, sign_hint)) { }
|
2014-10-29 02:29:51 -05:00
|
|
|
if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) {
|
2022-05-24 07:32:14 -05:00
|
|
|
children[0]->is_signed = sign_hint;
|
2021-03-25 13:06:05 -05:00
|
|
|
RTLIL::Const case_expr = children[0]->bitsAsConst(width_hint, sign_hint);
|
2014-10-29 02:29:51 -05:00
|
|
|
std::vector<AstNode*> new_children;
|
|
|
|
new_children.push_back(children[0]);
|
|
|
|
for (int i = 1; i < GetSize(children); i++) {
|
|
|
|
AstNode *child = children[i];
|
2016-04-21 08:31:54 -05:00
|
|
|
log_assert(child->type == AST_COND || child->type == AST_CONDX || child->type == AST_CONDZ);
|
2014-10-29 02:29:51 -05:00
|
|
|
for (auto v : child->children) {
|
|
|
|
if (v->type == AST_DEFAULT)
|
|
|
|
goto keep_const_cond;
|
|
|
|
if (v->type == AST_BLOCK)
|
|
|
|
continue;
|
2023-04-04 15:59:44 -05:00
|
|
|
while (v->simplify(const_fold, stage, width_hint, sign_hint)) { }
|
2014-10-29 02:29:51 -05:00
|
|
|
if (v->type == AST_CONSTANT && v->bits_only_01()) {
|
2021-03-25 13:06:05 -05:00
|
|
|
RTLIL::Const case_item_expr = v->bitsAsConst(width_hint, sign_hint);
|
|
|
|
RTLIL::Const match = const_eq(case_expr, case_item_expr, sign_hint, sign_hint, 1);
|
|
|
|
log_assert(match.bits.size() == 1);
|
|
|
|
if (match.bits.front() == RTLIL::State::S1) {
|
2014-10-29 02:29:51 -05:00
|
|
|
while (i+1 < GetSize(children))
|
|
|
|
delete children[++i];
|
|
|
|
goto keep_const_cond;
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
goto keep_const_cond;
|
|
|
|
}
|
|
|
|
if (0)
|
|
|
|
keep_const_cond:
|
|
|
|
new_children.push_back(child);
|
|
|
|
else
|
|
|
|
delete child;
|
|
|
|
}
|
|
|
|
new_children.swap(children);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-02-23 09:48:29 -06:00
|
|
|
dict<std::string, pool<int>> backup_memwr_visible;
|
|
|
|
dict<std::string, pool<int>> final_memwr_visible;
|
|
|
|
|
|
|
|
if (type == AST_CASE && stage == 2) {
|
|
|
|
backup_memwr_visible = current_memwr_visible;
|
|
|
|
final_memwr_visible = current_memwr_visible;
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
// simplify all children first
|
|
|
|
// (iterate by index as e.g. auto wires can add new children in the process)
|
|
|
|
for (size_t i = 0; i < children.size(); i++) {
|
|
|
|
bool did_something_here = true;
|
2019-02-24 13:09:41 -06:00
|
|
|
bool backup_flag_autowire = flag_autowire;
|
2021-02-12 13:25:34 -06:00
|
|
|
bool backup_unevaluated_tern_branch = unevaluated_tern_branch;
|
2013-01-05 04:13:26 -06:00
|
|
|
if ((type == AST_GENFOR || type == AST_FOR) && i >= 3)
|
|
|
|
break;
|
2013-12-04 14:06:54 -06:00
|
|
|
if ((type == AST_GENIF || type == AST_GENCASE) && i >= 1)
|
2013-01-05 04:13:26 -06:00
|
|
|
break;
|
2013-03-26 03:44:54 -05:00
|
|
|
if (type == AST_GENBLOCK)
|
|
|
|
break;
|
2022-08-30 06:58:09 -05:00
|
|
|
if (type == AST_CELLARRAY && children[i]->type == AST_CELL)
|
|
|
|
continue;
|
2013-12-04 02:10:16 -06:00
|
|
|
if (type == AST_BLOCK && !str.empty())
|
|
|
|
break;
|
2013-02-26 06:18:22 -06:00
|
|
|
if (type == AST_PREFIX && i >= 1)
|
|
|
|
break;
|
2019-02-24 13:09:41 -06:00
|
|
|
if (type == AST_DEFPARAM && i == 0)
|
|
|
|
flag_autowire = true;
|
2021-02-12 13:25:34 -06:00
|
|
|
if (type == AST_TERNARY && i > 0 && !unevaluated_tern_branch) {
|
|
|
|
AstNode *chosen = get_tern_choice().first;
|
|
|
|
unevaluated_tern_branch = chosen && chosen != children[i];
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
while (did_something_here && i < children.size()) {
|
2023-04-04 15:59:44 -05:00
|
|
|
bool const_fold_here = const_fold;
|
2013-11-02 07:00:17 -05:00
|
|
|
int width_hint_here = width_hint;
|
|
|
|
bool sign_hint_here = sign_hint;
|
2014-06-06 17:02:05 -05:00
|
|
|
if (i == 0 && (type == AST_REPLICATE || type == AST_WIRE))
|
2023-04-04 15:59:44 -05:00
|
|
|
const_fold_here = true;
|
2013-11-07 07:08:53 -06:00
|
|
|
if (type == AST_PARAMETER || type == AST_LOCALPARAM)
|
|
|
|
const_fold_here = true;
|
2013-01-05 04:13:26 -06:00
|
|
|
if (type == AST_BLOCK) {
|
|
|
|
current_block = this;
|
|
|
|
current_block_child = children[i];
|
|
|
|
}
|
2013-03-31 04:19:11 -05:00
|
|
|
if ((type == AST_ALWAYS || type == AST_INITIAL) && children[i]->type == AST_BLOCK)
|
2013-01-05 04:13:26 -06:00
|
|
|
current_top_block = children[i];
|
2013-11-03 23:04:42 -06:00
|
|
|
if (i == 0 && child_0_is_self_determined)
|
|
|
|
width_hint_here = -1, sign_hint_here = false;
|
|
|
|
if (i == 1 && child_1_is_self_determined)
|
|
|
|
width_hint_here = -1, sign_hint_here = false;
|
2014-06-25 03:05:36 -05:00
|
|
|
if (i == 2 && child_2_is_self_determined)
|
|
|
|
width_hint_here = -1, sign_hint_here = false;
|
2013-11-03 23:04:42 -06:00
|
|
|
if (children_are_self_determined)
|
|
|
|
width_hint_here = -1, sign_hint_here = false;
|
2023-04-04 15:59:44 -05:00
|
|
|
did_something_here = children[i]->simplify(const_fold_here, stage, width_hint_here, sign_hint_here);
|
2013-01-05 04:13:26 -06:00
|
|
|
if (did_something_here)
|
|
|
|
did_something = true;
|
2014-07-11 06:05:53 -05:00
|
|
|
}
|
|
|
|
if (stage == 2 && children[i]->type == AST_INITIAL && current_ast_mod != this) {
|
|
|
|
current_ast_mod->children.push_back(children[i]);
|
|
|
|
children.erase(children.begin() + (i--));
|
|
|
|
did_something = true;
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
2019-02-24 13:09:41 -06:00
|
|
|
flag_autowire = backup_flag_autowire;
|
2021-02-12 13:25:34 -06:00
|
|
|
unevaluated_tern_branch = backup_unevaluated_tern_branch;
|
2021-02-23 09:48:29 -06:00
|
|
|
if (stage == 2 && type == AST_CASE) {
|
|
|
|
for (auto &x : current_memwr_visible) {
|
|
|
|
for (int y : x.second)
|
|
|
|
final_memwr_visible[x.first].insert(y);
|
|
|
|
}
|
|
|
|
current_memwr_visible = backup_memwr_visible;
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
for (auto &attr : attributes) {
|
2023-04-04 15:59:44 -05:00
|
|
|
while (attr.second->simplify(true, stage, -1, false))
|
2014-03-05 12:45:33 -06:00
|
|
|
did_something = true;
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
2021-02-23 09:48:29 -06:00
|
|
|
if (type == AST_CASE && stage == 2) {
|
|
|
|
current_memwr_visible = final_memwr_visible;
|
|
|
|
}
|
|
|
|
if (type == AST_ALWAYS && stage == 2) {
|
|
|
|
current_memwr_visible.clear();
|
|
|
|
current_memwr_count.clear();
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2013-11-03 23:04:42 -06:00
|
|
|
if (reset_width_after_children) {
|
|
|
|
width_hint = backup_width_hint;
|
|
|
|
sign_hint = backup_sign_hint;
|
|
|
|
if (width_hint < 0)
|
|
|
|
detectSignWidth(width_hint, sign_hint);
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
current_block = backup_current_block;
|
|
|
|
current_block_child = backup_current_block_child;
|
|
|
|
current_top_block = backup_current_top_block;
|
2015-02-14 03:49:30 -06:00
|
|
|
current_always = backup_current_always;
|
2016-09-06 10:34:42 -05:00
|
|
|
current_always_clocked = backup_current_always_clocked;
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
for (auto it = backup_scope.begin(); it != backup_scope.end(); it++) {
|
|
|
|
if (it->second == NULL)
|
|
|
|
current_scope.erase(it->first);
|
|
|
|
else
|
|
|
|
current_scope[it->first] = it->second;
|
|
|
|
}
|
|
|
|
|
|
|
|
current_filename = filename;
|
|
|
|
|
2023-02-12 17:25:39 -06:00
|
|
|
if (type == AST_MODULE || type == AST_INTERFACE)
|
2013-01-05 04:13:26 -06:00
|
|
|
current_scope.clear();
|
|
|
|
|
2013-07-04 07:12:33 -05:00
|
|
|
// convert defparam nodes to cell parameters
|
2016-11-15 06:35:19 -06:00
|
|
|
if (type == AST_DEFPARAM && !children.empty())
|
|
|
|
{
|
|
|
|
if (children[0]->type != AST_IDENTIFIER)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Module name in defparam contains non-constant expressions!\n");
|
2016-11-15 06:35:19 -06:00
|
|
|
|
|
|
|
string modname, paramname = children[0]->str;
|
|
|
|
|
|
|
|
size_t pos = paramname.rfind('.');
|
|
|
|
|
|
|
|
while (pos != 0 && pos != std::string::npos)
|
|
|
|
{
|
|
|
|
modname = paramname.substr(0, pos);
|
|
|
|
|
|
|
|
if (current_scope.count(modname))
|
|
|
|
break;
|
|
|
|
|
|
|
|
pos = paramname.rfind('.', pos - 1);
|
|
|
|
}
|
|
|
|
|
2013-07-04 07:12:33 -05:00
|
|
|
if (pos == std::string::npos)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Can't find object for defparam `%s`!\n", RTLIL::unescape_id(paramname).c_str());
|
2016-11-15 06:35:19 -06:00
|
|
|
|
|
|
|
paramname = "\\" + paramname.substr(pos+1);
|
|
|
|
|
|
|
|
if (current_scope.at(modname)->type != AST_CELL)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Defparam argument `%s . %s` does not match a cell!\n",
|
2018-11-04 03:19:32 -06:00
|
|
|
RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paramname).c_str());
|
2016-11-15 06:35:19 -06:00
|
|
|
|
|
|
|
AstNode *paraset = new AstNode(AST_PARASET, children[1]->clone(), GetSize(children) > 2 ? children[2]->clone() : NULL);
|
|
|
|
paraset->str = paramname;
|
|
|
|
|
|
|
|
AstNode *cell = current_scope.at(modname);
|
2013-07-04 07:12:33 -05:00
|
|
|
cell->children.insert(cell->children.begin() + 1, paraset);
|
2016-11-15 06:35:19 -06:00
|
|
|
delete_children();
|
2013-07-04 07:12:33 -05:00
|
|
|
}
|
|
|
|
|
2019-09-19 14:43:13 -05:00
|
|
|
// resolve typedefs
|
|
|
|
if (type == AST_TYPEDEF) {
|
|
|
|
log_assert(children.size() == 1);
|
2020-05-08 08:40:49 -05:00
|
|
|
auto type_node = children[0];
|
2020-05-12 08:25:33 -05:00
|
|
|
log_assert(type_node->type == AST_WIRE || type_node->type == AST_MEMORY || type_node->type == AST_STRUCT || type_node->type == AST_UNION);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (type_node->simplify(const_fold, stage, width_hint, sign_hint)) {
|
2019-09-20 05:39:15 -05:00
|
|
|
did_something = true;
|
2020-05-08 08:40:49 -05:00
|
|
|
}
|
|
|
|
log_assert(!type_node->is_custom_type);
|
2019-09-19 14:43:13 -05:00
|
|
|
}
|
|
|
|
|
2019-09-19 15:07:20 -05:00
|
|
|
// resolve types of wires
|
2019-09-20 05:46:37 -05:00
|
|
|
if (type == AST_WIRE || type == AST_MEMORY) {
|
2019-09-19 14:43:13 -05:00
|
|
|
if (is_custom_type) {
|
2019-09-20 05:46:37 -05:00
|
|
|
log_assert(children.size() >= 1);
|
2019-09-19 14:43:13 -05:00
|
|
|
log_assert(children[0]->type == AST_WIRETYPE);
|
2020-05-08 08:40:49 -05:00
|
|
|
auto type_name = children[0]->str;
|
|
|
|
if (!current_scope.count(type_name)) {
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Unknown identifier `%s' used as type name\n", type_name.c_str());
|
2020-05-08 08:40:49 -05:00
|
|
|
}
|
|
|
|
AstNode *resolved_type_node = current_scope.at(type_name);
|
|
|
|
if (resolved_type_node->type != AST_TYPEDEF)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("`%s' does not name a type\n", type_name.c_str());
|
2020-05-08 08:40:49 -05:00
|
|
|
log_assert(resolved_type_node->children.size() == 1);
|
|
|
|
AstNode *template_node = resolved_type_node->children[0];
|
|
|
|
|
2023-12-31 18:18:00 -06:00
|
|
|
// Resolve the typedef from the bottom up, recursing within the current
|
|
|
|
// block of code. Defer further simplification until the complete type is
|
|
|
|
// resolved.
|
|
|
|
while (template_node->is_custom_type && template_node->simplify(const_fold, stage, width_hint, sign_hint)) {};
|
2020-05-08 08:40:49 -05:00
|
|
|
|
2023-01-29 13:22:00 -06:00
|
|
|
if (!str.empty() && str[0] == '\\' && (template_node->type == AST_STRUCT || template_node->type == AST_UNION)) {
|
|
|
|
// replace instance with wire representing the packed structure
|
Handling of attributes for struct / union variables
(* nowrshmsk *) on a struct / union variable now affects dynamic
bit slice assignments to members of the struct / union.
(* nowrshmsk *) can in some cases yield significant resource savings; the
combination of pipeline shifting and indexed writes is an example of this.
Constructs similar to the one below can benefit from (* nowrshmsk *), and
in addition it is no longer necessary to split out the shift assignments
on separate lines in order to avoid the error message "ERROR: incompatible
mix of lookahead and non-lookahead IDs in LHS expression."
always_ff @(posedge clk) begin
if (rotate) begin
{ v5, v4, v3, v2, v1, v0 } <= { v4, v3, v2, v1, v0, v5 };
if (res) begin
v0.bytes <= '0;
end else if (w) begin
v0.bytes[addr] <= data;
end
end
end
2023-03-02 12:02:30 -06:00
|
|
|
newNode = make_packed_struct(template_node, str, attributes);
|
2023-04-05 04:00:07 -05:00
|
|
|
newNode->set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str));
|
2020-06-09 02:53:00 -05:00
|
|
|
// add original input/output attribute to resolved wire
|
|
|
|
newNode->is_input = this->is_input;
|
|
|
|
newNode->is_output = this->is_output;
|
2020-05-08 08:40:49 -05:00
|
|
|
current_scope[str] = this;
|
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
2023-12-31 18:18:00 -06:00
|
|
|
// Prepare replacement node.
|
|
|
|
newNode = template_node->clone();
|
|
|
|
newNode->str = str;
|
|
|
|
newNode->set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str));
|
|
|
|
newNode->is_input = is_input;
|
|
|
|
newNode->is_output = is_output;
|
|
|
|
newNode->is_wand = is_wand;
|
|
|
|
newNode->is_wor = is_wor;
|
|
|
|
for (auto &pair : attributes)
|
|
|
|
newNode->set_attribute(pair.first, pair.second->clone());
|
2019-09-19 14:43:13 -05:00
|
|
|
|
2023-12-31 18:18:00 -06:00
|
|
|
// if an enum then add attributes to support simulator tracing
|
|
|
|
newNode->annotateTypedEnums(template_node);
|
2020-05-08 08:40:49 -05:00
|
|
|
|
2023-12-31 18:18:00 -06:00
|
|
|
bool add_packed_dimensions = (type == AST_WIRE && GetSize(children) > 1) || (type == AST_MEMORY && GetSize(children) > 2);
|
2020-05-08 08:40:49 -05:00
|
|
|
|
2023-12-31 18:18:00 -06:00
|
|
|
// Cannot add packed dimensions if unpacked dimensions are already specified.
|
|
|
|
if (add_packed_dimensions && newNode->type == AST_MEMORY)
|
|
|
|
input_error("Cannot extend unpacked type `%s' with packed dimensions\n", type_name.c_str());
|
2019-09-20 05:46:37 -05:00
|
|
|
|
2023-12-31 18:18:00 -06:00
|
|
|
// Add packed dimensions.
|
|
|
|
if (add_packed_dimensions) {
|
|
|
|
AstNode *packed = children[1];
|
|
|
|
if (newNode->children.empty())
|
|
|
|
newNode->children.insert(newNode->children.begin(), packed->clone());
|
|
|
|
else
|
|
|
|
prepend_ranges(newNode->children[0], packed);
|
|
|
|
}
|
2018-03-09 06:47:11 -06:00
|
|
|
|
2023-12-31 18:18:00 -06:00
|
|
|
// Add unpacked dimensions.
|
|
|
|
if (type == AST_MEMORY) {
|
|
|
|
AstNode *unpacked = children.back();
|
|
|
|
if (GetSize(newNode->children) < 2)
|
|
|
|
newNode->children.push_back(unpacked->clone());
|
|
|
|
else
|
|
|
|
prepend_ranges(newNode->children[1], unpacked);
|
|
|
|
newNode->type = type;
|
2019-09-20 05:46:37 -05:00
|
|
|
}
|
2023-12-31 18:18:00 -06:00
|
|
|
|
|
|
|
// Prepare to generate dimensions metadata for the resolved type.
|
|
|
|
newNode->dimensions.clear();
|
|
|
|
newNode->unpacked_dimensions = 0;
|
|
|
|
|
|
|
|
goto apply_newNode;
|
2019-09-19 14:43:13 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-09-19 15:07:20 -05:00
|
|
|
// resolve types of parameters
|
|
|
|
if (type == AST_LOCALPARAM || type == AST_PARAMETER) {
|
|
|
|
if (is_custom_type) {
|
2023-12-31 18:18:00 -06:00
|
|
|
log_assert(children.size() >= 2);
|
2019-09-19 15:07:20 -05:00
|
|
|
log_assert(children[1]->type == AST_WIRETYPE);
|
2024-01-05 12:29:06 -06:00
|
|
|
|
|
|
|
// Pretend it's just a wire in order to resolve the type in the code block above.
|
2023-12-31 18:18:00 -06:00
|
|
|
AstNodeType param_type = type;
|
|
|
|
type = AST_WIRE;
|
|
|
|
AstNode *expr = children[0];
|
|
|
|
children.erase(children.begin());
|
2024-01-05 12:29:06 -06:00
|
|
|
while (is_custom_type && simplify(const_fold, stage, width_hint, sign_hint)) {};
|
2023-12-31 18:18:00 -06:00
|
|
|
type = param_type;
|
|
|
|
children.insert(children.begin(), expr);
|
2024-01-05 12:29:06 -06:00
|
|
|
|
2023-12-31 18:18:00 -06:00
|
|
|
if (children[1]->type == AST_MEMORY)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("unpacked array type `%s' cannot be used for a parameter\n", children[1]->str.c_str());
|
2023-04-05 04:00:07 -05:00
|
|
|
fixup_hierarchy_flags();
|
2019-09-20 05:39:15 -05:00
|
|
|
did_something = true;
|
2019-09-19 15:07:20 -05:00
|
|
|
}
|
|
|
|
log_assert(!is_custom_type);
|
2018-03-09 06:47:11 -06:00
|
|
|
}
|
2019-09-19 15:07:20 -05:00
|
|
|
|
2013-02-26 06:18:22 -06:00
|
|
|
// resolve constant prefixes
|
|
|
|
if (type == AST_PREFIX) {
|
|
|
|
if (children[0]->type != AST_CONSTANT) {
|
2013-11-07 07:08:53 -06:00
|
|
|
// dumpAst(NULL, "> ");
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Index in generate block prefix syntax is not constant!\n");
|
2013-02-26 06:18:22 -06:00
|
|
|
}
|
2015-09-22 13:52:02 -05:00
|
|
|
if (children[1]->type == AST_PREFIX)
|
2023-04-04 15:59:44 -05:00
|
|
|
children[1]->simplify(const_fold, stage, width_hint, sign_hint);
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(children[1]->type == AST_IDENTIFIER);
|
2013-02-26 06:18:22 -06:00
|
|
|
newNode = children[1]->clone();
|
2013-11-20 06:57:40 -06:00
|
|
|
const char *second_part = children[1]->str.c_str();
|
|
|
|
if (second_part[0] == '\\')
|
|
|
|
second_part++;
|
|
|
|
newNode->str = stringf("%s[%d].%s", str.c_str(), children[0]->integer, second_part);
|
2013-02-26 06:18:22 -06:00
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
2014-02-01 06:50:23 -06:00
|
|
|
// evaluate TO_BITS nodes
|
|
|
|
if (type == AST_TO_BITS) {
|
|
|
|
if (children[0]->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Left operand of to_bits expression is not constant!\n");
|
2014-02-01 06:50:23 -06:00
|
|
|
if (children[1]->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Right operand of to_bits expression is not constant!\n");
|
2014-02-01 06:50:23 -06:00
|
|
|
RTLIL::Const new_value = children[1]->bitsAsConst(children[0]->bitsAsConst().as_int(), children[1]->is_signed);
|
|
|
|
newNode = mkconst_bits(new_value.bits, children[1]->is_signed);
|
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
// annotate constant ranges
|
|
|
|
if (type == AST_RANGE) {
|
|
|
|
bool old_range_valid = range_valid;
|
|
|
|
range_valid = false;
|
2014-07-28 07:25:03 -05:00
|
|
|
range_swapped = false;
|
2013-01-05 04:13:26 -06:00
|
|
|
range_left = -1;
|
|
|
|
range_right = 0;
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(children.size() >= 1);
|
2013-01-05 04:13:26 -06:00
|
|
|
if (children[0]->type == AST_CONSTANT) {
|
|
|
|
range_valid = true;
|
|
|
|
range_left = children[0]->integer;
|
|
|
|
if (children.size() == 1)
|
|
|
|
range_right = range_left;
|
|
|
|
}
|
|
|
|
if (children.size() >= 2) {
|
|
|
|
if (children[1]->type == AST_CONSTANT)
|
|
|
|
range_right = children[1]->integer;
|
|
|
|
else
|
|
|
|
range_valid = false;
|
|
|
|
}
|
|
|
|
if (old_range_valid != range_valid)
|
|
|
|
did_something = true;
|
2020-05-04 14:18:20 -05:00
|
|
|
if (range_valid && range_right > range_left) {
|
2024-01-25 00:28:15 -06:00
|
|
|
std::swap(range_left, range_right);
|
2014-07-28 07:25:03 -05:00
|
|
|
range_swapped = true;
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// annotate wires with their ranges
|
|
|
|
if (type == AST_WIRE) {
|
|
|
|
if (children.size() > 0) {
|
|
|
|
if (children[0]->range_valid) {
|
|
|
|
if (!range_valid)
|
|
|
|
did_something = true;
|
|
|
|
range_valid = true;
|
2014-07-28 07:25:03 -05:00
|
|
|
range_swapped = children[0]->range_swapped;
|
2013-01-05 04:13:26 -06:00
|
|
|
range_left = children[0]->range_left;
|
|
|
|
range_right = children[0]->range_right;
|
2020-05-18 11:15:03 -05:00
|
|
|
bool force_upto = false, force_downto = false;
|
|
|
|
if (attributes.count(ID::force_upto)) {
|
|
|
|
AstNode *val = attributes[ID::force_upto];
|
|
|
|
if (val->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Attribute `force_upto' with non-constant value!\n");
|
2020-05-18 11:15:03 -05:00
|
|
|
force_upto = val->asAttrConst().as_bool();
|
|
|
|
}
|
|
|
|
if (attributes.count(ID::force_downto)) {
|
|
|
|
AstNode *val = attributes[ID::force_downto];
|
|
|
|
if (val->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Attribute `force_downto' with non-constant value!\n");
|
2020-05-18 11:15:03 -05:00
|
|
|
force_downto = val->asAttrConst().as_bool();
|
|
|
|
}
|
|
|
|
if (force_upto && force_downto)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Attributes `force_downto' and `force_upto' cannot be both set!\n");
|
2020-05-18 11:15:03 -05:00
|
|
|
if ((force_upto && !range_swapped) || (force_downto && range_swapped)) {
|
|
|
|
std::swap(range_left, range_right);
|
|
|
|
range_swapped = force_upto;
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (!range_valid)
|
|
|
|
did_something = true;
|
|
|
|
range_valid = true;
|
2014-07-28 07:25:03 -05:00
|
|
|
range_swapped = false;
|
2013-01-05 04:13:26 -06:00
|
|
|
range_left = 0;
|
|
|
|
range_right = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
// Resolve packed and unpacked ranges in declarations.
|
|
|
|
if ((type == AST_WIRE || type == AST_MEMORY) && dimensions.empty()) {
|
|
|
|
if (!children.empty()) {
|
|
|
|
// Unpacked ranges first, then packed ranges.
|
|
|
|
for (int i = std::min(GetSize(children), 2) - 1; i >= 0; i--) {
|
|
|
|
if (children[i]->type == AST_MULTIRANGE) {
|
|
|
|
int width = 1;
|
|
|
|
for (auto range : children[i]->children) {
|
|
|
|
width *= add_dimension(this, range);
|
|
|
|
if (i) unpacked_dimensions++;
|
|
|
|
}
|
|
|
|
delete children[i];
|
|
|
|
int left = width - 1, right = 0;
|
|
|
|
if (i)
|
|
|
|
std::swap(left, right);
|
|
|
|
children[i] = new AstNode(AST_RANGE, mkconst_int(left, true), mkconst_int(right, true));
|
|
|
|
fixup_hierarchy_flags();
|
|
|
|
did_something = true;
|
|
|
|
} else if (children[i]->type == AST_RANGE) {
|
|
|
|
add_dimension(this, children[i]);
|
|
|
|
if (i) unpacked_dimensions++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// 1 bit signal: bit, logic or reg
|
|
|
|
dimensions.push_back({ 0, 1, false });
|
2014-08-06 08:43:46 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
// Resolve multidimensional array access.
|
|
|
|
if (type == AST_IDENTIFIER && !basic_prep && id2ast && (id2ast->type == AST_WIRE || id2ast->type == AST_MEMORY) &&
|
|
|
|
children.size() > 0 && (children[0]->type == AST_RANGE || children[0]->type == AST_MULTIRANGE))
|
2014-08-06 08:43:46 -05:00
|
|
|
{
|
2024-01-25 00:28:15 -06:00
|
|
|
int dims_sel = children[0]->type == AST_MULTIRANGE ? children[0]->children.size() : 1;
|
|
|
|
// Save original number of dimensions for $size() etc.
|
|
|
|
integer = dims_sel;
|
|
|
|
|
|
|
|
// Split access into unpacked and packed parts.
|
|
|
|
AstNode *unpacked_range = nullptr;
|
|
|
|
AstNode *packed_range = nullptr;
|
|
|
|
|
|
|
|
if (id2ast->unpacked_dimensions) {
|
|
|
|
if (id2ast->unpacked_dimensions > 1) {
|
|
|
|
// Flattened range for access to unpacked dimensions.
|
|
|
|
unpacked_range = make_index_range(id2ast, true);
|
|
|
|
} else {
|
|
|
|
// Index into one-dimensional unpacked part; unlink simple range node.
|
|
|
|
AstNode *&range = children[0]->type == AST_MULTIRANGE ? children[0]->children[0] : children[0];
|
|
|
|
unpacked_range = range;
|
|
|
|
range = nullptr;
|
|
|
|
}
|
|
|
|
}
|
2014-08-06 08:43:46 -05:00
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
if (dims_sel > id2ast->unpacked_dimensions) {
|
|
|
|
if (GetSize(id2ast->dimensions) - id2ast->unpacked_dimensions > 1) {
|
|
|
|
// Flattened range for access to packed dimensions.
|
|
|
|
packed_range = make_index_range(id2ast, false);
|
|
|
|
} else {
|
|
|
|
// Index into one-dimensional packed part; unlink simple range node.
|
|
|
|
AstNode *&range = children[0]->type == AST_MULTIRANGE ? children[0]->children[dims_sel - 1] : children[0];
|
|
|
|
packed_range = range;
|
|
|
|
range = nullptr;
|
|
|
|
}
|
2014-08-06 08:43:46 -05:00
|
|
|
}
|
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
for (auto &it : children)
|
|
|
|
delete it;
|
|
|
|
children.clear();
|
2014-08-06 08:43:46 -05:00
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
if (unpacked_range)
|
|
|
|
children.push_back(unpacked_range);
|
|
|
|
|
|
|
|
if (packed_range)
|
|
|
|
children.push_back(packed_range);
|
2014-08-06 08:43:46 -05:00
|
|
|
|
2023-04-05 04:00:07 -05:00
|
|
|
fixup_hierarchy_flags();
|
2024-01-25 00:28:15 -06:00
|
|
|
basic_prep = true;
|
2014-08-06 08:43:46 -05:00
|
|
|
did_something = true;
|
|
|
|
}
|
|
|
|
|
2013-11-07 02:58:15 -06:00
|
|
|
// trim/extend parameters
|
2018-03-09 06:47:11 -06:00
|
|
|
if (type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_ENUM_ITEM) {
|
2014-06-14 05:00:47 -05:00
|
|
|
if (children.size() > 1 && children[1]->type == AST_RANGE) {
|
2014-06-14 13:38:05 -05:00
|
|
|
if (!children[1]->range_valid)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Non-constant width range on parameter decl.\n");
|
2015-06-08 07:03:06 -05:00
|
|
|
int width = std::abs(children[1]->range_left - children[1]->range_right) + 1;
|
2014-06-14 05:00:47 -05:00
|
|
|
if (children[0]->type == AST_REALVALUE) {
|
2014-06-14 13:38:05 -05:00
|
|
|
RTLIL::Const constvalue = children[0]->realAsConst(width);
|
2020-02-23 01:19:52 -06:00
|
|
|
log_file_warning(filename, location.first_line, "converting real value %e to binary %s.\n",
|
2018-11-04 03:19:32 -06:00
|
|
|
children[0]->realvalue, log_signal(constvalue));
|
2014-06-14 05:00:47 -05:00
|
|
|
delete children[0];
|
2014-06-14 13:38:05 -05:00
|
|
|
children[0] = mkconst_bits(constvalue.bits, sign_hint);
|
2023-04-05 04:00:07 -05:00
|
|
|
fixup_hierarchy_flags();
|
2014-06-14 05:00:47 -05:00
|
|
|
did_something = true;
|
|
|
|
}
|
|
|
|
if (children[0]->type == AST_CONSTANT) {
|
|
|
|
if (width != int(children[0]->bits.size())) {
|
|
|
|
RTLIL::SigSpec sig(children[0]->bits);
|
|
|
|
sig.extend_u0(width, children[0]->is_signed);
|
|
|
|
AstNode *old_child_0 = children[0];
|
2016-03-18 06:15:00 -05:00
|
|
|
children[0] = mkconst_bits(sig.as_const().bits, is_signed);
|
2014-06-14 05:00:47 -05:00
|
|
|
delete old_child_0;
|
2023-04-05 04:00:07 -05:00
|
|
|
fixup_hierarchy_flags();
|
2014-06-14 05:00:47 -05:00
|
|
|
}
|
|
|
|
children[0]->is_signed = is_signed;
|
|
|
|
}
|
2014-07-28 09:45:26 -05:00
|
|
|
range_valid = true;
|
|
|
|
range_swapped = children[1]->range_swapped;
|
|
|
|
range_left = children[1]->range_left;
|
|
|
|
range_right = children[1]->range_right;
|
2014-06-14 05:00:47 -05:00
|
|
|
} else
|
|
|
|
if (children.size() > 1 && children[1]->type == AST_REALVALUE && children[0]->type == AST_CONSTANT) {
|
|
|
|
double as_realvalue = children[0]->asReal(sign_hint);
|
|
|
|
delete children[0];
|
|
|
|
children[0] = new AstNode(AST_REALVALUE);
|
|
|
|
children[0]->realvalue = as_realvalue;
|
2023-04-05 04:00:07 -05:00
|
|
|
fixup_hierarchy_flags();
|
2014-06-14 05:00:47 -05:00
|
|
|
did_something = true;
|
2013-11-07 02:58:15 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-05-08 08:40:49 -05:00
|
|
|
if (type == AST_IDENTIFIER && !basic_prep) {
|
|
|
|
// check if a plausible struct member sss.mmmm
|
2024-01-04 10:22:07 -06:00
|
|
|
if (!str.empty() && str[0] == '\\' && current_scope.count(str)) {
|
|
|
|
auto item_node = current_scope[str];
|
|
|
|
if (item_node->type == AST_STRUCT_ITEM || item_node->type == AST_STRUCT || item_node->type == AST_UNION) {
|
|
|
|
// Traverse any hierarchical path until the full name for the referenced struct/union is found.
|
|
|
|
std::string sname;
|
|
|
|
bool found_sname = false;
|
|
|
|
for (std::string::size_type pos = 0; (pos = str.find('.', pos)) != std::string::npos; pos++) {
|
|
|
|
sname = str.substr(0, pos);
|
|
|
|
if (current_scope.count(sname)) {
|
|
|
|
auto stype = current_scope[sname]->type;
|
|
|
|
if (stype == AST_WIRE || stype == AST_PARAMETER || stype == AST_LOCALPARAM) {
|
|
|
|
found_sname = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (found_sname) {
|
2020-05-08 08:40:49 -05:00
|
|
|
// structure member, rewrite this node to reference the packed struct wire
|
2024-01-25 00:28:15 -06:00
|
|
|
auto range = make_index_range(item_node);
|
2020-05-08 08:40:49 -05:00
|
|
|
newNode = new AstNode(AST_IDENTIFIER, range);
|
|
|
|
newNode->str = sname;
|
2023-02-09 12:27:51 -06:00
|
|
|
// save type and original number of dimensions for $size() etc.
|
2023-04-05 04:00:07 -05:00
|
|
|
newNode->set_attribute(ID::wiretype, item_node->clone());
|
2024-01-25 00:28:15 -06:00
|
|
|
if (!item_node->dimensions.empty() && children.size() > 0) {
|
2023-02-09 12:27:51 -06:00
|
|
|
if (children[0]->type == AST_RANGE)
|
|
|
|
newNode->integer = 1;
|
|
|
|
else if (children[0]->type == AST_MULTIRANGE)
|
|
|
|
newNode->integer = children[0]->children.size();
|
|
|
|
}
|
2020-05-08 08:40:49 -05:00
|
|
|
newNode->basic_prep = true;
|
2021-06-22 09:39:57 -05:00
|
|
|
if (item_node->is_signed)
|
|
|
|
newNode = new AstNode(AST_TO_SIGNED, newNode);
|
2020-05-08 08:40:49 -05:00
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2020-06-07 12:28:45 -05:00
|
|
|
// annotate identifiers using scope resolution and create auto-wires as needed
|
2013-01-05 04:13:26 -06:00
|
|
|
if (type == AST_IDENTIFIER) {
|
|
|
|
if (current_scope.count(str) == 0) {
|
2020-04-16 04:27:59 -05:00
|
|
|
AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod;
|
2021-06-05 15:21:09 -05:00
|
|
|
str = try_pop_module_prefix();
|
2020-04-16 04:27:59 -05:00
|
|
|
for (auto node : current_scope_ast->children) {
|
2018-03-09 06:47:11 -06:00
|
|
|
//log("looking at mod scope child %s\n", type2str(node->type).c_str());
|
|
|
|
switch (node->type) {
|
|
|
|
case AST_PARAMETER:
|
|
|
|
case AST_LOCALPARAM:
|
|
|
|
case AST_WIRE:
|
|
|
|
case AST_AUTOWIRE:
|
|
|
|
case AST_GENVAR:
|
|
|
|
case AST_MEMORY:
|
|
|
|
case AST_FUNCTION:
|
|
|
|
case AST_TASK:
|
|
|
|
case AST_DPI_FUNCTION:
|
|
|
|
//log("found child %s, %s\n", type2str(node->type).c_str(), node->str.c_str());
|
2020-01-17 00:21:09 -06:00
|
|
|
if (str == node->str) {
|
2020-02-27 18:53:49 -06:00
|
|
|
//log("add %s, type %s to scope\n", str.c_str(), type2str(node->type).c_str());
|
2020-01-17 00:21:09 -06:00
|
|
|
current_scope[node->str] = node;
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
break;
|
2018-03-09 06:47:11 -06:00
|
|
|
case AST_ENUM:
|
2013-01-05 04:13:26 -06:00
|
|
|
current_scope[node->str] = node;
|
2018-03-09 06:47:11 -06:00
|
|
|
for (auto enum_node : node->children) {
|
|
|
|
log_assert(enum_node->type==AST_ENUM_ITEM);
|
|
|
|
if (str == enum_node->str) {
|
2020-02-03 00:12:24 -06:00
|
|
|
//log("\nadding enum item %s to scope\n", str.c_str());
|
2018-03-09 06:47:11 -06:00
|
|
|
current_scope[str] = enum_node;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
2013-01-05 04:13:26 -06:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (current_scope.count(str) == 0) {
|
2020-04-16 04:27:59 -05:00
|
|
|
if (current_ast_mod == nullptr) {
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Identifier `%s' is implicitly declared outside of a module.\n", str.c_str());
|
2020-04-16 04:27:59 -05:00
|
|
|
} else if (flag_autowire || str == "\\$global_clock") {
|
2019-02-21 11:40:11 -06:00
|
|
|
AstNode *auto_wire = new AstNode(AST_AUTOWIRE);
|
|
|
|
auto_wire->str = str;
|
|
|
|
current_ast_mod->children.push_back(auto_wire);
|
|
|
|
current_scope[str] = auto_wire;
|
|
|
|
did_something = true;
|
|
|
|
} else {
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
|
2019-02-21 11:40:11 -06:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
2014-03-05 12:45:33 -06:00
|
|
|
if (id2ast != current_scope[str]) {
|
|
|
|
id2ast = current_scope[str];
|
|
|
|
did_something = true;
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
2013-11-20 03:51:32 -06:00
|
|
|
// split memory access with bit select to individual statements
|
2021-05-26 17:22:31 -05:00
|
|
|
if (type == AST_IDENTIFIER && children.size() == 2 && children[0]->type == AST_RANGE && children[1]->type == AST_RANGE && !in_lvalue && stage == 2)
|
2013-11-20 03:51:32 -06:00
|
|
|
{
|
2014-07-17 06:13:21 -05:00
|
|
|
if (id2ast == NULL || id2ast->type != AST_MEMORY || children[0]->children.size() != 1)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Invalid bit-select on memory access!\n");
|
2013-11-20 03:51:32 -06:00
|
|
|
|
|
|
|
int mem_width, mem_size, addr_bits;
|
|
|
|
id2ast->meminfo(mem_width, mem_size, addr_bits);
|
|
|
|
|
2016-08-22 07:27:46 -05:00
|
|
|
int data_range_left = id2ast->children[0]->range_left;
|
|
|
|
int data_range_right = id2ast->children[0]->range_right;
|
|
|
|
|
2019-03-21 16:19:17 -05:00
|
|
|
if (id2ast->children[0]->range_swapped)
|
|
|
|
std::swap(data_range_left, data_range_right);
|
|
|
|
|
2013-11-20 03:51:32 -06:00
|
|
|
std::stringstream sstr;
|
2022-08-08 09:13:33 -05:00
|
|
|
sstr << "$mem2bits$" << str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
|
2013-11-20 03:51:32 -06:00
|
|
|
std::string wire_id = sstr.str();
|
|
|
|
|
2016-08-22 07:27:46 -05:00
|
|
|
AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(data_range_left, true), mkconst_int(data_range_right, true)));
|
2013-11-20 03:51:32 -06:00
|
|
|
wire->str = wire_id;
|
|
|
|
if (current_block)
|
2023-04-05 04:00:07 -05:00
|
|
|
wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
|
2013-11-20 03:51:32 -06:00
|
|
|
current_ast_mod->children.push_back(wire);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (wire->simplify(true, 1, -1, false)) { }
|
2013-11-20 03:51:32 -06:00
|
|
|
|
|
|
|
AstNode *data = clone();
|
|
|
|
delete data->children[1];
|
|
|
|
data->children.pop_back();
|
|
|
|
|
|
|
|
AstNode *assign = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), data);
|
|
|
|
assign->children[0]->str = wire_id;
|
2018-06-05 09:44:24 -05:00
|
|
|
assign->children[0]->was_checked = true;
|
2013-11-20 03:51:32 -06:00
|
|
|
|
|
|
|
if (current_block)
|
|
|
|
{
|
|
|
|
size_t assign_idx = 0;
|
|
|
|
while (assign_idx < current_block->children.size() && current_block->children[assign_idx] != current_block_child)
|
|
|
|
assign_idx++;
|
|
|
|
log_assert(assign_idx < current_block->children.size());
|
|
|
|
current_block->children.insert(current_block->children.begin()+assign_idx, assign);
|
|
|
|
wire->is_reg = true;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
AstNode *proc = new AstNode(AST_ALWAYS, new AstNode(AST_BLOCK));
|
|
|
|
proc->children[0]->children.push_back(assign);
|
|
|
|
current_ast_mod->children.push_back(proc);
|
|
|
|
}
|
|
|
|
|
|
|
|
newNode = new AstNode(AST_IDENTIFIER, children[1]->clone());
|
|
|
|
newNode->str = wire_id;
|
2020-09-16 16:55:17 -05:00
|
|
|
newNode->integer = integer; // save original number of dimensions for $size() etc.
|
2013-11-20 03:51:32 -06:00
|
|
|
newNode->id2ast = wire;
|
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
2014-06-06 15:55:02 -05:00
|
|
|
if (type == AST_WHILE)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("While loops are only allowed in constant functions!\n");
|
2014-06-06 15:55:02 -05:00
|
|
|
|
|
|
|
if (type == AST_REPEAT)
|
2019-04-09 11:28:32 -05:00
|
|
|
{
|
|
|
|
AstNode *count = children[0];
|
|
|
|
AstNode *body = children[1];
|
|
|
|
|
|
|
|
// eval count expression
|
2023-04-04 15:59:44 -05:00
|
|
|
while (count->simplify(true, stage, 32, true)) { }
|
2019-04-09 11:28:32 -05:00
|
|
|
|
|
|
|
if (count->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Repeat loops outside must have constant repeat counts!\n");
|
2019-04-09 11:28:32 -05:00
|
|
|
|
|
|
|
// convert to a block with the body repeated n times
|
|
|
|
type = AST_BLOCK;
|
|
|
|
children.clear();
|
|
|
|
for (int i = 0; i < count->bitsAsConst().as_int(); i++)
|
|
|
|
children.insert(children.begin(), body->clone());
|
|
|
|
|
|
|
|
delete count;
|
|
|
|
delete body;
|
|
|
|
did_something = true;
|
|
|
|
}
|
2014-06-06 15:55:02 -05:00
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
// unroll for loops and generate-for blocks
|
|
|
|
if ((type == AST_GENFOR || type == AST_FOR) && children.size() != 0)
|
|
|
|
{
|
|
|
|
AstNode *init_ast = children[0];
|
|
|
|
AstNode *while_ast = children[1];
|
|
|
|
AstNode *next_ast = children[2];
|
|
|
|
AstNode *body_ast = children[3];
|
|
|
|
|
2013-12-04 14:33:00 -06:00
|
|
|
while (body_ast->type == AST_GENBLOCK && body_ast->str.empty() &&
|
|
|
|
body_ast->children.size() == 1 && body_ast->children.at(0)->type == AST_GENBLOCK)
|
|
|
|
body_ast = body_ast->children.at(0);
|
|
|
|
|
2020-07-25 11:35:03 -05:00
|
|
|
const char* loop_type_str = "procedural";
|
|
|
|
const char* var_type_str = "register";
|
|
|
|
AstNodeType var_type = AST_WIRE;
|
|
|
|
if (type == AST_GENFOR) {
|
|
|
|
loop_type_str = "generate";
|
|
|
|
var_type_str = "genvar";
|
|
|
|
var_type = AST_GENVAR;
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
if (init_ast->type != AST_ASSIGN_EQ)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Unsupported 1st expression of %s for-loop!\n", loop_type_str);
|
2013-01-05 04:13:26 -06:00
|
|
|
if (next_ast->type != AST_ASSIGN_EQ)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Unsupported 3rd expression of %s for-loop!\n", loop_type_str);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2020-07-25 11:35:03 -05:00
|
|
|
if (init_ast->children[0]->id2ast == NULL || init_ast->children[0]->id2ast->type != var_type)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Left hand side of 1st expression of %s for-loop is not a %s!\n", loop_type_str, var_type_str);
|
2020-07-25 11:35:03 -05:00
|
|
|
if (next_ast->children[0]->id2ast == NULL || next_ast->children[0]->id2ast->type != var_type)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Left hand side of 3rd expression of %s for-loop is not a %s!\n", loop_type_str, var_type_str);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
if (init_ast->children[0]->id2ast != next_ast->children[0]->id2ast)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Incompatible left-hand sides in 1st and 3rd expression of %s for-loop!\n", loop_type_str);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
// eval 1st expression
|
|
|
|
AstNode *varbuf = init_ast->children[1]->clone();
|
2019-04-22 11:19:02 -05:00
|
|
|
{
|
|
|
|
int expr_width_hint = -1;
|
|
|
|
bool expr_sign_hint = true;
|
|
|
|
varbuf->detectSignWidth(expr_width_hint, expr_sign_hint);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (varbuf->simplify(true, stage, 32, true)) { }
|
2019-04-22 11:19:02 -05:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
if (varbuf->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Right hand side of 1st expression of %s for-loop is not constant!\n", loop_type_str);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2019-12-11 18:26:26 -06:00
|
|
|
auto resolved = current_scope.at(init_ast->children[0]->str);
|
|
|
|
if (resolved->range_valid) {
|
2020-02-05 19:19:42 -06:00
|
|
|
int const_size = varbuf->range_left - varbuf->range_right;
|
|
|
|
int resolved_size = resolved->range_left - resolved->range_right;
|
|
|
|
if (const_size < resolved_size) {
|
|
|
|
for (int i = const_size; i < resolved_size; i++)
|
|
|
|
varbuf->bits.push_back(resolved->is_signed ? varbuf->bits.back() : State::S0);
|
|
|
|
varbuf->range_left = resolved->range_left;
|
|
|
|
varbuf->range_right = resolved->range_right;
|
|
|
|
varbuf->range_swapped = resolved->range_swapped;
|
|
|
|
varbuf->range_valid = resolved->range_valid;
|
|
|
|
}
|
2019-12-11 18:26:26 -06:00
|
|
|
}
|
|
|
|
|
2020-02-05 19:19:42 -06:00
|
|
|
varbuf = new AstNode(AST_LOCALPARAM, varbuf);
|
|
|
|
varbuf->str = init_ast->children[0]->str;
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
AstNode *backup_scope_varbuf = current_scope[varbuf->str];
|
|
|
|
current_scope[varbuf->str] = varbuf;
|
|
|
|
|
|
|
|
size_t current_block_idx = 0;
|
|
|
|
if (type == AST_FOR) {
|
|
|
|
while (current_block_idx < current_block->children.size() &&
|
|
|
|
current_block->children[current_block_idx] != current_block_child)
|
|
|
|
current_block_idx++;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (1)
|
|
|
|
{
|
|
|
|
// eval 2nd expression
|
|
|
|
AstNode *buf = while_ast->clone();
|
2019-04-22 11:19:02 -05:00
|
|
|
{
|
|
|
|
int expr_width_hint = -1;
|
|
|
|
bool expr_sign_hint = true;
|
|
|
|
buf->detectSignWidth(expr_width_hint, expr_sign_hint);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (buf->simplify(true, stage, expr_width_hint, expr_sign_hint)) { }
|
2019-04-22 11:19:02 -05:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
if (buf->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("2nd expression of %s for-loop is not constant!\n", loop_type_str);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
if (buf->integer == 0) {
|
|
|
|
delete buf;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
delete buf;
|
|
|
|
|
|
|
|
// expand body
|
|
|
|
int index = varbuf->children[0]->integer;
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
log_assert(body_ast->type == AST_GENBLOCK || body_ast->type == AST_BLOCK);
|
|
|
|
log_assert(!body_ast->str.empty());
|
|
|
|
buf = body_ast->clone();
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
std::stringstream sstr;
|
|
|
|
sstr << buf->str << "[" << index << "].";
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
std::string prefix = sstr.str();
|
|
|
|
|
|
|
|
// create a scoped localparam for the current value of the loop variable
|
|
|
|
AstNode *local_index = varbuf->clone();
|
|
|
|
size_t pos = local_index->str.rfind('.');
|
|
|
|
if (pos != std::string::npos) // remove outer prefix
|
|
|
|
local_index->str = "\\" + local_index->str.substr(pos + 1);
|
|
|
|
local_index->str = prefix_id(prefix, local_index->str);
|
|
|
|
current_scope[local_index->str] = local_index;
|
|
|
|
current_ast_mod->children.push_back(local_index);
|
|
|
|
|
|
|
|
buf->expand_genblock(prefix);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
if (type == AST_GENFOR) {
|
2013-11-20 06:57:40 -06:00
|
|
|
for (size_t i = 0; i < buf->children.size(); i++) {
|
2023-04-04 15:59:44 -05:00
|
|
|
buf->children[i]->simplify(const_fold, stage, -1, false);
|
2013-01-05 04:13:26 -06:00
|
|
|
current_ast_mod->children.push_back(buf->children[i]);
|
2013-11-20 06:57:40 -06:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
} else {
|
|
|
|
for (size_t i = 0; i < buf->children.size(); i++)
|
|
|
|
current_block->children.insert(current_block->children.begin() + current_block_idx++, buf->children[i]);
|
|
|
|
}
|
|
|
|
buf->children.clear();
|
|
|
|
delete buf;
|
|
|
|
|
|
|
|
// eval 3rd expression
|
|
|
|
buf = next_ast->children[1]->clone();
|
2023-04-05 04:00:07 -05:00
|
|
|
buf->set_in_param_flag(true);
|
2019-04-22 11:19:02 -05:00
|
|
|
{
|
|
|
|
int expr_width_hint = -1;
|
|
|
|
bool expr_sign_hint = true;
|
|
|
|
buf->detectSignWidth(expr_width_hint, expr_sign_hint);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (buf->simplify(true, stage, expr_width_hint, expr_sign_hint)) { }
|
2019-04-22 11:19:02 -05:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
if (buf->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Right hand side of 3rd expression of %s for-loop is not constant (%s)!\n", loop_type_str, type2str(buf->type).c_str());
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
delete varbuf->children[0];
|
|
|
|
varbuf->children[0] = buf;
|
|
|
|
}
|
|
|
|
|
2019-04-30 08:03:32 -05:00
|
|
|
if (type == AST_FOR) {
|
|
|
|
AstNode *buf = next_ast->clone();
|
|
|
|
delete buf->children[1];
|
|
|
|
buf->children[1] = varbuf->children[0]->clone();
|
|
|
|
current_block->children.insert(current_block->children.begin() + current_block_idx++, buf);
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
current_scope[varbuf->str] = backup_scope_varbuf;
|
|
|
|
delete varbuf;
|
|
|
|
delete_children();
|
|
|
|
did_something = true;
|
|
|
|
}
|
|
|
|
|
2017-01-04 09:03:04 -06:00
|
|
|
// check for local objects in unnamed block
|
|
|
|
if (type == AST_BLOCK && str.empty())
|
|
|
|
{
|
|
|
|
for (size_t i = 0; i < children.size(); i++)
|
2019-09-19 14:43:13 -05:00
|
|
|
if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF)
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
{
|
|
|
|
log_assert(!VERILOG_FRONTEND::sv_mode);
|
2023-04-04 04:53:50 -05:00
|
|
|
children[i]->input_error("Local declaration in unnamed block is only supported in SystemVerilog mode!\n");
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
}
|
2017-01-04 09:03:04 -06:00
|
|
|
}
|
|
|
|
|
2013-12-04 02:10:16 -06:00
|
|
|
// transform block with name
|
|
|
|
if (type == AST_BLOCK && !str.empty())
|
|
|
|
{
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
expand_genblock(str + ".");
|
2013-12-04 02:10:16 -06:00
|
|
|
|
2022-01-06 23:04:00 -06:00
|
|
|
// if this is an autonamed block is in an always_comb
|
|
|
|
if (current_always && current_always->attributes.count(ID::always_comb)
|
2022-02-22 09:57:08 -06:00
|
|
|
&& is_autonamed_block(str))
|
2022-01-06 23:04:00 -06:00
|
|
|
// track local variables in this block so we can consider adding
|
|
|
|
// nosync once the block has been fully elaborated
|
|
|
|
for (AstNode *child : children)
|
|
|
|
if (child->type == AST_WIRE &&
|
|
|
|
!child->attributes.count(ID::nosync))
|
|
|
|
mark_auto_nosync(this, child);
|
|
|
|
|
2013-12-04 02:10:16 -06:00
|
|
|
std::vector<AstNode*> new_children;
|
|
|
|
for (size_t i = 0; i < children.size(); i++)
|
2019-09-19 14:43:13 -05:00
|
|
|
if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF) {
|
2023-04-04 15:59:44 -05:00
|
|
|
children[i]->simplify(false, stage, -1, false);
|
2013-12-04 02:10:16 -06:00
|
|
|
current_ast_mod->children.push_back(children[i]);
|
2014-08-05 05:15:53 -05:00
|
|
|
current_scope[children[i]->str] = children[i];
|
2013-12-04 02:10:16 -06:00
|
|
|
} else
|
|
|
|
new_children.push_back(children[i]);
|
|
|
|
|
|
|
|
children.swap(new_children);
|
|
|
|
did_something = true;
|
|
|
|
str.clear();
|
|
|
|
}
|
|
|
|
|
2013-03-26 03:44:54 -05:00
|
|
|
// simplify unconditional generate block
|
|
|
|
if (type == AST_GENBLOCK && children.size() != 0)
|
|
|
|
{
|
|
|
|
if (!str.empty()) {
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
expand_genblock(str + ".");
|
2013-03-26 03:44:54 -05:00
|
|
|
}
|
|
|
|
|
2013-11-20 06:57:40 -06:00
|
|
|
for (size_t i = 0; i < children.size(); i++) {
|
2023-04-04 15:59:44 -05:00
|
|
|
children[i]->simplify(const_fold, stage, -1, false);
|
2013-03-26 03:44:54 -05:00
|
|
|
current_ast_mod->children.push_back(children[i]);
|
2013-11-20 06:57:40 -06:00
|
|
|
}
|
2013-03-26 03:44:54 -05:00
|
|
|
|
|
|
|
children.clear();
|
|
|
|
did_something = true;
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
// simplify generate-if blocks
|
|
|
|
if (type == AST_GENIF && children.size() != 0)
|
|
|
|
{
|
|
|
|
AstNode *buf = children[0]->clone();
|
2023-04-04 15:59:44 -05:00
|
|
|
while (buf->simplify(true, stage, width_hint, sign_hint)) { }
|
2013-01-05 04:13:26 -06:00
|
|
|
if (buf->type != AST_CONSTANT) {
|
2013-11-07 07:08:53 -06:00
|
|
|
// for (auto f : log_files)
|
|
|
|
// dumpAst(f, "verilog-ast> ");
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Condition for generate if is not constant!\n");
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
2013-12-04 14:06:54 -06:00
|
|
|
if (buf->asBool() != 0) {
|
2013-01-05 04:13:26 -06:00
|
|
|
delete buf;
|
|
|
|
buf = children[1]->clone();
|
|
|
|
} else {
|
|
|
|
delete buf;
|
|
|
|
buf = children.size() > 2 ? children[2]->clone() : NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (buf)
|
|
|
|
{
|
|
|
|
if (buf->type != AST_GENBLOCK)
|
|
|
|
buf = new AstNode(AST_GENBLOCK, buf);
|
|
|
|
|
|
|
|
if (!buf->str.empty()) {
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
buf->expand_genblock(buf->str + ".");
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
2013-11-20 06:57:40 -06:00
|
|
|
for (size_t i = 0; i < buf->children.size(); i++) {
|
2023-04-04 15:59:44 -05:00
|
|
|
buf->children[i]->simplify(const_fold, stage, -1, false);
|
2013-01-05 04:13:26 -06:00
|
|
|
current_ast_mod->children.push_back(buf->children[i]);
|
2013-11-20 06:57:40 -06:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
buf->children.clear();
|
|
|
|
delete buf;
|
|
|
|
}
|
|
|
|
|
|
|
|
delete_children();
|
|
|
|
did_something = true;
|
|
|
|
}
|
|
|
|
|
2013-12-04 14:06:54 -06:00
|
|
|
// simplify generate-case blocks
|
|
|
|
if (type == AST_GENCASE && children.size() != 0)
|
|
|
|
{
|
|
|
|
AstNode *buf = children[0]->clone();
|
2023-04-04 15:59:44 -05:00
|
|
|
while (buf->simplify(true, stage, width_hint, sign_hint)) { }
|
2013-12-04 14:06:54 -06:00
|
|
|
if (buf->type != AST_CONSTANT) {
|
|
|
|
// for (auto f : log_files)
|
|
|
|
// dumpAst(f, "verilog-ast> ");
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Condition for generate case is not constant!\n");
|
2013-12-04 14:06:54 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
bool ref_signed = buf->is_signed;
|
|
|
|
RTLIL::Const ref_value = buf->bitsAsConst();
|
|
|
|
delete buf;
|
|
|
|
|
|
|
|
AstNode *selected_case = NULL;
|
|
|
|
for (size_t i = 1; i < children.size(); i++)
|
|
|
|
{
|
2016-04-21 08:31:54 -05:00
|
|
|
log_assert(children.at(i)->type == AST_COND || children.at(i)->type == AST_CONDX || children.at(i)->type == AST_CONDZ);
|
2013-12-04 14:06:54 -06:00
|
|
|
|
|
|
|
AstNode *this_genblock = NULL;
|
|
|
|
for (auto child : children.at(i)->children) {
|
|
|
|
log_assert(this_genblock == NULL);
|
|
|
|
if (child->type == AST_GENBLOCK)
|
|
|
|
this_genblock = child;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (auto child : children.at(i)->children)
|
|
|
|
{
|
|
|
|
if (child->type == AST_DEFAULT) {
|
|
|
|
if (selected_case == NULL)
|
|
|
|
selected_case = this_genblock;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (child->type == AST_GENBLOCK)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
buf = child->clone();
|
2023-04-05 04:00:07 -05:00
|
|
|
buf->set_in_param_flag(true);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (buf->simplify(true, stage, width_hint, sign_hint)) { }
|
2013-12-04 14:06:54 -06:00
|
|
|
if (buf->type != AST_CONSTANT) {
|
|
|
|
// for (auto f : log_files)
|
|
|
|
// dumpAst(f, "verilog-ast> ");
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Expression in generate case is not constant!\n");
|
2013-12-04 14:06:54 -06:00
|
|
|
}
|
|
|
|
|
2014-07-25 06:07:31 -05:00
|
|
|
bool is_selected = RTLIL::const_eq(ref_value, buf->bitsAsConst(), ref_signed && buf->is_signed, ref_signed && buf->is_signed, 1).as_bool();
|
|
|
|
delete buf;
|
|
|
|
|
|
|
|
if (is_selected) {
|
2013-12-04 14:06:54 -06:00
|
|
|
selected_case = this_genblock;
|
|
|
|
i = children.size();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (selected_case != NULL)
|
|
|
|
{
|
|
|
|
log_assert(selected_case->type == AST_GENBLOCK);
|
|
|
|
buf = selected_case->clone();
|
|
|
|
|
|
|
|
if (!buf->str.empty()) {
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
buf->expand_genblock(buf->str + ".");
|
2013-12-04 14:06:54 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
for (size_t i = 0; i < buf->children.size(); i++) {
|
2023-04-04 15:59:44 -05:00
|
|
|
buf->children[i]->simplify(const_fold, stage, -1, false);
|
2013-12-04 14:06:54 -06:00
|
|
|
current_ast_mod->children.push_back(buf->children[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
buf->children.clear();
|
|
|
|
delete buf;
|
|
|
|
}
|
|
|
|
|
|
|
|
delete_children();
|
|
|
|
did_something = true;
|
|
|
|
}
|
|
|
|
|
2014-06-07 04:48:50 -05:00
|
|
|
// unroll cell arrays
|
|
|
|
if (type == AST_CELLARRAY)
|
|
|
|
{
|
|
|
|
if (!children.at(0)->range_valid)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Non-constant array range on cell array.\n");
|
2014-06-07 04:48:50 -05:00
|
|
|
|
|
|
|
newNode = new AstNode(AST_GENBLOCK);
|
2015-10-25 13:30:49 -05:00
|
|
|
int num = max(children.at(0)->range_left, children.at(0)->range_right) - min(children.at(0)->range_left, children.at(0)->range_right) + 1;
|
2014-06-07 04:48:50 -05:00
|
|
|
|
|
|
|
for (int i = 0; i < num; i++) {
|
|
|
|
int idx = children.at(0)->range_left > children.at(0)->range_right ? children.at(0)->range_right + i : children.at(0)->range_right - i;
|
|
|
|
AstNode *new_cell = children.at(1)->clone();
|
|
|
|
newNode->children.push_back(new_cell);
|
|
|
|
new_cell->str += stringf("[%d]", idx);
|
|
|
|
if (new_cell->type == AST_PRIMITIVE) {
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Cell arrays of primitives are currently not supported.\n");
|
2014-06-07 04:48:50 -05:00
|
|
|
} else {
|
|
|
|
log_assert(new_cell->children.at(0)->type == AST_CELLTYPE);
|
|
|
|
new_cell->children.at(0)->str = stringf("$array:%d:%d:%s", i, num, new_cell->children.at(0)->str.c_str());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
2015-08-14 03:56:05 -05:00
|
|
|
// replace primitives with assignments
|
2013-01-05 04:13:26 -06:00
|
|
|
if (type == AST_PRIMITIVE)
|
|
|
|
{
|
|
|
|
if (children.size() < 2)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Insufficient number of arguments for primitive `%s'!\n", str.c_str());
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
std::vector<AstNode*> children_list;
|
|
|
|
for (auto child : children) {
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(child->type == AST_ARGUMENT);
|
|
|
|
log_assert(child->children.size() == 1);
|
2013-01-05 04:13:26 -06:00
|
|
|
children_list.push_back(child->children[0]);
|
|
|
|
child->children.clear();
|
|
|
|
delete child;
|
|
|
|
}
|
|
|
|
children.clear();
|
|
|
|
|
2013-08-20 04:23:59 -05:00
|
|
|
if (str == "bufif0" || str == "bufif1" || str == "notif0" || str == "notif1")
|
2013-08-19 12:50:04 -05:00
|
|
|
{
|
|
|
|
if (children_list.size() != 3)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Invalid number of arguments for primitive `%s'!\n", str.c_str());
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2013-08-19 12:50:04 -05:00
|
|
|
std::vector<RTLIL::State> z_const(1, RTLIL::State::Sz);
|
|
|
|
|
2013-08-20 04:23:59 -05:00
|
|
|
AstNode *mux_input = children_list.at(1);
|
|
|
|
if (str == "notif0" || str == "notif1") {
|
|
|
|
mux_input = new AstNode(AST_BIT_NOT, mux_input);
|
|
|
|
}
|
2013-08-19 12:50:04 -05:00
|
|
|
AstNode *node = new AstNode(AST_TERNARY, children_list.at(2));
|
|
|
|
if (str == "bufif0") {
|
|
|
|
node->children.push_back(AstNode::mkconst_bits(z_const, false));
|
2013-08-20 04:23:59 -05:00
|
|
|
node->children.push_back(mux_input);
|
2013-08-19 12:50:04 -05:00
|
|
|
} else {
|
2013-08-20 04:23:59 -05:00
|
|
|
node->children.push_back(mux_input);
|
2013-08-19 12:50:04 -05:00
|
|
|
node->children.push_back(AstNode::mkconst_bits(z_const, false));
|
|
|
|
}
|
|
|
|
|
|
|
|
str.clear();
|
|
|
|
type = AST_ASSIGN;
|
|
|
|
children.push_back(children_list.at(0));
|
2018-09-17 17:23:40 -05:00
|
|
|
children.back()->was_checked = true;
|
2013-08-19 12:50:04 -05:00
|
|
|
children.push_back(node);
|
2023-04-05 04:00:07 -05:00
|
|
|
fixup_hierarchy_flags();
|
2013-08-19 12:50:04 -05:00
|
|
|
did_something = true;
|
|
|
|
}
|
2021-03-16 18:18:36 -05:00
|
|
|
else if (str == "buf" || str == "not")
|
|
|
|
{
|
|
|
|
AstNode *input = children_list.back();
|
|
|
|
if (str == "not")
|
|
|
|
input = new AstNode(AST_BIT_NOT, input);
|
|
|
|
|
|
|
|
newNode = new AstNode(AST_GENBLOCK);
|
|
|
|
for (auto it = children_list.begin(); it != std::prev(children_list.end()); it++) {
|
|
|
|
newNode->children.push_back(new AstNode(AST_ASSIGN, *it, input->clone()));
|
|
|
|
newNode->children.back()->was_checked = true;
|
|
|
|
}
|
|
|
|
delete input;
|
|
|
|
|
|
|
|
did_something = true;
|
|
|
|
}
|
2013-08-19 12:50:04 -05:00
|
|
|
else
|
|
|
|
{
|
|
|
|
AstNodeType op_type = AST_NONE;
|
|
|
|
bool invert_results = false;
|
|
|
|
|
|
|
|
if (str == "and")
|
|
|
|
op_type = AST_BIT_AND;
|
|
|
|
if (str == "nand")
|
|
|
|
op_type = AST_BIT_AND, invert_results = true;
|
|
|
|
if (str == "or")
|
|
|
|
op_type = AST_BIT_OR;
|
|
|
|
if (str == "nor")
|
|
|
|
op_type = AST_BIT_OR, invert_results = true;
|
|
|
|
if (str == "xor")
|
|
|
|
op_type = AST_BIT_XOR;
|
|
|
|
if (str == "xnor")
|
|
|
|
op_type = AST_BIT_XOR, invert_results = true;
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(op_type != AST_NONE);
|
2013-08-19 12:50:04 -05:00
|
|
|
|
|
|
|
AstNode *node = children_list[1];
|
|
|
|
if (op_type != AST_POS)
|
2020-05-04 12:22:05 -05:00
|
|
|
for (size_t i = 2; i < children_list.size(); i++) {
|
2013-08-19 12:50:04 -05:00
|
|
|
node = new AstNode(op_type, node, children_list[i]);
|
2020-05-04 12:22:05 -05:00
|
|
|
node->location = location;
|
|
|
|
}
|
2013-08-19 12:50:04 -05:00
|
|
|
if (invert_results)
|
|
|
|
node = new AstNode(AST_BIT_NOT, node);
|
|
|
|
|
|
|
|
str.clear();
|
|
|
|
type = AST_ASSIGN;
|
|
|
|
children.push_back(children_list[0]);
|
2018-09-17 17:23:40 -05:00
|
|
|
children.back()->was_checked = true;
|
2013-08-19 12:50:04 -05:00
|
|
|
children.push_back(node);
|
2023-04-05 04:00:07 -05:00
|
|
|
fixup_hierarchy_flags();
|
2013-08-19 12:50:04 -05:00
|
|
|
did_something = true;
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
// replace dynamic ranges in left-hand side expressions (e.g. "foo[bar] <= 1'b1;") with
|
2020-04-01 05:43:42 -05:00
|
|
|
// either a big case block that selects the correct single-bit assignment, or mask and
|
|
|
|
// shift operations.
|
|
|
|
if (type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE)
|
|
|
|
{
|
2013-01-05 04:13:26 -06:00
|
|
|
if (children[0]->type != AST_IDENTIFIER || children[0]->children.size() == 0)
|
|
|
|
goto skip_dynamic_range_lvalue_expansion;
|
|
|
|
if (children[0]->children[0]->range_valid || did_something)
|
|
|
|
goto skip_dynamic_range_lvalue_expansion;
|
|
|
|
if (children[0]->id2ast == NULL || children[0]->id2ast->type != AST_WIRE)
|
|
|
|
goto skip_dynamic_range_lvalue_expansion;
|
|
|
|
if (!children[0]->id2ast->range_valid)
|
|
|
|
goto skip_dynamic_range_lvalue_expansion;
|
2020-04-01 05:43:42 -05:00
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
AST::AstNode *member_node = children[0]->get_struct_member();
|
2023-08-04 16:45:47 -05:00
|
|
|
int wire_width = member_node ?
|
|
|
|
member_node->range_left - member_node->range_right + 1 :
|
|
|
|
children[0]->id2ast->range_left - children[0]->id2ast->range_right + 1;
|
|
|
|
int wire_offset = children[0]->id2ast->range_right;
|
|
|
|
int result_width = 1;
|
2020-04-01 05:43:42 -05:00
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
AstNode *shift_expr = NULL;
|
|
|
|
AstNode *range = children[0]->children[0];
|
2020-04-01 05:43:42 -05:00
|
|
|
|
2023-04-04 04:34:17 -05:00
|
|
|
if (!try_determine_range_width(range, result_width))
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
|
2023-04-04 04:34:17 -05:00
|
|
|
|
|
|
|
if (range->children.size() >= 2)
|
2013-01-05 04:13:26 -06:00
|
|
|
shift_expr = range->children[1]->clone();
|
2023-04-04 04:34:17 -05:00
|
|
|
else
|
|
|
|
shift_expr = range->children[0]->clone();
|
2020-04-01 05:43:42 -05:00
|
|
|
|
2023-08-04 16:45:47 -05:00
|
|
|
bool use_case_method = children[0]->id2ast->get_bool_attribute(ID::nowrshmsk);
|
2020-04-27 10:04:47 -05:00
|
|
|
|
2020-06-04 16:10:03 -05:00
|
|
|
if (!use_case_method && current_always->detect_latch(children[0]->str))
|
|
|
|
use_case_method = true;
|
|
|
|
|
2023-08-04 16:45:47 -05:00
|
|
|
if (use_case_method) {
|
2020-04-01 05:43:42 -05:00
|
|
|
// big case block
|
|
|
|
|
2023-08-04 16:45:47 -05:00
|
|
|
int stride = 1;
|
|
|
|
long long bitno_div = stride;
|
|
|
|
|
|
|
|
int case_width_hint;
|
|
|
|
bool case_sign_hint;
|
|
|
|
shift_expr->detectSignWidth(case_width_hint, case_sign_hint);
|
|
|
|
int max_width = case_width_hint;
|
|
|
|
|
|
|
|
if (member_node) { // Member in packed struct/union
|
|
|
|
// Clamp chunk to range of member within struct/union.
|
|
|
|
log_assert(!wire_offset && !children[0]->id2ast->range_swapped);
|
|
|
|
|
|
|
|
// When the (* nowrshmsk *) attribute is set, a CASE block is generated below
|
|
|
|
// to select the indexed bit slice. When a multirange array is indexed, the
|
|
|
|
// start of each possible slice is separated by the bit stride of the last
|
|
|
|
// index dimension, and we can optimize the CASE block accordingly.
|
|
|
|
// The dimension of the original array expression is saved in the 'integer' field.
|
|
|
|
int dims = children[0]->integer;
|
|
|
|
stride = wire_width;
|
|
|
|
for (int dim = 0; dim < dims; dim++) {
|
2024-01-25 00:28:15 -06:00
|
|
|
stride /= member_node->dimensions[dim].range_width;
|
2023-08-04 16:45:47 -05:00
|
|
|
}
|
|
|
|
bitno_div = stride;
|
|
|
|
} else {
|
|
|
|
// Extract (index)*(width) from non_opt_range pattern ((@selfsz@((index)*(width)))+(0)).
|
|
|
|
AstNode *lsb_expr =
|
|
|
|
shift_expr->type == AST_ADD && shift_expr->children[0]->type == AST_SELFSZ &&
|
|
|
|
shift_expr->children[1]->type == AST_CONSTANT && shift_expr->children[1]->integer == 0 ?
|
|
|
|
shift_expr->children[0]->children[0] :
|
|
|
|
shift_expr;
|
|
|
|
|
|
|
|
// Extract stride from indexing of two-dimensional packed arrays and
|
|
|
|
// variable slices on the form dst[i*stride +: width] = src.
|
|
|
|
if (lsb_expr->type == AST_MUL &&
|
|
|
|
(lsb_expr->children[0]->type == AST_CONSTANT ||
|
|
|
|
lsb_expr->children[1]->type == AST_CONSTANT))
|
|
|
|
{
|
|
|
|
int stride_ix = lsb_expr->children[1]->type == AST_CONSTANT;
|
|
|
|
stride = (int)lsb_expr->children[stride_ix]->integer;
|
|
|
|
bitno_div = stride != 0 ? stride : 1;
|
|
|
|
|
|
|
|
// Check whether i*stride can overflow.
|
|
|
|
int i_width;
|
|
|
|
bool i_sign;
|
|
|
|
lsb_expr->children[1 - stride_ix]->detectSignWidth(i_width, i_sign);
|
|
|
|
int stride_width;
|
|
|
|
bool stride_sign;
|
|
|
|
lsb_expr->children[stride_ix]->detectSignWidth(stride_width, stride_sign);
|
|
|
|
max_width = std::max(i_width, stride_width);
|
|
|
|
// Stride width calculated from actual stride value.
|
|
|
|
stride_width = std::ceil(std::log2(std::abs(stride)));
|
|
|
|
|
|
|
|
if (i_width + stride_width > max_width) {
|
|
|
|
// For (truncated) i*stride to be within the range of dst, the following must hold:
|
|
|
|
// i*stride ≡ bitno (mod shift_mod), i.e.
|
|
|
|
// i*stride = k*shift_mod + bitno
|
|
|
|
//
|
|
|
|
// The Diophantine equation on the form ax + by = c:
|
|
|
|
// stride*i - shift_mod*k = bitno
|
|
|
|
// has solutions iff c is a multiple of d = gcd(a, b), i.e.
|
|
|
|
// bitno mod gcd(stride, shift_mod) = 0
|
|
|
|
//
|
|
|
|
// long long is at least 64 bits in C++11
|
|
|
|
long long shift_mod = 1ll << (max_width - case_sign_hint);
|
|
|
|
// std::gcd requires C++17
|
|
|
|
// bitno_div = std::gcd(stride, shift_mod);
|
|
|
|
bitno_div = gcd((long long)stride, shift_mod);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// long long is at least 64 bits in C++11
|
|
|
|
long long max_offset = (1ll << (max_width - case_sign_hint)) - 1;
|
|
|
|
long long min_offset = case_sign_hint ? -(1ll << (max_width - 1)) : 0;
|
|
|
|
|
2023-12-08 13:47:43 -06:00
|
|
|
// A temporary register holds the result of the (possibly complex) rvalue expression,
|
|
|
|
// avoiding repetition in each AST_COND below.
|
|
|
|
int rvalue_width;
|
|
|
|
bool rvalue_sign;
|
|
|
|
children[1]->detectSignWidth(rvalue_width, rvalue_sign);
|
|
|
|
AstNode *rvalue = mktemp_logic("$bitselwrite$rvalue$", current_ast_mod, true, rvalue_width - 1, 0, rvalue_sign);
|
|
|
|
AstNode *caseNode = new AstNode(AST_CASE, shift_expr);
|
|
|
|
newNode = new AstNode(AST_BLOCK,
|
|
|
|
new AstNode(AST_ASSIGN_EQ, rvalue, children[1]->clone()),
|
|
|
|
caseNode);
|
|
|
|
|
2020-04-01 05:43:42 -05:00
|
|
|
did_something = true;
|
2023-08-04 16:45:47 -05:00
|
|
|
for (int i = 1 - result_width; i < wire_width; i++) {
|
|
|
|
// Out of range indexes are handled in genrtlil.cc
|
|
|
|
int start_bit = wire_offset + i;
|
|
|
|
int end_bit = start_bit + result_width - 1;
|
|
|
|
// Check whether the current index can be generated by shift_expr.
|
|
|
|
if (start_bit < min_offset || start_bit > max_offset)
|
|
|
|
continue;
|
|
|
|
if (start_bit%bitno_div != 0 || (stride == 0 && start_bit != 0))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
AstNode *cond = new AstNode(AST_COND, mkconst_int(start_bit, case_sign_hint, max_width));
|
2020-04-01 05:43:42 -05:00
|
|
|
AstNode *lvalue = children[0]->clone();
|
|
|
|
lvalue->delete_children();
|
2023-02-28 11:45:55 -06:00
|
|
|
if (member_node)
|
2023-04-05 04:00:07 -05:00
|
|
|
lvalue->set_attribute(ID::wiretype, member_node->clone());
|
2020-04-01 05:43:42 -05:00
|
|
|
lvalue->children.push_back(new AstNode(AST_RANGE,
|
|
|
|
mkconst_int(end_bit, true), mkconst_int(start_bit, true)));
|
2023-12-08 13:47:43 -06:00
|
|
|
cond->children.push_back(new AstNode(AST_BLOCK, new AstNode(type, lvalue, rvalue->clone())));
|
|
|
|
caseNode->children.push_back(cond);
|
2020-04-01 05:43:42 -05:00
|
|
|
}
|
2023-08-04 16:45:47 -05:00
|
|
|
} else {
|
|
|
|
// mask and shift operations
|
2023-12-12 06:37:34 -06:00
|
|
|
// dst = (dst & ~(width'1 << lsb)) | unsigned'(width'(src)) << lsb)
|
2020-04-01 05:43:42 -05:00
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
AstNode *lvalue = children[0]->clone();
|
|
|
|
lvalue->delete_children();
|
2023-02-28 11:45:55 -06:00
|
|
|
if (member_node)
|
2023-04-05 04:00:07 -05:00
|
|
|
lvalue->set_attribute(ID::wiretype, member_node->clone());
|
2020-04-01 05:43:42 -05:00
|
|
|
|
2020-04-15 13:36:40 -05:00
|
|
|
AstNode *old_data = lvalue->clone();
|
|
|
|
if (type == AST_ASSIGN_LE)
|
|
|
|
old_data->lookahead = true;
|
|
|
|
|
2023-12-12 06:37:34 -06:00
|
|
|
int shift_width_hint;
|
|
|
|
bool shift_sign_hint;
|
|
|
|
shift_expr->detectSignWidth(shift_width_hint, shift_sign_hint);
|
2020-04-01 05:43:42 -05:00
|
|
|
|
2023-12-12 06:37:34 -06:00
|
|
|
// All operations are carried out in a new block.
|
|
|
|
newNode = new AstNode(AST_BLOCK);
|
|
|
|
|
|
|
|
// Temporary register holding the result of the bit- or part-select position expression.
|
|
|
|
AstNode *pos = mktemp_logic("$bitselwrite$pos$", current_ast_mod, true, shift_width_hint - 1, 0, shift_sign_hint);
|
|
|
|
newNode->children.push_back(new AstNode(AST_ASSIGN_EQ, pos, shift_expr));
|
2020-04-29 07:28:04 -05:00
|
|
|
|
2023-12-12 06:37:34 -06:00
|
|
|
// Calculate lsb from position.
|
|
|
|
AstNode *shift_val = pos->clone();
|
|
|
|
|
|
|
|
// If the expression is signed, we must add an extra bit for possible negation of the most negative number.
|
|
|
|
// If the expression is unsigned, we must add an extra bit for sign.
|
|
|
|
shift_val = new AstNode(AST_CAST_SIZE, mkconst_int(shift_width_hint + 1, true), shift_val);
|
|
|
|
if (!shift_sign_hint)
|
|
|
|
shift_val = new AstNode(AST_TO_SIGNED, shift_val);
|
2022-01-18 00:18:12 -06:00
|
|
|
|
|
|
|
// offset the shift amount by the lower bound of the dimension
|
2023-12-12 06:37:34 -06:00
|
|
|
if (wire_offset != 0)
|
|
|
|
shift_val = new AstNode(AST_SUB, shift_val, mkconst_int(wire_offset, true));
|
2020-04-27 10:04:47 -05:00
|
|
|
|
2022-01-18 00:18:12 -06:00
|
|
|
// reflect the shift amount if the dimension is swapped
|
|
|
|
if (children[0]->id2ast->range_swapped)
|
2023-12-12 06:37:34 -06:00
|
|
|
shift_val = new AstNode(AST_SUB, mkconst_int(wire_width - result_width, true), shift_val);
|
2022-01-18 00:18:12 -06:00
|
|
|
|
|
|
|
// AST_SHIFT uses negative amounts for shifting left
|
2023-12-12 06:37:34 -06:00
|
|
|
shift_val = new AstNode(AST_NEG, shift_val);
|
2020-04-27 10:04:47 -05:00
|
|
|
|
2023-12-12 06:37:34 -06:00
|
|
|
// dst = (dst & ~(width'1 << lsb)) | unsigned'(width'(src)) << lsb)
|
|
|
|
did_something = true;
|
|
|
|
AstNode *bitmask = mkconst_bits(std::vector<RTLIL::State>(result_width, State::S1), false);
|
|
|
|
newNode->children.push_back(
|
|
|
|
new AstNode(type,
|
|
|
|
lvalue,
|
|
|
|
new AstNode(AST_BIT_OR,
|
|
|
|
new AstNode(AST_BIT_AND,
|
|
|
|
old_data,
|
|
|
|
new AstNode(AST_BIT_NOT,
|
|
|
|
new AstNode(AST_SHIFT,
|
|
|
|
bitmask,
|
|
|
|
shift_val->clone()))),
|
|
|
|
new AstNode(AST_SHIFT,
|
|
|
|
new AstNode(AST_TO_UNSIGNED,
|
|
|
|
new AstNode(AST_CAST_SIZE,
|
|
|
|
mkconst_int(result_width, true),
|
|
|
|
children[1]->clone())),
|
|
|
|
shift_val))));
|
2023-04-05 04:00:07 -05:00
|
|
|
|
|
|
|
newNode->fixup_hierarchy_flags(true);
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
2020-04-01 05:43:42 -05:00
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
skip_dynamic_range_lvalue_expansion:;
|
|
|
|
|
|
|
|
// found right-hand side identifier for memory -> replace with memory read port
|
|
|
|
if (stage > 1 && type == AST_IDENTIFIER && id2ast != NULL && id2ast->type == AST_MEMORY && !in_lvalue &&
|
2015-08-22 07:46:42 -05:00
|
|
|
children.size() == 1 && children[0]->type == AST_RANGE && children[0]->children.size() == 1) {
|
2024-01-25 00:28:15 -06:00
|
|
|
if (integer < (unsigned)id2ast->unpacked_dimensions)
|
|
|
|
input_error("Insufficient number of array indices for %s.\n", log_id(str));
|
2013-01-05 04:13:26 -06:00
|
|
|
newNode = new AstNode(AST_MEMRD, children[0]->children[0]->clone());
|
|
|
|
newNode->str = str;
|
2013-11-03 23:04:42 -06:00
|
|
|
newNode->id2ast = id2ast;
|
2013-01-05 04:13:26 -06:00
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
2016-07-08 07:31:06 -05:00
|
|
|
// assignment with nontrivial member in left-hand concat expression -> split assignment
|
|
|
|
if ((type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE) && children[0]->type == AST_CONCAT && width_hint > 0)
|
|
|
|
{
|
|
|
|
bool found_nontrivial_member = false;
|
|
|
|
|
|
|
|
for (auto child : children[0]->children) {
|
|
|
|
if (child->type == AST_IDENTIFIER && child->id2ast != NULL && child->id2ast->type == AST_MEMORY)
|
|
|
|
found_nontrivial_member = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (found_nontrivial_member)
|
|
|
|
{
|
|
|
|
newNode = new AstNode(AST_BLOCK);
|
|
|
|
|
|
|
|
AstNode *wire_tmp = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(width_hint-1, true), mkconst_int(0, true)));
|
2022-08-08 09:13:33 -05:00
|
|
|
wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
|
2016-07-08 07:31:06 -05:00
|
|
|
current_ast_mod->children.push_back(wire_tmp);
|
|
|
|
current_scope[wire_tmp->str] = wire_tmp;
|
2023-04-05 04:00:07 -05:00
|
|
|
wire_tmp->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
|
2023-04-04 15:59:44 -05:00
|
|
|
while (wire_tmp->simplify(true, 1, -1, false)) { }
|
2019-05-01 03:01:54 -05:00
|
|
|
wire_tmp->is_logic = true;
|
2016-07-08 07:31:06 -05:00
|
|
|
|
|
|
|
AstNode *wire_tmp_id = new AstNode(AST_IDENTIFIER);
|
|
|
|
wire_tmp_id->str = wire_tmp->str;
|
|
|
|
|
|
|
|
newNode->children.push_back(new AstNode(AST_ASSIGN_EQ, wire_tmp_id, children[1]->clone()));
|
2018-09-17 17:23:40 -05:00
|
|
|
newNode->children.back()->was_checked = true;
|
2016-07-08 07:31:06 -05:00
|
|
|
|
|
|
|
int cursor = 0;
|
|
|
|
for (auto child : children[0]->children)
|
|
|
|
{
|
|
|
|
int child_width_hint = -1;
|
|
|
|
bool child_sign_hint = true;
|
|
|
|
child->detectSignWidth(child_width_hint, child_sign_hint);
|
|
|
|
|
|
|
|
AstNode *rhs = wire_tmp_id->clone();
|
|
|
|
rhs->children.push_back(new AstNode(AST_RANGE, AstNode::mkconst_int(cursor+child_width_hint-1, true), AstNode::mkconst_int(cursor, true)));
|
|
|
|
newNode->children.push_back(new AstNode(type, child->clone(), rhs));
|
|
|
|
|
|
|
|
cursor += child_width_hint;
|
|
|
|
}
|
|
|
|
|
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
// assignment with memory in left-hand side expression -> replace with memory write port
|
|
|
|
if (stage > 1 && (type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE) && children[0]->type == AST_IDENTIFIER &&
|
2014-07-17 06:13:21 -05:00
|
|
|
children[0]->id2ast && children[0]->id2ast->type == AST_MEMORY && children[0]->id2ast->children.size() >= 2 &&
|
|
|
|
children[0]->id2ast->children[0]->range_valid && children[0]->id2ast->children[1]->range_valid &&
|
2014-08-06 08:43:46 -05:00
|
|
|
(children[0]->children.size() == 1 || children[0]->children.size() == 2) && children[0]->children[0]->type == AST_RANGE)
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
2024-01-25 00:28:15 -06:00
|
|
|
if (children[0]->integer < (unsigned)children[0]->id2ast->unpacked_dimensions)
|
|
|
|
input_error("Insufficient number of array indices for %s.\n", log_id(str));
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
std::stringstream sstr;
|
2022-08-08 09:13:33 -05:00
|
|
|
sstr << "$memwr$" << children[0]->str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
|
2013-01-05 04:13:26 -06:00
|
|
|
std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN";
|
|
|
|
|
|
|
|
int mem_width, mem_size, addr_bits;
|
2016-11-01 17:17:43 -05:00
|
|
|
bool mem_signed = children[0]->id2ast->is_signed;
|
2013-01-05 04:13:26 -06:00
|
|
|
children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits);
|
|
|
|
|
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-01-01 14:18:28 -06:00
|
|
|
newNode = new AstNode(AST_BLOCK);
|
|
|
|
AstNode *defNode = new AstNode(AST_BLOCK);
|
|
|
|
|
2016-08-22 07:27:46 -05:00
|
|
|
int data_range_left = children[0]->id2ast->children[0]->range_left;
|
|
|
|
int data_range_right = children[0]->id2ast->children[0]->range_right;
|
|
|
|
int mem_data_range_offset = std::min(data_range_left, data_range_right);
|
|
|
|
|
2016-08-19 11:38:25 -05:00
|
|
|
int addr_width_hint = -1;
|
|
|
|
bool addr_sign_hint = true;
|
|
|
|
children[0]->children[0]->children[0]->detectSignWidthWorker(addr_width_hint, addr_sign_hint);
|
|
|
|
addr_bits = std::max(addr_bits, addr_width_hint);
|
|
|
|
|
2014-07-16 05:23:47 -05:00
|
|
|
std::vector<RTLIL::State> x_bits_addr, x_bits_data, set_bits_en;
|
2014-02-22 10:08:00 -06:00
|
|
|
for (int i = 0; i < addr_bits; i++)
|
|
|
|
x_bits_addr.push_back(RTLIL::State::Sx);
|
2013-11-18 12:55:12 -06:00
|
|
|
for (int i = 0; i < mem_width; i++)
|
2014-02-22 10:08:00 -06:00
|
|
|
x_bits_data.push_back(RTLIL::State::Sx);
|
2014-07-16 05:23:47 -05:00
|
|
|
for (int i = 0; i < mem_width; i++)
|
|
|
|
set_bits_en.push_back(RTLIL::State::S1);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-01-01 14:18:28 -06:00
|
|
|
AstNode *node_addr = nullptr;
|
|
|
|
if (children[0]->children[0]->children[0]->isConst()) {
|
|
|
|
node_addr = children[0]->children[0]->children[0]->clone();
|
|
|
|
} else {
|
|
|
|
AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true)));
|
|
|
|
wire_addr->str = id_addr;
|
|
|
|
wire_addr->was_checked = true;
|
|
|
|
current_ast_mod->children.push_back(wire_addr);
|
|
|
|
current_scope[wire_addr->str] = wire_addr;
|
2023-04-04 15:59:44 -05:00
|
|
|
while (wire_addr->simplify(true, 1, -1, false)) { }
|
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-01-01 14:18:28 -06:00
|
|
|
|
2021-02-23 09:48:29 -06:00
|
|
|
AstNode *assign_addr = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_addr, false));
|
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-01-01 14:18:28 -06:00
|
|
|
assign_addr->children[0]->str = id_addr;
|
|
|
|
assign_addr->children[0]->was_checked = true;
|
|
|
|
defNode->children.push_back(assign_addr);
|
|
|
|
|
2021-02-23 09:48:29 -06:00
|
|
|
assign_addr = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), children[0]->children[0]->children[0]->clone());
|
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-01-01 14:18:28 -06:00
|
|
|
assign_addr->children[0]->str = id_addr;
|
|
|
|
assign_addr->children[0]->was_checked = true;
|
|
|
|
newNode->children.push_back(assign_addr);
|
|
|
|
|
|
|
|
node_addr = new AstNode(AST_IDENTIFIER);
|
|
|
|
node_addr->str = id_addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
AstNode *node_data = nullptr;
|
|
|
|
if (children[0]->children.size() == 1 && children[1]->isConst()) {
|
|
|
|
node_data = children[1]->clone();
|
|
|
|
} else {
|
|
|
|
AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
|
|
|
|
wire_data->str = id_data;
|
|
|
|
wire_data->was_checked = true;
|
|
|
|
wire_data->is_signed = mem_signed;
|
|
|
|
current_ast_mod->children.push_back(wire_data);
|
|
|
|
current_scope[wire_data->str] = wire_data;
|
2023-04-04 15:59:44 -05:00
|
|
|
while (wire_data->simplify(true, 1, -1, false)) { }
|
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-01-01 14:18:28 -06:00
|
|
|
|
2021-02-23 09:48:29 -06:00
|
|
|
AstNode *assign_data = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_data, false));
|
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-01-01 14:18:28 -06:00
|
|
|
assign_data->children[0]->str = id_data;
|
|
|
|
assign_data->children[0]->was_checked = true;
|
|
|
|
defNode->children.push_back(assign_data);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-01-01 14:18:28 -06:00
|
|
|
node_data = new AstNode(AST_IDENTIFIER);
|
|
|
|
node_data->str = id_data;
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2021-05-20 19:27:06 -05:00
|
|
|
AstNode *wire_en = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
|
|
|
|
wire_en->str = id_en;
|
|
|
|
wire_en->was_checked = true;
|
|
|
|
current_ast_mod->children.push_back(wire_en);
|
|
|
|
current_scope[wire_en->str] = wire_en;
|
2023-04-04 15:59:44 -05:00
|
|
|
while (wire_en->simplify(true, 1, -1, false)) { }
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2021-05-20 19:27:06 -05:00
|
|
|
AstNode *assign_en_first = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, mem_width));
|
|
|
|
assign_en_first->children[0]->str = id_en;
|
|
|
|
assign_en_first->children[0]->was_checked = true;
|
|
|
|
defNode->children.push_back(assign_en_first);
|
|
|
|
|
|
|
|
AstNode *node_en = new AstNode(AST_IDENTIFIER);
|
|
|
|
node_en->str = id_en;
|
2013-01-05 04:13:26 -06:00
|
|
|
|
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-01-01 14:18:28 -06:00
|
|
|
if (!defNode->children.empty())
|
|
|
|
current_top_block->children.insert(current_top_block->children.begin(), defNode);
|
|
|
|
else
|
|
|
|
delete defNode;
|
2013-01-05 04:13:26 -06:00
|
|
|
|
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-01-01 14:18:28 -06:00
|
|
|
AstNode *assign_data = nullptr;
|
|
|
|
AstNode *assign_en = nullptr;
|
2014-07-17 06:13:21 -05:00
|
|
|
if (children[0]->children.size() == 2)
|
|
|
|
{
|
|
|
|
if (children[0]->children[1]->range_valid)
|
|
|
|
{
|
|
|
|
int offset = children[0]->children[1]->range_right;
|
|
|
|
int width = children[0]->children[1]->range_left - offset + 1;
|
2016-08-22 07:27:46 -05:00
|
|
|
offset -= mem_data_range_offset;
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-07-17 06:13:21 -05:00
|
|
|
std::vector<RTLIL::State> padding_x(offset, RTLIL::State::Sx);
|
|
|
|
|
2021-02-23 09:48:29 -06:00
|
|
|
assign_data = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER),
|
2014-07-17 06:13:21 -05:00
|
|
|
new AstNode(AST_CONCAT, mkconst_bits(padding_x, false), children[1]->clone()));
|
|
|
|
assign_data->children[0]->str = id_data;
|
2018-06-05 09:44:24 -05:00
|
|
|
assign_data->children[0]->was_checked = true;
|
2014-07-17 06:13:21 -05:00
|
|
|
|
2021-05-20 19:27:06 -05:00
|
|
|
for (int i = 0; i < mem_width; i++)
|
|
|
|
set_bits_en[i] = offset <= i && i < offset+width ? RTLIL::State::S1 : RTLIL::State::S0;
|
|
|
|
assign_en = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_bits(set_bits_en, false));
|
|
|
|
assign_en->children[0]->str = id_en;
|
|
|
|
assign_en->children[0]->was_checked = true;
|
2014-07-17 06:13:21 -05:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2014-07-17 09:49:23 -05:00
|
|
|
AstNode *the_range = children[0]->children[1];
|
2023-04-04 04:34:17 -05:00
|
|
|
AstNode *offset_ast;
|
|
|
|
int width;
|
|
|
|
|
|
|
|
if (!try_determine_range_width(the_range, width))
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
|
2023-04-04 04:34:17 -05:00
|
|
|
|
|
|
|
if (the_range->children.size() >= 2)
|
|
|
|
offset_ast = the_range->children[1]->clone();
|
|
|
|
else
|
|
|
|
offset_ast = the_range->children[0]->clone();
|
2014-07-17 09:49:23 -05:00
|
|
|
|
2016-08-22 07:27:46 -05:00
|
|
|
if (mem_data_range_offset)
|
|
|
|
offset_ast = new AstNode(AST_SUB, offset_ast, mkconst_int(mem_data_range_offset, true));
|
|
|
|
|
2021-02-23 09:48:29 -06:00
|
|
|
assign_data = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER),
|
2014-07-17 09:49:23 -05:00
|
|
|
new AstNode(AST_SHIFT_LEFT, children[1]->clone(), offset_ast->clone()));
|
|
|
|
assign_data->children[0]->str = id_data;
|
2018-06-05 09:44:24 -05:00
|
|
|
assign_data->children[0]->was_checked = true;
|
2014-07-17 09:49:23 -05:00
|
|
|
|
2021-05-20 19:27:06 -05:00
|
|
|
for (int i = 0; i < mem_width; i++)
|
|
|
|
set_bits_en[i] = i < width ? RTLIL::State::S1 : RTLIL::State::S0;
|
|
|
|
assign_en = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER),
|
|
|
|
new AstNode(AST_SHIFT_LEFT, mkconst_bits(set_bits_en, false), offset_ast->clone()));
|
|
|
|
assign_en->children[0]->str = id_en;
|
|
|
|
assign_en->children[0]->was_checked = true;
|
2014-07-17 09:49:23 -05:00
|
|
|
delete offset_ast;
|
2014-07-17 06:13:21 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-01-01 14:18:28 -06:00
|
|
|
if (!(children[0]->children.size() == 1 && children[1]->isConst())) {
|
2021-02-23 09:48:29 -06:00
|
|
|
assign_data = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), children[1]->clone());
|
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-01-01 14:18:28 -06:00
|
|
|
assign_data->children[0]->str = id_data;
|
|
|
|
assign_data->children[0]->was_checked = true;
|
|
|
|
}
|
2014-07-17 06:13:21 -05:00
|
|
|
|
2021-05-20 19:27:06 -05:00
|
|
|
assign_en = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_bits(set_bits_en, false));
|
|
|
|
assign_en->children[0]->str = id_en;
|
|
|
|
assign_en->children[0]->was_checked = true;
|
2014-07-17 06:13:21 -05:00
|
|
|
}
|
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-01-01 14:18:28 -06:00
|
|
|
if (assign_data)
|
|
|
|
newNode->children.push_back(assign_data);
|
|
|
|
if (assign_en)
|
2015-02-14 03:49:30 -06:00
|
|
|
newNode->children.push_back(assign_en);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2021-05-20 19:27:06 -05:00
|
|
|
AstNode *wrnode;
|
|
|
|
if (current_always->type == AST_INITIAL)
|
|
|
|
wrnode = new AstNode(AST_MEMINIT, node_addr, node_data, node_en, mkconst_int(1, false));
|
|
|
|
else
|
|
|
|
wrnode = new AstNode(AST_MEMWR, node_addr, node_data, node_en);
|
2013-01-05 04:13:26 -06:00
|
|
|
wrnode->str = children[0]->str;
|
2015-02-14 07:21:15 -06:00
|
|
|
wrnode->id2ast = children[0]->id2ast;
|
2021-02-23 09:48:29 -06:00
|
|
|
wrnode->location = location;
|
|
|
|
if (wrnode->type == AST_MEMWR) {
|
|
|
|
int portid = current_memwr_count[wrnode->str]++;
|
|
|
|
wrnode->children.push_back(mkconst_int(portid, false));
|
|
|
|
std::vector<RTLIL::State> priority_mask;
|
|
|
|
for (int i = 0; i < portid; i++) {
|
|
|
|
bool has_prio = current_memwr_visible[wrnode->str].count(i);
|
|
|
|
priority_mask.push_back(State(has_prio));
|
|
|
|
}
|
|
|
|
wrnode->children.push_back(mkconst_bits(priority_mask, false));
|
|
|
|
current_memwr_visible[wrnode->str].insert(portid);
|
|
|
|
current_always->children.push_back(wrnode);
|
|
|
|
} else {
|
|
|
|
current_ast_mod->children.push_back(wrnode);
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-01-01 14:18:28 -06:00
|
|
|
if (newNode->children.empty()) {
|
|
|
|
delete newNode;
|
|
|
|
newNode = new AstNode();
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
|
|
|
// replace function and task calls with the code from the function or task
|
|
|
|
if ((type == AST_FCALL || type == AST_TCALL) && !str.empty())
|
|
|
|
{
|
2013-12-04 14:19:54 -06:00
|
|
|
if (type == AST_FCALL)
|
|
|
|
{
|
2016-07-21 07:23:22 -05:00
|
|
|
if (str == "\\$initstate")
|
|
|
|
{
|
|
|
|
int myidx = autoidx++;
|
|
|
|
|
|
|
|
AstNode *wire = new AstNode(AST_WIRE);
|
|
|
|
wire->str = stringf("$initstate$%d_wire", myidx);
|
|
|
|
current_ast_mod->children.push_back(wire);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (wire->simplify(true, 1, -1, false)) { }
|
2016-07-21 07:23:22 -05:00
|
|
|
|
|
|
|
AstNode *cell = new AstNode(AST_CELL, new AstNode(AST_CELLTYPE), new AstNode(AST_ARGUMENT, new AstNode(AST_IDENTIFIER)));
|
|
|
|
cell->str = stringf("$initstate$%d", myidx);
|
|
|
|
cell->children[0]->str = "$initstate";
|
|
|
|
cell->children[1]->str = "\\Y";
|
|
|
|
cell->children[1]->children[0]->str = wire->str;
|
|
|
|
cell->children[1]->children[0]->id2ast = wire;
|
|
|
|
current_ast_mod->children.push_back(cell);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (cell->simplify(true, 1, -1, false)) { }
|
2016-07-21 07:23:22 -05:00
|
|
|
|
|
|
|
newNode = new AstNode(AST_IDENTIFIER);
|
|
|
|
newNode->str = wire->str;
|
|
|
|
newNode->id2ast = wire;
|
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
2016-09-18 18:30:07 -05:00
|
|
|
if (str == "\\$past")
|
|
|
|
{
|
2019-02-21 10:55:33 -06:00
|
|
|
if (width_hint < 0)
|
2016-09-18 18:30:07 -05:00
|
|
|
goto replace_fcall_later;
|
|
|
|
|
|
|
|
int num_steps = 1;
|
|
|
|
|
|
|
|
if (GetSize(children) != 1 && GetSize(children) != 2)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("System function %s got %d arguments, expected 1 or 2.\n",
|
2018-11-04 03:19:32 -06:00
|
|
|
RTLIL::unescape_id(str).c_str(), int(children.size()));
|
2016-09-18 18:30:07 -05:00
|
|
|
|
|
|
|
if (!current_always_clocked)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("System function %s is only allowed in clocked blocks.\n",
|
2018-11-04 03:19:32 -06:00
|
|
|
RTLIL::unescape_id(str).c_str());
|
2016-09-18 18:30:07 -05:00
|
|
|
|
|
|
|
if (GetSize(children) == 2)
|
|
|
|
{
|
|
|
|
AstNode *buf = children[1]->clone();
|
2023-04-04 15:59:44 -05:00
|
|
|
while (buf->simplify(true, stage, -1, false)) { }
|
2016-09-18 18:30:07 -05:00
|
|
|
if (buf->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
|
2016-09-18 18:30:07 -05:00
|
|
|
|
|
|
|
num_steps = buf->asInt(true);
|
|
|
|
delete buf;
|
|
|
|
}
|
|
|
|
|
|
|
|
AstNode *block = nullptr;
|
|
|
|
|
|
|
|
for (auto child : current_always->children)
|
|
|
|
if (child->type == AST_BLOCK)
|
|
|
|
block = child;
|
|
|
|
|
|
|
|
log_assert(block != nullptr);
|
|
|
|
|
2018-12-18 10:49:38 -06:00
|
|
|
if (num_steps == 0) {
|
|
|
|
newNode = children[0]->clone();
|
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
2016-09-18 18:30:07 -05:00
|
|
|
int myidx = autoidx++;
|
|
|
|
AstNode *outreg = nullptr;
|
|
|
|
|
|
|
|
for (int i = 0; i < num_steps; i++)
|
|
|
|
{
|
|
|
|
AstNode *reg = new AstNode(AST_WIRE, new AstNode(AST_RANGE,
|
|
|
|
mkconst_int(width_hint-1, true), mkconst_int(0, true)));
|
|
|
|
|
2022-08-08 09:13:33 -05:00
|
|
|
reg->str = stringf("$past$%s:%d$%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, myidx, i);
|
2016-09-18 18:30:07 -05:00
|
|
|
reg->is_reg = true;
|
2022-05-24 10:18:53 -05:00
|
|
|
reg->is_signed = sign_hint;
|
2016-09-18 18:30:07 -05:00
|
|
|
|
|
|
|
current_ast_mod->children.push_back(reg);
|
|
|
|
|
2023-04-04 15:59:44 -05:00
|
|
|
while (reg->simplify(true, 1, -1, false)) { }
|
2016-09-18 18:30:07 -05:00
|
|
|
|
|
|
|
AstNode *regid = new AstNode(AST_IDENTIFIER);
|
|
|
|
regid->str = reg->str;
|
|
|
|
regid->id2ast = reg;
|
2018-09-17 17:23:40 -05:00
|
|
|
regid->was_checked = true;
|
2016-09-18 18:30:07 -05:00
|
|
|
|
|
|
|
AstNode *rhs = nullptr;
|
|
|
|
|
|
|
|
if (outreg == nullptr) {
|
|
|
|
rhs = children.at(0)->clone();
|
|
|
|
} else {
|
|
|
|
rhs = new AstNode(AST_IDENTIFIER);
|
|
|
|
rhs->str = outreg->str;
|
|
|
|
rhs->id2ast = outreg;
|
|
|
|
}
|
|
|
|
|
|
|
|
block->children.push_back(new AstNode(AST_ASSIGN_LE, regid, rhs));
|
|
|
|
outreg = reg;
|
|
|
|
}
|
|
|
|
|
|
|
|
newNode = new AstNode(AST_IDENTIFIER);
|
|
|
|
newNode->str = outreg->str;
|
|
|
|
newNode->id2ast = outreg;
|
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
2018-10-01 12:41:35 -05:00
|
|
|
if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell" || str == "\\$changed")
|
2016-09-18 18:30:07 -05:00
|
|
|
{
|
|
|
|
if (GetSize(children) != 1)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("System function %s got %d arguments, expected 1.\n",
|
2018-11-04 03:19:32 -06:00
|
|
|
RTLIL::unescape_id(str).c_str(), int(children.size()));
|
2016-09-18 18:30:07 -05:00
|
|
|
|
|
|
|
if (!current_always_clocked)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("System function %s is only allowed in clocked blocks.\n",
|
2018-11-04 03:19:32 -06:00
|
|
|
RTLIL::unescape_id(str).c_str());
|
2016-09-18 18:30:07 -05:00
|
|
|
|
|
|
|
AstNode *present = children.at(0)->clone();
|
|
|
|
AstNode *past = clone();
|
|
|
|
past->str = "\\$past";
|
|
|
|
|
|
|
|
if (str == "\\$stable")
|
|
|
|
newNode = new AstNode(AST_EQ, past, present);
|
|
|
|
|
2018-10-01 12:41:35 -05:00
|
|
|
else if (str == "\\$changed")
|
|
|
|
newNode = new AstNode(AST_NE, past, present);
|
|
|
|
|
2016-09-18 18:30:07 -05:00
|
|
|
else if (str == "\\$rose")
|
2018-11-03 12:39:32 -05:00
|
|
|
newNode = new AstNode(AST_LOGIC_AND,
|
2018-11-04 03:19:32 -06:00
|
|
|
new AstNode(AST_LOGIC_NOT, new AstNode(AST_BIT_AND, past, mkconst_int(1,false))),
|
2018-11-03 12:39:32 -05:00
|
|
|
new AstNode(AST_BIT_AND, present, mkconst_int(1,false)));
|
2016-09-18 18:30:07 -05:00
|
|
|
|
|
|
|
else if (str == "\\$fell")
|
2018-11-03 12:39:32 -05:00
|
|
|
newNode = new AstNode(AST_LOGIC_AND,
|
2018-11-04 03:19:32 -06:00
|
|
|
new AstNode(AST_BIT_AND, past, mkconst_int(1,false)),
|
|
|
|
new AstNode(AST_LOGIC_NOT, new AstNode(AST_BIT_AND, present, mkconst_int(1,false))));
|
2016-09-18 18:30:07 -05:00
|
|
|
|
|
|
|
else
|
|
|
|
log_abort();
|
|
|
|
|
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
2016-10-14 08:24:03 -05:00
|
|
|
// $anyconst and $anyseq are mapped in AstNode::genRTLIL()
|
2018-02-23 06:14:47 -06:00
|
|
|
if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") {
|
2016-09-18 18:30:07 -05:00
|
|
|
recursion_counter--;
|
2016-07-27 08:41:22 -05:00
|
|
|
return false;
|
2016-09-18 18:30:07 -05:00
|
|
|
}
|
2016-07-27 08:41:22 -05:00
|
|
|
|
2013-12-04 14:19:54 -06:00
|
|
|
if (str == "\\$clog2")
|
|
|
|
{
|
2014-06-14 06:36:23 -05:00
|
|
|
if (children.size() != 1)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("System function %s got %d arguments, expected 1.\n",
|
2018-11-04 03:19:32 -06:00
|
|
|
RTLIL::unescape_id(str).c_str(), int(children.size()));
|
2014-06-14 06:36:23 -05:00
|
|
|
|
2013-12-04 14:19:54 -06:00
|
|
|
AstNode *buf = children[0]->clone();
|
2023-04-04 15:59:44 -05:00
|
|
|
while (buf->simplify(true, stage, width_hint, sign_hint)) { }
|
2014-01-12 14:04:42 -06:00
|
|
|
if (buf->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
|
2013-12-04 14:19:54 -06:00
|
|
|
|
|
|
|
RTLIL::Const arg_value = buf->bitsAsConst();
|
2014-09-08 05:25:23 -05:00
|
|
|
if (arg_value.as_bool())
|
2014-10-10 09:59:44 -05:00
|
|
|
arg_value = const_sub(arg_value, 1, false, false, GetSize(arg_value));
|
2014-07-25 06:07:31 -05:00
|
|
|
delete buf;
|
|
|
|
|
2013-12-04 14:19:54 -06:00
|
|
|
uint32_t result = 0;
|
|
|
|
for (size_t i = 0; i < arg_value.bits.size(); i++)
|
|
|
|
if (arg_value.bits.at(i) == RTLIL::State::S1)
|
2014-09-06 12:31:04 -05:00
|
|
|
result = i + 1;
|
2013-12-04 14:19:54 -06:00
|
|
|
|
2018-11-24 11:49:23 -06:00
|
|
|
newNode = mkconst_int(result, true);
|
2013-12-04 14:19:54 -06:00
|
|
|
goto apply_newNode;
|
2013-11-20 04:05:58 -06:00
|
|
|
}
|
2017-09-25 22:25:42 -05:00
|
|
|
|
2023-12-27 17:23:59 -06:00
|
|
|
if (str == "\\$dimensions" || str == "\\$unpacked_dimensions" ||
|
|
|
|
str == "\\$increment" || str == "\\$size" || str == "\\$bits" || str == "\\$high" || str == "\\$low" || str == "\\$left" || str == "\\$right")
|
2017-09-25 22:25:42 -05:00
|
|
|
{
|
2017-09-26 11:18:25 -05:00
|
|
|
int dim = 1;
|
2023-12-27 17:23:59 -06:00
|
|
|
if (str == "\\$dimensions" || str == "\\$unpacked_dimensions" || str == "\\$bits") {
|
2020-09-15 12:49:52 -05:00
|
|
|
if (children.size() != 1)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("System function %s got %d arguments, expected 1.\n",
|
2020-09-15 12:49:52 -05:00
|
|
|
RTLIL::unescape_id(str).c_str(), int(children.size()));
|
|
|
|
} else {
|
|
|
|
if (children.size() != 1 && children.size() != 2)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("System function %s got %d arguments, expected 1 or 2.\n",
|
2020-09-15 12:49:52 -05:00
|
|
|
RTLIL::unescape_id(str).c_str(), int(children.size()));
|
|
|
|
if (children.size() == 2) {
|
|
|
|
AstNode *buf = children[1]->clone();
|
|
|
|
// Evaluate constant expression
|
2023-04-04 15:59:44 -05:00
|
|
|
while (buf->simplify(true, stage, width_hint, sign_hint)) { }
|
2020-09-15 12:49:52 -05:00
|
|
|
dim = buf->asInt(false);
|
|
|
|
delete buf;
|
|
|
|
}
|
2017-09-26 11:18:25 -05:00
|
|
|
}
|
2017-09-25 22:25:42 -05:00
|
|
|
AstNode *buf = children[0]->clone();
|
2017-09-26 01:11:25 -05:00
|
|
|
int mem_depth = 1;
|
2020-09-15 12:49:52 -05:00
|
|
|
int result, high = 0, low = 0, left = 0, right = 0, width = 1; // defaults for a simple wire
|
2023-12-27 17:23:59 -06:00
|
|
|
int expr_dimensions = 0, expr_unpacked_dimensions = 0;
|
2017-09-26 01:11:25 -05:00
|
|
|
AstNode *id_ast = NULL;
|
2017-09-26 11:18:25 -05:00
|
|
|
|
2017-09-25 22:25:42 -05:00
|
|
|
buf->detectSignWidth(width_hint, sign_hint);
|
2017-09-26 12:34:24 -05:00
|
|
|
|
2017-09-26 11:18:25 -05:00
|
|
|
if (buf->type == AST_IDENTIFIER) {
|
|
|
|
id_ast = buf->id2ast;
|
|
|
|
if (id_ast == NULL && current_scope.count(buf->str))
|
|
|
|
id_ast = current_scope.at(buf->str);
|
|
|
|
if (!id_ast)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Failed to resolve identifier %s for width detection!\n", buf->str.c_str());
|
2023-02-09 12:27:51 -06:00
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
if (id_ast->type == AST_WIRE || id_ast->type == AST_MEMORY) {
|
|
|
|
// Check for item in packed struct / union
|
|
|
|
AstNode *item_node = buf->get_struct_member();
|
|
|
|
if (item_node)
|
|
|
|
id_ast = item_node;
|
|
|
|
|
2023-02-09 12:27:51 -06:00
|
|
|
// The dimension of the original array expression is saved in the 'integer' field
|
|
|
|
dim += buf->integer;
|
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
int dims = GetSize(id_ast->dimensions);
|
|
|
|
// TODO: IEEE Std 1800-2017 20.7: "If the first argument to an array query function would cause $dimensions to return 0
|
|
|
|
// or if the second argument is out of range, then 'x shall be returned."
|
|
|
|
if (dim < 1 || dim > dims)
|
|
|
|
input_error("Dimension %d out of range in `%s', as it only has %d dimensions!\n", dim, id_ast->str.c_str(), dims);
|
2023-12-27 17:23:59 -06:00
|
|
|
|
|
|
|
expr_dimensions = dims - dim + 1;
|
|
|
|
expr_unpacked_dimensions = std::max(id_ast->unpacked_dimensions - dim + 1, 0);
|
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
right = low = id_ast->dimensions[dim - 1].range_right;
|
|
|
|
left = high = low + id_ast->dimensions[dim - 1].range_width - 1;
|
|
|
|
if (id_ast->dimensions[dim - 1].range_swapped) {
|
|
|
|
std::swap(left, right);
|
|
|
|
}
|
|
|
|
for (int i = dim; i < dims; i++) {
|
|
|
|
mem_depth *= id_ast->dimensions[i].range_width;
|
2017-09-26 01:11:25 -05:00
|
|
|
}
|
|
|
|
}
|
2020-09-15 12:49:52 -05:00
|
|
|
width = high - low + 1;
|
|
|
|
} else {
|
|
|
|
width = width_hint;
|
2023-12-27 17:23:59 -06:00
|
|
|
right = low = 0;
|
|
|
|
left = high = width - 1;
|
|
|
|
expr_dimensions = 1;
|
2017-09-26 01:11:25 -05:00
|
|
|
}
|
2017-09-25 22:25:42 -05:00
|
|
|
delete buf;
|
2023-12-27 17:23:59 -06:00
|
|
|
if (str == "\\$dimensions")
|
|
|
|
result = expr_dimensions;
|
|
|
|
else if (str == "\\$unpacked_dimensions")
|
|
|
|
result = expr_unpacked_dimensions;
|
|
|
|
else if (str == "\\$high")
|
2020-09-15 12:49:52 -05:00
|
|
|
result = high;
|
|
|
|
else if (str == "\\$low")
|
|
|
|
result = low;
|
|
|
|
else if (str == "\\$left")
|
|
|
|
result = left;
|
|
|
|
else if (str == "\\$right")
|
|
|
|
result = right;
|
2023-12-27 15:00:13 -06:00
|
|
|
else if (str == "\\$increment")
|
|
|
|
result = left >= right ? 1 : -1;
|
2020-09-15 12:49:52 -05:00
|
|
|
else if (str == "\\$size")
|
|
|
|
result = width;
|
2023-02-09 12:27:51 -06:00
|
|
|
else { // str == "\\$bits"
|
2020-09-15 12:49:52 -05:00
|
|
|
result = width * mem_depth;
|
|
|
|
}
|
2022-05-20 14:46:39 -05:00
|
|
|
newNode = mkconst_int(result, true);
|
2017-09-25 22:25:42 -05:00
|
|
|
goto apply_newNode;
|
|
|
|
}
|
2013-12-04 14:19:54 -06:00
|
|
|
|
2014-06-14 06:36:23 -05:00
|
|
|
if (str == "\\$ln" || str == "\\$log10" || str == "\\$exp" || str == "\\$sqrt" || str == "\\$pow" ||
|
|
|
|
str == "\\$floor" || str == "\\$ceil" || str == "\\$sin" || str == "\\$cos" || str == "\\$tan" ||
|
|
|
|
str == "\\$asin" || str == "\\$acos" || str == "\\$atan" || str == "\\$atan2" || str == "\\$hypot" ||
|
2017-01-03 10:40:58 -06:00
|
|
|
str == "\\$sinh" || str == "\\$cosh" || str == "\\$tanh" || str == "\\$asinh" || str == "\\$acosh" || str == "\\$atanh" ||
|
|
|
|
str == "\\$rtoi" || str == "\\$itor")
|
2014-06-14 06:36:23 -05:00
|
|
|
{
|
|
|
|
bool func_with_two_arguments = str == "\\$pow" || str == "\\$atan2" || str == "\\$hypot";
|
|
|
|
double x = 0, y = 0;
|
|
|
|
|
|
|
|
if (func_with_two_arguments) {
|
|
|
|
if (children.size() != 2)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("System function %s got %d arguments, expected 2.\n",
|
2018-11-04 03:19:32 -06:00
|
|
|
RTLIL::unescape_id(str).c_str(), int(children.size()));
|
2014-06-14 06:36:23 -05:00
|
|
|
} else {
|
|
|
|
if (children.size() != 1)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("System function %s got %d arguments, expected 1.\n",
|
2018-11-04 03:19:32 -06:00
|
|
|
RTLIL::unescape_id(str).c_str(), int(children.size()));
|
2014-06-14 06:36:23 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
if (children.size() >= 1) {
|
2023-04-04 15:59:44 -05:00
|
|
|
while (children[0]->simplify(true, stage, width_hint, sign_hint)) { }
|
2014-06-14 06:36:23 -05:00
|
|
|
if (!children[0]->isConst())
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Failed to evaluate system function `%s' with non-constant argument.\n",
|
2018-11-04 03:19:32 -06:00
|
|
|
RTLIL::unescape_id(str).c_str());
|
2014-06-14 06:36:23 -05:00
|
|
|
int child_width_hint = width_hint;
|
|
|
|
bool child_sign_hint = sign_hint;
|
|
|
|
children[0]->detectSignWidth(child_width_hint, child_sign_hint);
|
|
|
|
x = children[0]->asReal(child_sign_hint);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (children.size() >= 2) {
|
2023-04-04 15:59:44 -05:00
|
|
|
while (children[1]->simplify(true, stage, width_hint, sign_hint)) { }
|
2014-06-14 06:36:23 -05:00
|
|
|
if (!children[1]->isConst())
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Failed to evaluate system function `%s' with non-constant argument.\n",
|
2018-11-04 03:19:32 -06:00
|
|
|
RTLIL::unescape_id(str).c_str());
|
2014-06-14 06:36:23 -05:00
|
|
|
int child_width_hint = width_hint;
|
|
|
|
bool child_sign_hint = sign_hint;
|
|
|
|
children[1]->detectSignWidth(child_width_hint, child_sign_hint);
|
|
|
|
y = children[1]->asReal(child_sign_hint);
|
|
|
|
}
|
|
|
|
|
2017-01-03 10:40:58 -06:00
|
|
|
if (str == "\\$rtoi") {
|
|
|
|
newNode = AstNode::mkconst_int(x, true);
|
|
|
|
} else {
|
|
|
|
newNode = new AstNode(AST_REALVALUE);
|
|
|
|
if (str == "\\$ln") newNode->realvalue = ::log(x);
|
|
|
|
else if (str == "\\$log10") newNode->realvalue = ::log10(x);
|
|
|
|
else if (str == "\\$exp") newNode->realvalue = ::exp(x);
|
|
|
|
else if (str == "\\$sqrt") newNode->realvalue = ::sqrt(x);
|
|
|
|
else if (str == "\\$pow") newNode->realvalue = ::pow(x, y);
|
|
|
|
else if (str == "\\$floor") newNode->realvalue = ::floor(x);
|
|
|
|
else if (str == "\\$ceil") newNode->realvalue = ::ceil(x);
|
|
|
|
else if (str == "\\$sin") newNode->realvalue = ::sin(x);
|
|
|
|
else if (str == "\\$cos") newNode->realvalue = ::cos(x);
|
|
|
|
else if (str == "\\$tan") newNode->realvalue = ::tan(x);
|
|
|
|
else if (str == "\\$asin") newNode->realvalue = ::asin(x);
|
|
|
|
else if (str == "\\$acos") newNode->realvalue = ::acos(x);
|
|
|
|
else if (str == "\\$atan") newNode->realvalue = ::atan(x);
|
|
|
|
else if (str == "\\$atan2") newNode->realvalue = ::atan2(x, y);
|
|
|
|
else if (str == "\\$hypot") newNode->realvalue = ::hypot(x, y);
|
|
|
|
else if (str == "\\$sinh") newNode->realvalue = ::sinh(x);
|
|
|
|
else if (str == "\\$cosh") newNode->realvalue = ::cosh(x);
|
|
|
|
else if (str == "\\$tanh") newNode->realvalue = ::tanh(x);
|
|
|
|
else if (str == "\\$asinh") newNode->realvalue = ::asinh(x);
|
|
|
|
else if (str == "\\$acosh") newNode->realvalue = ::acosh(x);
|
|
|
|
else if (str == "\\$atanh") newNode->realvalue = ::atanh(x);
|
|
|
|
else if (str == "\\$itor") newNode->realvalue = x;
|
|
|
|
else log_abort();
|
|
|
|
}
|
2014-06-14 06:36:23 -05:00
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
2020-01-19 15:15:51 -06:00
|
|
|
if (str == "\\$sformatf") {
|
2020-11-29 02:57:07 -06:00
|
|
|
Fmt fmt = processFormat(stage, /*sformat_like=*/true);
|
|
|
|
newNode = AstNode::mkconst_str(fmt.render());
|
2020-01-19 15:15:51 -06:00
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
2021-02-22 17:55:55 -06:00
|
|
|
if (str == "\\$countbits") {
|
|
|
|
if (children.size() < 2)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("System function %s got %d arguments, expected at least 2.\n",
|
2021-02-22 17:55:55 -06:00
|
|
|
RTLIL::unescape_id(str).c_str(), int(children.size()));
|
|
|
|
|
|
|
|
std::vector<RTLIL::State> control_bits;
|
|
|
|
|
|
|
|
// Determine which bits to count
|
|
|
|
for (size_t i = 1; i < children.size(); i++) {
|
|
|
|
AstNode *node = children[i];
|
2023-04-04 15:59:44 -05:00
|
|
|
while (node->simplify(true, stage, -1, false)) { }
|
2021-02-22 17:55:55 -06:00
|
|
|
if (node->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Failed to evaluate system function `%s' with non-constant control bit argument.\n", str.c_str());
|
2021-02-22 17:55:55 -06:00
|
|
|
if (node->bits.size() != 1)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Failed to evaluate system function `%s' with control bit width != 1.\n", str.c_str());
|
2021-02-22 17:55:55 -06:00
|
|
|
control_bits.push_back(node->bits[0]);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Detect width of exp (first argument of $countbits)
|
|
|
|
int exp_width = -1;
|
|
|
|
bool exp_sign = false;
|
|
|
|
AstNode *exp = children[0];
|
|
|
|
exp->detectSignWidth(exp_width, exp_sign, NULL);
|
|
|
|
|
|
|
|
newNode = mkconst_int(0, false);
|
|
|
|
|
|
|
|
for (int i = 0; i < exp_width; i++) {
|
|
|
|
// Generate nodes for: exp << i >> ($size(exp) - 1)
|
|
|
|
// ^^ ^^
|
|
|
|
AstNode *lsh_node = new AstNode(AST_SHIFT_LEFT, exp->clone(), mkconst_int(i, false));
|
|
|
|
AstNode *rsh_node = new AstNode(AST_SHIFT_RIGHT, lsh_node, mkconst_int(exp_width - 1, false));
|
|
|
|
|
|
|
|
AstNode *or_node = nullptr;
|
|
|
|
|
|
|
|
for (RTLIL::State control_bit : control_bits) {
|
|
|
|
// Generate node for: (exp << i >> ($size(exp) - 1)) === control_bit
|
|
|
|
// ^^^
|
|
|
|
AstNode *eq_node = new AstNode(AST_EQX, rsh_node->clone(), mkconst_bits({control_bit}, false));
|
|
|
|
|
|
|
|
// Or the result for each checked bit value
|
|
|
|
if (or_node)
|
|
|
|
or_node = new AstNode(AST_LOGIC_OR, or_node, eq_node);
|
|
|
|
else
|
|
|
|
or_node = eq_node;
|
|
|
|
}
|
|
|
|
|
|
|
|
// We should have at least one element in control_bits,
|
|
|
|
// because we checked for the number of arguments above
|
|
|
|
log_assert(or_node != nullptr);
|
|
|
|
|
|
|
|
delete rsh_node;
|
|
|
|
|
|
|
|
// Generate node for adding with result of previous bit
|
|
|
|
newNode = new AstNode(AST_ADD, newNode, or_node);
|
|
|
|
}
|
|
|
|
|
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
2021-02-22 18:19:06 -06:00
|
|
|
if (str == "\\$countones" || str == "\\$isunknown" || str == "\\$onehot" || str == "\\$onehot0") {
|
|
|
|
if (children.size() != 1)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("System function %s got %d arguments, expected 1.\n",
|
2021-02-22 18:19:06 -06:00
|
|
|
RTLIL::unescape_id(str).c_str(), int(children.size()));
|
|
|
|
|
|
|
|
AstNode *countbits = clone();
|
|
|
|
countbits->str = "\\$countbits";
|
|
|
|
|
|
|
|
if (str == "\\$countones") {
|
|
|
|
countbits->children.push_back(mkconst_bits({RTLIL::State::S1}, false));
|
|
|
|
newNode = countbits;
|
|
|
|
} else if (str == "\\$isunknown") {
|
|
|
|
countbits->children.push_back(mkconst_bits({RTLIL::Sx}, false));
|
|
|
|
countbits->children.push_back(mkconst_bits({RTLIL::Sz}, false));
|
|
|
|
newNode = new AstNode(AST_GT, countbits, mkconst_int(0, false));
|
|
|
|
} else if (str == "\\$onehot") {
|
|
|
|
countbits->children.push_back(mkconst_bits({RTLIL::State::S1}, false));
|
|
|
|
newNode = new AstNode(AST_EQ, countbits, mkconst_int(1, false));
|
|
|
|
} else if (str == "\\$onehot0") {
|
|
|
|
countbits->children.push_back(mkconst_bits({RTLIL::State::S1}, false));
|
|
|
|
newNode = new AstNode(AST_LE, countbits, mkconst_int(1, false));
|
|
|
|
} else {
|
|
|
|
log_abort();
|
|
|
|
}
|
|
|
|
|
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
2014-08-21 05:43:51 -05:00
|
|
|
if (current_scope.count(str) != 0 && current_scope[str]->type == AST_DPI_FUNCTION)
|
|
|
|
{
|
|
|
|
AstNode *dpi_decl = current_scope[str];
|
|
|
|
|
|
|
|
std::string rtype, fname;
|
|
|
|
std::vector<std::string> argtypes;
|
|
|
|
std::vector<AstNode*> args;
|
|
|
|
|
|
|
|
rtype = RTLIL::unescape_id(dpi_decl->children.at(0)->str);
|
2014-08-21 10:22:04 -05:00
|
|
|
fname = RTLIL::unescape_id(dpi_decl->children.at(1)->str);
|
2014-08-21 05:43:51 -05:00
|
|
|
|
2014-10-10 09:59:44 -05:00
|
|
|
for (int i = 2; i < GetSize(dpi_decl->children); i++)
|
2014-08-21 05:43:51 -05:00
|
|
|
{
|
2014-10-10 09:59:44 -05:00
|
|
|
if (i-2 >= GetSize(children))
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Insufficient number of arguments in DPI function call.\n");
|
2014-08-21 05:43:51 -05:00
|
|
|
|
|
|
|
argtypes.push_back(RTLIL::unescape_id(dpi_decl->children.at(i)->str));
|
2014-08-21 10:22:04 -05:00
|
|
|
args.push_back(children.at(i-2)->clone());
|
2023-04-04 15:59:44 -05:00
|
|
|
while (args.back()->simplify(true, stage, -1, false)) { }
|
2014-08-21 05:43:51 -05:00
|
|
|
|
|
|
|
if (args.back()->type != AST_CONSTANT && args.back()->type != AST_REALVALUE)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Failed to evaluate DPI function with non-constant argument.\n");
|
2014-08-21 05:43:51 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
newNode = dpi_call(rtype, fname, argtypes, args);
|
2014-08-21 06:09:47 -05:00
|
|
|
|
|
|
|
for (auto arg : args)
|
|
|
|
delete arg;
|
|
|
|
|
2014-08-21 05:43:51 -05:00
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
2022-10-29 14:14:11 -05:00
|
|
|
if (current_scope.count(str) == 0)
|
|
|
|
str = try_pop_module_prefix();
|
2013-12-04 14:19:54 -06:00
|
|
|
if (current_scope.count(str) == 0 || current_scope[str]->type != AST_FUNCTION)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Can't resolve function name `%s'.\n", str.c_str());
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
2015-09-18 02:50:53 -05:00
|
|
|
|
2015-09-17 22:34:56 -05:00
|
|
|
if (type == AST_TCALL)
|
|
|
|
{
|
2016-03-21 10:19:51 -05:00
|
|
|
if (str == "$finish" || str == "$stop")
|
2015-09-17 22:34:56 -05:00
|
|
|
{
|
2015-09-18 02:50:53 -05:00
|
|
|
if (!current_always || current_always->type != AST_INITIAL)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("System task `%s' outside initial block is unsupported.\n", str.c_str());
|
2015-09-18 02:50:53 -05:00
|
|
|
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("System task `%s' executed.\n", str.c_str());
|
2015-09-17 22:34:56 -05:00
|
|
|
}
|
|
|
|
|
2014-10-26 14:33:10 -05:00
|
|
|
if (str == "\\$readmemh" || str == "\\$readmemb")
|
|
|
|
{
|
|
|
|
if (GetSize(children) < 2 || GetSize(children) > 4)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("System function %s got %d arguments, expected 2-4.\n",
|
2018-11-04 03:19:32 -06:00
|
|
|
RTLIL::unescape_id(str).c_str(), int(children.size()));
|
2014-10-26 14:33:10 -05:00
|
|
|
|
|
|
|
AstNode *node_filename = children[0]->clone();
|
2023-04-04 15:59:44 -05:00
|
|
|
while (node_filename->simplify(true, stage, width_hint, sign_hint)) { }
|
2014-10-26 14:33:10 -05:00
|
|
|
if (node_filename->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str());
|
2014-10-26 14:33:10 -05:00
|
|
|
|
|
|
|
AstNode *node_memory = children[1]->clone();
|
2023-04-04 15:59:44 -05:00
|
|
|
while (node_memory->simplify(true, stage, width_hint, sign_hint)) { }
|
2014-10-26 14:33:10 -05:00
|
|
|
if (node_memory->type != AST_IDENTIFIER || node_memory->id2ast == nullptr || node_memory->id2ast->type != AST_MEMORY)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str.c_str());
|
2014-10-26 14:33:10 -05:00
|
|
|
|
|
|
|
int start_addr = -1, finish_addr = -1;
|
|
|
|
|
|
|
|
if (GetSize(children) > 2) {
|
|
|
|
AstNode *node_addr = children[2]->clone();
|
2023-04-04 15:59:44 -05:00
|
|
|
while (node_addr->simplify(true, stage, width_hint, sign_hint)) { }
|
2014-10-26 14:33:10 -05:00
|
|
|
if (node_addr->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str.c_str());
|
2016-02-13 10:31:24 -06:00
|
|
|
start_addr = int(node_addr->asInt(false));
|
2014-10-26 14:33:10 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
if (GetSize(children) > 3) {
|
|
|
|
AstNode *node_addr = children[3]->clone();
|
2023-04-04 15:59:44 -05:00
|
|
|
while (node_addr->simplify(true, stage, width_hint, sign_hint)) { }
|
2014-10-26 14:33:10 -05:00
|
|
|
if (node_addr->type != AST_CONSTANT)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Failed to evaluate system function `%s' with non-constant 4th argument.\n", str.c_str());
|
2016-02-13 10:31:24 -06:00
|
|
|
finish_addr = int(node_addr->asInt(false));
|
2014-10-26 14:33:10 -05:00
|
|
|
}
|
|
|
|
|
2015-07-31 03:40:09 -05:00
|
|
|
bool unconditional_init = false;
|
|
|
|
if (current_always->type == AST_INITIAL) {
|
2015-09-30 08:46:51 -05:00
|
|
|
pool<AstNode*> queue;
|
2015-07-31 03:40:09 -05:00
|
|
|
log_assert(current_always->children[0]->type == AST_BLOCK);
|
2015-09-30 08:46:51 -05:00
|
|
|
queue.insert(current_always->children[0]);
|
|
|
|
while (!unconditional_init && !queue.empty()) {
|
|
|
|
pool<AstNode*> next_queue;
|
|
|
|
for (auto n : queue)
|
|
|
|
for (auto c : n->children) {
|
|
|
|
if (c == this)
|
|
|
|
unconditional_init = true;
|
|
|
|
next_queue.insert(c);
|
2015-07-31 03:40:09 -05:00
|
|
|
}
|
2015-09-30 08:46:51 -05:00
|
|
|
next_queue.swap(queue);
|
|
|
|
}
|
2015-07-31 03:40:09 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
newNode = readmem(str == "\\$readmemh", node_filename->bitsAsConst().decode_string(), node_memory->id2ast, start_addr, finish_addr, unconditional_init);
|
2019-03-02 11:58:20 -06:00
|
|
|
delete node_filename;
|
|
|
|
delete node_memory;
|
2014-10-26 14:33:10 -05:00
|
|
|
goto apply_newNode;
|
|
|
|
}
|
|
|
|
|
2022-10-29 14:14:11 -05:00
|
|
|
if (current_scope.count(str) == 0)
|
|
|
|
str = try_pop_module_prefix();
|
2013-01-05 04:13:26 -06:00
|
|
|
if (current_scope.count(str) == 0 || current_scope[str]->type != AST_TASK)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Can't resolve task name `%s'.\n", str.c_str());
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
2014-08-18 07:29:30 -05:00
|
|
|
|
|
|
|
std::stringstream sstr;
|
2022-08-08 09:13:33 -05:00
|
|
|
sstr << str << "$func$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++) << '.';
|
2014-08-18 07:29:30 -05:00
|
|
|
std::string prefix = sstr.str();
|
|
|
|
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
AstNode *decl = current_scope[str];
|
2021-02-12 13:25:34 -06:00
|
|
|
if (unevaluated_tern_branch && decl->is_recursive_function())
|
|
|
|
goto replace_fcall_later;
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
decl = decl->clone();
|
|
|
|
decl->replace_result_wire_name_in_function(str, "$result"); // enables recursion
|
|
|
|
decl->expand_genblock(prefix);
|
|
|
|
|
2021-01-27 12:21:13 -06:00
|
|
|
if (decl->type == AST_FUNCTION && !decl->attributes.count(ID::via_celltype))
|
2014-02-14 12:56:44 -06:00
|
|
|
{
|
2021-01-27 12:21:13 -06:00
|
|
|
bool require_const_eval = decl->has_const_only_constructs();
|
2014-02-14 12:56:44 -06:00
|
|
|
bool all_args_const = true;
|
2014-02-16 06:16:38 -06:00
|
|
|
for (auto child : children) {
|
2023-04-04 15:59:44 -05:00
|
|
|
while (child->simplify(true, 1, -1, false)) { }
|
2020-07-19 21:27:09 -05:00
|
|
|
if (child->type != AST_CONSTANT && child->type != AST_REALVALUE)
|
2014-02-14 12:56:44 -06:00
|
|
|
all_args_const = false;
|
2014-02-16 06:16:38 -06:00
|
|
|
}
|
2014-02-14 12:56:44 -06:00
|
|
|
|
|
|
|
if (all_args_const) {
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
AstNode *func_workspace = decl->clone();
|
2023-04-05 04:00:07 -05:00
|
|
|
func_workspace->set_in_param_flag(true);
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
func_workspace->str = prefix_id(prefix, "$result");
|
2021-01-27 12:21:13 -06:00
|
|
|
newNode = func_workspace->eval_const_function(this, in_param || require_const_eval);
|
2014-02-14 12:56:44 -06:00
|
|
|
delete func_workspace;
|
2021-01-27 12:21:13 -06:00
|
|
|
if (newNode) {
|
|
|
|
delete decl;
|
|
|
|
goto apply_newNode;
|
|
|
|
}
|
2014-02-14 12:56:44 -06:00
|
|
|
}
|
|
|
|
|
2014-06-06 15:55:02 -05:00
|
|
|
if (in_param)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Non-constant function call in constant expression.\n");
|
2014-06-06 17:02:05 -05:00
|
|
|
if (require_const_eval)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Function %s can only be called with constant arguments.\n", str.c_str());
|
2014-02-14 12:56:44 -06:00
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
size_t arg_count = 0;
|
2015-11-23 10:09:57 -06:00
|
|
|
dict<std::string, AstNode*> wire_cache;
|
2019-03-08 00:44:37 -06:00
|
|
|
vector<AstNode*> new_stmts;
|
|
|
|
vector<AstNode*> output_assignments;
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
if (current_block == NULL)
|
|
|
|
{
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(type == AST_FCALL);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
AstNode *wire = NULL;
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
std::string res_name = prefix_id(prefix, "$result");
|
2013-01-05 04:13:26 -06:00
|
|
|
for (auto child : decl->children)
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
if (child->type == AST_WIRE && child->str == res_name)
|
2013-01-05 04:13:26 -06:00
|
|
|
wire = child->clone();
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(wire != NULL);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
wire->port_id = 0;
|
|
|
|
wire->is_input = false;
|
|
|
|
wire->is_output = false;
|
|
|
|
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
current_scope[wire->str] = wire;
|
2013-01-05 04:13:26 -06:00
|
|
|
current_ast_mod->children.push_back(wire);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (wire->simplify(true, 1, -1, false)) { }
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
AstNode *lvalue = new AstNode(AST_IDENTIFIER);
|
|
|
|
lvalue->str = wire->str;
|
|
|
|
|
|
|
|
AstNode *always = new AstNode(AST_ALWAYS, new AstNode(AST_BLOCK,
|
|
|
|
new AstNode(AST_ASSIGN_EQ, lvalue, clone())));
|
2018-09-17 17:23:40 -05:00
|
|
|
always->children[0]->children[0]->was_checked = true;
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
current_ast_mod->children.push_back(always);
|
|
|
|
|
|
|
|
goto replace_fcall_with_id;
|
|
|
|
}
|
|
|
|
|
2020-05-04 12:48:37 -05:00
|
|
|
if (decl->attributes.count(ID::via_celltype))
|
2014-08-18 07:29:30 -05:00
|
|
|
{
|
2020-05-04 12:48:37 -05:00
|
|
|
std::string celltype = decl->attributes.at(ID::via_celltype)->asAttrConst().decode_string();
|
2014-08-18 07:29:30 -05:00
|
|
|
std::string outport = str;
|
|
|
|
|
|
|
|
if (celltype.find(' ') != std::string::npos) {
|
|
|
|
int pos = celltype.find(' ');
|
|
|
|
outport = RTLIL::escape_id(celltype.substr(pos+1));
|
|
|
|
celltype = RTLIL::escape_id(celltype.substr(0, pos));
|
|
|
|
} else
|
|
|
|
celltype = RTLIL::escape_id(celltype);
|
|
|
|
|
|
|
|
AstNode *cell = new AstNode(AST_CELL, new AstNode(AST_CELLTYPE));
|
2014-10-10 09:59:44 -05:00
|
|
|
cell->str = prefix.substr(0, GetSize(prefix)-1);
|
2014-08-18 07:29:30 -05:00
|
|
|
cell->children[0]->str = celltype;
|
|
|
|
|
|
|
|
for (auto attr : decl->attributes)
|
|
|
|
if (attr.first.str().rfind("\\via_celltype_defparam_", 0) == 0)
|
|
|
|
{
|
|
|
|
AstNode *cell_arg = new AstNode(AST_PARASET, attr.second->clone());
|
2019-08-06 21:08:33 -05:00
|
|
|
cell_arg->str = RTLIL::escape_id(attr.first.substr(strlen("\\via_celltype_defparam_")));
|
2014-08-18 07:29:30 -05:00
|
|
|
cell->children.push_back(cell_arg);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (auto child : decl->children)
|
|
|
|
if (child->type == AST_WIRE && (child->is_input || child->is_output || (type == AST_FCALL && child->str == str)))
|
|
|
|
{
|
|
|
|
AstNode *wire = child->clone();
|
|
|
|
wire->port_id = 0;
|
|
|
|
wire->is_input = false;
|
|
|
|
wire->is_output = false;
|
|
|
|
current_ast_mod->children.push_back(wire);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (wire->simplify(true, 1, -1, false)) { }
|
2014-08-18 07:29:30 -05:00
|
|
|
|
|
|
|
AstNode *wire_id = new AstNode(AST_IDENTIFIER);
|
|
|
|
wire_id->str = wire->str;
|
|
|
|
|
|
|
|
if ((child->is_input || child->is_output) && arg_count < children.size())
|
|
|
|
{
|
|
|
|
AstNode *arg = children[arg_count++]->clone();
|
|
|
|
AstNode *assign = child->is_input ?
|
2014-08-21 10:33:40 -05:00
|
|
|
new AstNode(AST_ASSIGN_EQ, wire_id->clone(), arg) :
|
|
|
|
new AstNode(AST_ASSIGN_EQ, arg, wire_id->clone());
|
2018-09-17 17:23:40 -05:00
|
|
|
assign->children[0]->was_checked = true;
|
2014-08-18 07:29:30 -05:00
|
|
|
|
|
|
|
for (auto it = current_block->children.begin(); it != current_block->children.end(); it++) {
|
|
|
|
if (*it != current_block_child)
|
|
|
|
continue;
|
|
|
|
current_block->children.insert(it, assign);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-08-21 10:33:40 -05:00
|
|
|
AstNode *cell_arg = new AstNode(AST_ARGUMENT, wire_id);
|
2014-08-18 07:29:30 -05:00
|
|
|
cell_arg->str = child->str == str ? outport : child->str;
|
|
|
|
cell->children.push_back(cell_arg);
|
|
|
|
}
|
|
|
|
|
|
|
|
current_ast_mod->children.push_back(cell);
|
|
|
|
goto replace_fcall_with_id;
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
for (auto child : decl->children)
|
2018-03-09 06:47:11 -06:00
|
|
|
if (child->type == AST_WIRE || child->type == AST_MEMORY || child->type == AST_PARAMETER || child->type == AST_LOCALPARAM || child->type == AST_ENUM_ITEM)
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
2015-11-23 10:09:57 -06:00
|
|
|
AstNode *wire = nullptr;
|
|
|
|
|
|
|
|
if (wire_cache.count(child->str))
|
|
|
|
{
|
|
|
|
wire = wire_cache.at(child->str);
|
2020-08-29 12:31:02 -05:00
|
|
|
bool contains_value = wire->type == AST_LOCALPARAM;
|
|
|
|
if (wire->children.size() == contains_value) {
|
2015-11-23 10:09:57 -06:00
|
|
|
for (auto c : child->children)
|
|
|
|
wire->children.push_back(c->clone());
|
2017-02-14 08:10:59 -06:00
|
|
|
} else if (!child->children.empty()) {
|
2023-04-04 15:59:44 -05:00
|
|
|
while (child->simplify(true, stage, -1, false)) { }
|
2020-08-29 12:31:02 -05:00
|
|
|
if (GetSize(child->children) == GetSize(wire->children) - contains_value) {
|
2017-02-14 08:10:59 -06:00
|
|
|
for (int i = 0; i < GetSize(child->children); i++)
|
2020-08-29 12:31:02 -05:00
|
|
|
if (*child->children.at(i) != *wire->children.at(i + contains_value))
|
2017-02-14 08:10:59 -06:00
|
|
|
goto tcall_incompatible_wires;
|
|
|
|
} else {
|
|
|
|
tcall_incompatible_wires:
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Incompatible re-declaration of wire %s.\n", child->str.c_str());
|
2017-02-14 08:10:59 -06:00
|
|
|
}
|
2015-11-23 10:09:57 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
wire = child->clone();
|
|
|
|
wire->port_id = 0;
|
|
|
|
wire->is_input = false;
|
|
|
|
wire->is_output = false;
|
2019-03-08 00:44:37 -06:00
|
|
|
wire->is_reg = true;
|
2023-04-05 04:00:07 -05:00
|
|
|
wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
|
2020-02-17 03:40:02 -06:00
|
|
|
if (child->type == AST_ENUM_ITEM)
|
2023-04-05 04:00:07 -05:00
|
|
|
wire->set_attribute(ID::enum_base_type, child->attributes[ID::enum_base_type]);
|
2020-02-03 00:12:24 -06:00
|
|
|
|
2015-11-23 10:09:57 -06:00
|
|
|
wire_cache[child->str] = wire;
|
|
|
|
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
current_scope[wire->str] = wire;
|
2015-11-23 10:09:57 -06:00
|
|
|
current_ast_mod->children.push_back(wire);
|
|
|
|
}
|
2015-11-12 06:02:36 -06:00
|
|
|
|
2023-04-04 15:59:44 -05:00
|
|
|
while (wire->simplify(true, 1, -1, false)) { }
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-08-14 15:26:10 -05:00
|
|
|
if ((child->is_input || child->is_output) && arg_count < children.size())
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
|
|
|
AstNode *arg = children[arg_count++]->clone();
|
2020-07-24 22:18:24 -05:00
|
|
|
// convert purely constant arguments into localparams
|
|
|
|
if (child->is_input && child->type == AST_WIRE && arg->type == AST_CONSTANT && node_contains_assignment_to(decl, child)) {
|
|
|
|
wire->type = AST_LOCALPARAM;
|
2021-03-16 10:43:03 -05:00
|
|
|
if (wire->attributes.count(ID::nosync))
|
|
|
|
delete wire->attributes.at(ID::nosync);
|
2020-07-24 22:18:24 -05:00
|
|
|
wire->attributes.erase(ID::nosync);
|
|
|
|
wire->children.insert(wire->children.begin(), arg->clone());
|
2020-12-05 19:56:18 -06:00
|
|
|
// args without a range implicitly have width 1
|
|
|
|
if (wire->children.back()->type != AST_RANGE) {
|
2020-12-26 09:39:57 -06:00
|
|
|
// check if this wire is redeclared with an explicit size
|
|
|
|
bool uses_explicit_size = false;
|
|
|
|
for (const AstNode *other_child : decl->children)
|
|
|
|
if (other_child->type == AST_WIRE && child->str == other_child->str
|
|
|
|
&& !other_child->children.empty()
|
|
|
|
&& other_child->children.back()->type == AST_RANGE) {
|
|
|
|
uses_explicit_size = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (!uses_explicit_size) {
|
|
|
|
AstNode* range = new AstNode();
|
|
|
|
range->type = AST_RANGE;
|
|
|
|
wire->children.push_back(range);
|
|
|
|
range->children.push_back(mkconst_int(0, true));
|
|
|
|
range->children.push_back(mkconst_int(0, true));
|
|
|
|
}
|
2020-12-05 19:56:18 -06:00
|
|
|
}
|
2023-04-05 04:00:07 -05:00
|
|
|
wire->fixup_hierarchy_flags();
|
2021-02-21 13:45:21 -06:00
|
|
|
// updates the sizing
|
2023-04-04 15:59:44 -05:00
|
|
|
while (wire->simplify(true, 1, -1, false)) { }
|
2021-03-16 10:43:03 -05:00
|
|
|
delete arg;
|
2020-07-24 22:18:24 -05:00
|
|
|
continue;
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
AstNode *wire_id = new AstNode(AST_IDENTIFIER);
|
|
|
|
wire_id->str = wire->str;
|
2014-08-14 15:26:10 -05:00
|
|
|
AstNode *assign = child->is_input ?
|
|
|
|
new AstNode(AST_ASSIGN_EQ, wire_id, arg) :
|
|
|
|
new AstNode(AST_ASSIGN_EQ, arg, wire_id);
|
2018-09-17 17:23:40 -05:00
|
|
|
assign->children[0]->was_checked = true;
|
2019-03-08 00:44:37 -06:00
|
|
|
if (child->is_input)
|
|
|
|
new_stmts.push_back(assign);
|
|
|
|
else
|
|
|
|
output_assignments.push_back(assign);
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
}
|
2014-08-05 01:35:51 -05:00
|
|
|
|
|
|
|
for (auto child : decl->children)
|
2017-01-05 06:18:58 -06:00
|
|
|
if (child->type != AST_WIRE && child->type != AST_MEMORY && child->type != AST_PARAMETER && child->type != AST_LOCALPARAM)
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
new_stmts.push_back(child->clone());
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2019-03-08 00:44:37 -06:00
|
|
|
new_stmts.insert(new_stmts.end(), output_assignments.begin(), output_assignments.end());
|
|
|
|
|
|
|
|
for (auto it = current_block->children.begin(); ; it++) {
|
|
|
|
log_assert(it != current_block->children.end());
|
|
|
|
if (*it == current_block_child) {
|
|
|
|
current_block->children.insert(it, new_stmts.begin(), new_stmts.end());
|
|
|
|
break;
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
2019-03-08 00:44:37 -06:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
replace_fcall_with_id:
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
delete decl;
|
2013-01-05 04:13:26 -06:00
|
|
|
if (type == AST_FCALL) {
|
|
|
|
delete_children();
|
|
|
|
type = AST_IDENTIFIER;
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
str = prefix_id(prefix, "$result");
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
if (type == AST_TCALL)
|
|
|
|
str = "";
|
|
|
|
did_something = true;
|
|
|
|
}
|
|
|
|
|
2016-09-18 18:30:07 -05:00
|
|
|
replace_fcall_later:;
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
// perform const folding when activated
|
2014-08-17 17:02:30 -05:00
|
|
|
if (const_fold)
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
2013-12-05 06:26:17 -06:00
|
|
|
bool string_op;
|
2013-06-10 06:56:03 -05:00
|
|
|
std::vector<RTLIL::State> tmp_bits;
|
2013-01-05 04:13:26 -06:00
|
|
|
RTLIL::Const (*const_func)(const RTLIL::Const&, const RTLIL::Const&, bool, bool, int);
|
|
|
|
RTLIL::Const dummy_arg;
|
|
|
|
|
|
|
|
switch (type)
|
|
|
|
{
|
|
|
|
case AST_IDENTIFIER:
|
2018-03-09 06:47:11 -06:00
|
|
|
if (current_scope.count(str) > 0 && (current_scope[str]->type == AST_PARAMETER || current_scope[str]->type == AST_LOCALPARAM || current_scope[str]->type == AST_ENUM_ITEM)) {
|
2013-11-07 07:08:53 -06:00
|
|
|
if (current_scope[str]->children[0]->type == AST_CONSTANT) {
|
|
|
|
if (children.size() != 0 && children[0]->type == AST_RANGE && children[0]->range_valid) {
|
2013-01-05 04:13:26 -06:00
|
|
|
std::vector<RTLIL::State> data;
|
2014-07-28 09:45:26 -05:00
|
|
|
bool param_upto = current_scope[str]->range_valid && current_scope[str]->range_swapped;
|
|
|
|
int param_offset = current_scope[str]->range_valid ? current_scope[str]->range_right : 0;
|
|
|
|
int param_width = current_scope[str]->range_valid ? current_scope[str]->range_left - current_scope[str]->range_right + 1 :
|
2014-10-10 09:59:44 -05:00
|
|
|
GetSize(current_scope[str]->children[0]->bits);
|
2014-07-28 09:45:26 -05:00
|
|
|
int tmp_range_left = children[0]->range_left, tmp_range_right = children[0]->range_right;
|
|
|
|
if (param_upto) {
|
|
|
|
tmp_range_left = (param_width + 2*param_offset) - children[0]->range_right - 1;
|
|
|
|
tmp_range_right = (param_width + 2*param_offset) - children[0]->range_left - 1;
|
|
|
|
}
|
2024-01-25 00:28:15 -06:00
|
|
|
AstNode *member_node = get_struct_member();
|
2023-02-28 11:45:55 -06:00
|
|
|
int chunk_offset = member_node ? member_node->range_right : 0;
|
|
|
|
log_assert(!(chunk_offset && param_upto));
|
2014-07-28 09:45:26 -05:00
|
|
|
for (int i = tmp_range_right; i <= tmp_range_left; i++) {
|
|
|
|
int index = i - param_offset;
|
|
|
|
if (0 <= index && index < param_width)
|
2023-02-28 11:45:55 -06:00
|
|
|
data.push_back(current_scope[str]->children[0]->bits[chunk_offset + index]);
|
2014-07-28 09:45:26 -05:00
|
|
|
else
|
|
|
|
data.push_back(RTLIL::State::Sx);
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
newNode = mkconst_bits(data, false);
|
2013-11-07 07:08:53 -06:00
|
|
|
} else
|
|
|
|
if (children.size() == 0)
|
|
|
|
newNode = current_scope[str]->children[0]->clone();
|
2014-06-14 04:27:05 -05:00
|
|
|
} else
|
|
|
|
if (current_scope[str]->children[0]->isConst())
|
|
|
|
newNode = current_scope[str]->children[0]->clone();
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case AST_BIT_NOT:
|
|
|
|
if (children[0]->type == AST_CONSTANT) {
|
2013-11-04 08:37:09 -06:00
|
|
|
RTLIL::Const y = RTLIL::const_not(children[0]->bitsAsConst(width_hint, sign_hint), dummy_arg, sign_hint, false, width_hint);
|
|
|
|
newNode = mkconst_bits(y.bits, sign_hint);
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
break;
|
2013-12-05 06:09:41 -06:00
|
|
|
case AST_TO_SIGNED:
|
|
|
|
case AST_TO_UNSIGNED:
|
|
|
|
if (children[0]->type == AST_CONSTANT) {
|
|
|
|
RTLIL::Const y = children[0]->bitsAsConst(width_hint, sign_hint);
|
|
|
|
newNode = mkconst_bits(y.bits, type == AST_TO_SIGNED);
|
|
|
|
}
|
|
|
|
break;
|
2013-01-05 04:13:26 -06:00
|
|
|
if (0) { case AST_BIT_AND: const_func = RTLIL::const_and; }
|
|
|
|
if (0) { case AST_BIT_OR: const_func = RTLIL::const_or; }
|
|
|
|
if (0) { case AST_BIT_XOR: const_func = RTLIL::const_xor; }
|
|
|
|
if (0) { case AST_BIT_XNOR: const_func = RTLIL::const_xnor; }
|
|
|
|
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
|
2013-11-04 08:37:09 -06:00
|
|
|
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
|
|
|
|
children[1]->bitsAsConst(width_hint, sign_hint), sign_hint, sign_hint, width_hint);
|
|
|
|
newNode = mkconst_bits(y.bits, sign_hint);
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
if (0) { case AST_REDUCE_AND: const_func = RTLIL::const_reduce_and; }
|
|
|
|
if (0) { case AST_REDUCE_OR: const_func = RTLIL::const_reduce_or; }
|
|
|
|
if (0) { case AST_REDUCE_XOR: const_func = RTLIL::const_reduce_xor; }
|
|
|
|
if (0) { case AST_REDUCE_XNOR: const_func = RTLIL::const_reduce_xnor; }
|
|
|
|
if (0) { case AST_REDUCE_BOOL: const_func = RTLIL::const_reduce_bool; }
|
2013-06-10 06:19:04 -05:00
|
|
|
if (children[0]->type == AST_CONSTANT) {
|
2013-11-04 08:37:09 -06:00
|
|
|
RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), dummy_arg, false, false, -1);
|
2013-01-05 04:13:26 -06:00
|
|
|
newNode = mkconst_bits(y.bits, false);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case AST_LOGIC_NOT:
|
|
|
|
if (children[0]->type == AST_CONSTANT) {
|
|
|
|
RTLIL::Const y = RTLIL::const_logic_not(RTLIL::Const(children[0]->bits), dummy_arg, children[0]->is_signed, false, -1);
|
|
|
|
newNode = mkconst_bits(y.bits, false);
|
2014-06-14 04:27:05 -05:00
|
|
|
} else
|
|
|
|
if (children[0]->isConst()) {
|
|
|
|
newNode = mkconst_int(children[0]->asReal(sign_hint) == 0, false, 1);
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
if (0) { case AST_LOGIC_AND: const_func = RTLIL::const_logic_and; }
|
|
|
|
if (0) { case AST_LOGIC_OR: const_func = RTLIL::const_logic_or; }
|
|
|
|
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
|
|
|
|
RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), RTLIL::Const(children[1]->bits),
|
|
|
|
children[0]->is_signed, children[1]->is_signed, -1);
|
|
|
|
newNode = mkconst_bits(y.bits, false);
|
2014-06-14 04:27:05 -05:00
|
|
|
} else
|
|
|
|
if (children[0]->isConst() && children[1]->isConst()) {
|
|
|
|
if (type == AST_LOGIC_AND)
|
|
|
|
newNode = mkconst_int((children[0]->asReal(sign_hint) != 0) && (children[1]->asReal(sign_hint) != 0), false, 1);
|
|
|
|
else
|
|
|
|
newNode = mkconst_int((children[0]->asReal(sign_hint) != 0) || (children[1]->asReal(sign_hint) != 0), false, 1);
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
if (0) { case AST_SHIFT_LEFT: const_func = RTLIL::const_shl; }
|
|
|
|
if (0) { case AST_SHIFT_RIGHT: const_func = RTLIL::const_shr; }
|
|
|
|
if (0) { case AST_SHIFT_SLEFT: const_func = RTLIL::const_sshl; }
|
|
|
|
if (0) { case AST_SHIFT_SRIGHT: const_func = RTLIL::const_sshr; }
|
2013-11-07 15:20:00 -06:00
|
|
|
if (0) { case AST_POW: const_func = RTLIL::const_pow; }
|
2013-01-05 04:13:26 -06:00
|
|
|
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
|
2013-11-04 08:37:09 -06:00
|
|
|
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
|
2013-11-08 04:06:11 -06:00
|
|
|
RTLIL::Const(children[1]->bits), sign_hint, type == AST_POW ? children[1]->is_signed : false, width_hint);
|
2013-11-04 08:37:09 -06:00
|
|
|
newNode = mkconst_bits(y.bits, sign_hint);
|
2014-06-14 04:27:05 -05:00
|
|
|
} else
|
|
|
|
if (type == AST_POW && children[0]->isConst() && children[1]->isConst()) {
|
|
|
|
newNode = new AstNode(AST_REALVALUE);
|
|
|
|
newNode->realvalue = pow(children[0]->asReal(sign_hint), children[1]->asReal(sign_hint));
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
break;
|
2013-12-27 06:50:08 -06:00
|
|
|
if (0) { case AST_LT: const_func = RTLIL::const_lt; }
|
|
|
|
if (0) { case AST_LE: const_func = RTLIL::const_le; }
|
|
|
|
if (0) { case AST_EQ: const_func = RTLIL::const_eq; }
|
|
|
|
if (0) { case AST_NE: const_func = RTLIL::const_ne; }
|
|
|
|
if (0) { case AST_EQX: const_func = RTLIL::const_eqx; }
|
|
|
|
if (0) { case AST_NEX: const_func = RTLIL::const_nex; }
|
|
|
|
if (0) { case AST_GE: const_func = RTLIL::const_ge; }
|
|
|
|
if (0) { case AST_GT: const_func = RTLIL::const_gt; }
|
2013-01-05 04:13:26 -06:00
|
|
|
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
|
2015-10-25 13:30:49 -05:00
|
|
|
int cmp_width = max(children[0]->bits.size(), children[1]->bits.size());
|
2013-11-04 08:37:09 -06:00
|
|
|
bool cmp_signed = children[0]->is_signed && children[1]->is_signed;
|
|
|
|
RTLIL::Const y = const_func(children[0]->bitsAsConst(cmp_width, cmp_signed),
|
|
|
|
children[1]->bitsAsConst(cmp_width, cmp_signed), cmp_signed, cmp_signed, 1);
|
2013-01-05 04:13:26 -06:00
|
|
|
newNode = mkconst_bits(y.bits, false);
|
2014-06-14 04:27:05 -05:00
|
|
|
} else
|
|
|
|
if (children[0]->isConst() && children[1]->isConst()) {
|
2014-06-17 05:47:51 -05:00
|
|
|
bool cmp_signed = (children[0]->type == AST_REALVALUE || children[0]->is_signed) && (children[1]->type == AST_REALVALUE || children[1]->is_signed);
|
2014-06-14 04:27:05 -05:00
|
|
|
switch (type) {
|
2014-06-17 05:47:51 -05:00
|
|
|
case AST_LT: newNode = mkconst_int(children[0]->asReal(cmp_signed) < children[1]->asReal(cmp_signed), false, 1); break;
|
|
|
|
case AST_LE: newNode = mkconst_int(children[0]->asReal(cmp_signed) <= children[1]->asReal(cmp_signed), false, 1); break;
|
|
|
|
case AST_EQ: newNode = mkconst_int(children[0]->asReal(cmp_signed) == children[1]->asReal(cmp_signed), false, 1); break;
|
|
|
|
case AST_NE: newNode = mkconst_int(children[0]->asReal(cmp_signed) != children[1]->asReal(cmp_signed), false, 1); break;
|
|
|
|
case AST_EQX: newNode = mkconst_int(children[0]->asReal(cmp_signed) == children[1]->asReal(cmp_signed), false, 1); break;
|
|
|
|
case AST_NEX: newNode = mkconst_int(children[0]->asReal(cmp_signed) != children[1]->asReal(cmp_signed), false, 1); break;
|
|
|
|
case AST_GE: newNode = mkconst_int(children[0]->asReal(cmp_signed) >= children[1]->asReal(cmp_signed), false, 1); break;
|
|
|
|
case AST_GT: newNode = mkconst_int(children[0]->asReal(cmp_signed) > children[1]->asReal(cmp_signed), false, 1); break;
|
2014-06-14 04:27:05 -05:00
|
|
|
default: log_abort();
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
if (0) { case AST_ADD: const_func = RTLIL::const_add; }
|
|
|
|
if (0) { case AST_SUB: const_func = RTLIL::const_sub; }
|
|
|
|
if (0) { case AST_MUL: const_func = RTLIL::const_mul; }
|
|
|
|
if (0) { case AST_DIV: const_func = RTLIL::const_div; }
|
|
|
|
if (0) { case AST_MOD: const_func = RTLIL::const_mod; }
|
2014-06-14 04:27:05 -05:00
|
|
|
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
|
|
|
|
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
|
|
|
|
children[1]->bitsAsConst(width_hint, sign_hint), sign_hint, sign_hint, width_hint);
|
|
|
|
newNode = mkconst_bits(y.bits, sign_hint);
|
|
|
|
} else
|
2014-06-14 01:51:22 -05:00
|
|
|
if (children[0]->isConst() && children[1]->isConst()) {
|
2014-06-14 04:27:05 -05:00
|
|
|
newNode = new AstNode(AST_REALVALUE);
|
|
|
|
switch (type) {
|
|
|
|
case AST_ADD: newNode->realvalue = children[0]->asReal(sign_hint) + children[1]->asReal(sign_hint); break;
|
|
|
|
case AST_SUB: newNode->realvalue = children[0]->asReal(sign_hint) - children[1]->asReal(sign_hint); break;
|
|
|
|
case AST_MUL: newNode->realvalue = children[0]->asReal(sign_hint) * children[1]->asReal(sign_hint); break;
|
|
|
|
case AST_DIV: newNode->realvalue = children[0]->asReal(sign_hint) / children[1]->asReal(sign_hint); break;
|
|
|
|
case AST_MOD: newNode->realvalue = fmod(children[0]->asReal(sign_hint), children[1]->asReal(sign_hint)); break;
|
|
|
|
default: log_abort();
|
2014-06-14 01:51:22 -05:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
break;
|
2020-04-29 07:28:04 -05:00
|
|
|
if (0) { case AST_SELFSZ: const_func = RTLIL::const_pos; }
|
2013-01-05 04:13:26 -06:00
|
|
|
if (0) { case AST_POS: const_func = RTLIL::const_pos; }
|
|
|
|
if (0) { case AST_NEG: const_func = RTLIL::const_neg; }
|
|
|
|
if (children[0]->type == AST_CONSTANT) {
|
2013-11-04 08:37:09 -06:00
|
|
|
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint), dummy_arg, sign_hint, false, width_hint);
|
|
|
|
newNode = mkconst_bits(y.bits, sign_hint);
|
2014-06-14 04:27:05 -05:00
|
|
|
} else
|
|
|
|
if (children[0]->isConst()) {
|
|
|
|
newNode = new AstNode(AST_REALVALUE);
|
2020-04-29 07:28:04 -05:00
|
|
|
if (type == AST_NEG)
|
2014-06-14 04:27:05 -05:00
|
|
|
newNode->realvalue = -children[0]->asReal(sign_hint);
|
2020-04-29 07:28:04 -05:00
|
|
|
else
|
|
|
|
newNode->realvalue = +children[0]->asReal(sign_hint);
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case AST_TERNARY:
|
2014-06-16 08:12:24 -05:00
|
|
|
if (children[0]->isConst())
|
|
|
|
{
|
2021-02-12 13:25:34 -06:00
|
|
|
auto pair = get_tern_choice();
|
|
|
|
AstNode *choice = pair.first;
|
|
|
|
AstNode *not_choice = pair.second;
|
2014-06-16 08:12:24 -05:00
|
|
|
|
2014-06-14 04:27:05 -05:00
|
|
|
if (choice != NULL) {
|
|
|
|
if (choice->type == AST_CONSTANT) {
|
2014-06-16 08:12:24 -05:00
|
|
|
int other_width_hint = width_hint;
|
|
|
|
bool other_sign_hint = sign_hint, other_real = false;
|
|
|
|
not_choice->detectSignWidth(other_width_hint, other_sign_hint, &other_real);
|
|
|
|
if (other_real) {
|
|
|
|
newNode = new AstNode(AST_REALVALUE);
|
2014-06-25 03:05:36 -05:00
|
|
|
choice->detectSignWidth(width_hint, sign_hint);
|
2014-06-16 08:12:24 -05:00
|
|
|
newNode->realvalue = choice->asReal(sign_hint);
|
|
|
|
} else {
|
|
|
|
RTLIL::Const y = choice->bitsAsConst(width_hint, sign_hint);
|
|
|
|
if (choice->is_string && y.bits.size() % 8 == 0 && sign_hint == false)
|
|
|
|
newNode = mkconst_str(y.bits);
|
|
|
|
else
|
|
|
|
newNode = mkconst_bits(y.bits, sign_hint);
|
|
|
|
}
|
2014-06-14 04:27:05 -05:00
|
|
|
} else
|
|
|
|
if (choice->isConst()) {
|
|
|
|
newNode = choice->clone();
|
|
|
|
}
|
2013-11-07 21:44:09 -06:00
|
|
|
} else if (children[1]->type == AST_CONSTANT && children[2]->type == AST_CONSTANT) {
|
|
|
|
RTLIL::Const a = children[1]->bitsAsConst(width_hint, sign_hint);
|
|
|
|
RTLIL::Const b = children[2]->bitsAsConst(width_hint, sign_hint);
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(a.bits.size() == b.bits.size());
|
2013-11-07 21:44:09 -06:00
|
|
|
for (size_t i = 0; i < a.bits.size(); i++)
|
|
|
|
if (a.bits[i] != b.bits[i])
|
|
|
|
a.bits[i] = RTLIL::State::Sx;
|
|
|
|
newNode = mkconst_bits(a.bits, sign_hint);
|
2014-06-16 08:05:37 -05:00
|
|
|
} else if (children[1]->isConst() && children[2]->isConst()) {
|
|
|
|
newNode = new AstNode(AST_REALVALUE);
|
|
|
|
if (children[1]->asReal(sign_hint) == children[2]->asReal(sign_hint))
|
|
|
|
newNode->realvalue = children[1]->asReal(sign_hint);
|
|
|
|
else
|
|
|
|
// IEEE Std 1800-2012 Sec. 11.4.11 states that the entry in Table 7-1 for
|
|
|
|
// the data type in question should be returned if the ?: is ambiguous. The
|
|
|
|
// value in Table 7-1 for the 'real' type is 0.0.
|
|
|
|
newNode->realvalue = 0.0;
|
2013-11-04 09:46:14 -06:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
break;
|
2020-06-19 21:09:43 -05:00
|
|
|
case AST_CAST_SIZE:
|
|
|
|
if (children.at(0)->type == AST_CONSTANT && children.at(1)->type == AST_CONSTANT) {
|
|
|
|
int width = children[0]->bitsAsConst().as_int();
|
2021-03-03 13:36:19 -06:00
|
|
|
RTLIL::Const val;
|
|
|
|
if (children[1]->is_unsized)
|
|
|
|
val = children[1]->bitsAsUnsizedConst(width);
|
|
|
|
else
|
|
|
|
val = children[1]->bitsAsConst(width);
|
2020-06-19 21:09:43 -05:00
|
|
|
newNode = mkconst_bits(val.bits, children[1]->is_signed);
|
|
|
|
}
|
|
|
|
break;
|
2013-06-10 06:56:03 -05:00
|
|
|
case AST_CONCAT:
|
2013-12-05 06:26:17 -06:00
|
|
|
string_op = !children.empty();
|
2013-06-10 06:56:03 -05:00
|
|
|
for (auto it = children.begin(); it != children.end(); it++) {
|
|
|
|
if ((*it)->type != AST_CONSTANT)
|
|
|
|
goto not_const;
|
2013-12-05 06:26:17 -06:00
|
|
|
if (!(*it)->is_string)
|
|
|
|
string_op = false;
|
2013-06-10 06:56:03 -05:00
|
|
|
tmp_bits.insert(tmp_bits.end(), (*it)->bits.begin(), (*it)->bits.end());
|
|
|
|
}
|
2013-12-05 06:26:17 -06:00
|
|
|
newNode = string_op ? mkconst_str(tmp_bits) : mkconst_bits(tmp_bits, false);
|
2013-11-07 07:08:53 -06:00
|
|
|
break;
|
|
|
|
case AST_REPLICATE:
|
|
|
|
if (children.at(0)->type != AST_CONSTANT || children.at(1)->type != AST_CONSTANT)
|
|
|
|
goto not_const;
|
|
|
|
for (int i = 0; i < children[0]->bitsAsConst().as_int(); i++)
|
|
|
|
tmp_bits.insert(tmp_bits.end(), children.at(1)->bits.begin(), children.at(1)->bits.end());
|
2013-12-05 06:26:17 -06:00
|
|
|
newNode = children.at(1)->is_string ? mkconst_str(tmp_bits) : mkconst_bits(tmp_bits, false);
|
2013-06-10 06:56:03 -05:00
|
|
|
break;
|
2013-01-05 04:13:26 -06:00
|
|
|
default:
|
2013-06-10 06:56:03 -05:00
|
|
|
not_const:
|
2013-01-05 04:13:26 -06:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// if any of the above set 'newNode' -> use 'newNode' as template to update 'this'
|
|
|
|
if (newNode) {
|
|
|
|
apply_newNode:
|
|
|
|
// fprintf(stderr, "----\n");
|
|
|
|
// dumpAst(stderr, "- ");
|
|
|
|
// newNode->dumpAst(stderr, "+ ");
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(newNode != NULL);
|
2013-01-05 04:13:26 -06:00
|
|
|
newNode->filename = filename;
|
2020-02-23 01:19:52 -06:00
|
|
|
newNode->location = location;
|
2013-01-05 04:13:26 -06:00
|
|
|
newNode->cloneInto(this);
|
2023-04-05 04:00:07 -05:00
|
|
|
fixup_hierarchy_flags();
|
2013-01-05 04:13:26 -06:00
|
|
|
delete newNode;
|
|
|
|
did_something = true;
|
|
|
|
}
|
|
|
|
|
2014-01-20 13:25:20 -06:00
|
|
|
if (!did_something)
|
|
|
|
basic_prep = true;
|
|
|
|
|
2015-02-13 05:33:12 -06:00
|
|
|
recursion_counter--;
|
2013-01-05 04:13:26 -06:00
|
|
|
return did_something;
|
|
|
|
}
|
|
|
|
|
2020-12-31 18:23:36 -06:00
|
|
|
void AstNode::replace_result_wire_name_in_function(const std::string &from, const std::string &to)
|
2013-11-20 04:05:58 -06:00
|
|
|
{
|
2020-12-31 18:23:36 -06:00
|
|
|
for (AstNode *child : children)
|
|
|
|
child->replace_result_wire_name_in_function(from, to);
|
|
|
|
if (str == from && type != AST_FCALL && type != AST_TCALL)
|
|
|
|
str = to;
|
2013-11-20 04:05:58 -06:00
|
|
|
}
|
|
|
|
|
2014-10-26 14:33:10 -05:00
|
|
|
// replace a readmem[bh] TCALL ast node with a block of memory assignments
|
2015-07-31 03:40:09 -05:00
|
|
|
AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init)
|
2014-10-26 14:33:10 -05:00
|
|
|
{
|
2015-09-25 06:49:48 -05:00
|
|
|
int mem_width, mem_size, addr_bits;
|
|
|
|
memory->meminfo(mem_width, mem_size, addr_bits);
|
|
|
|
|
2014-10-26 14:33:10 -05:00
|
|
|
AstNode *block = new AstNode(AST_BLOCK);
|
|
|
|
|
2015-07-31 03:40:09 -05:00
|
|
|
AstNode *meminit = nullptr;
|
2015-08-14 15:22:17 -05:00
|
|
|
int next_meminit_cursor=0;
|
2015-07-31 03:40:09 -05:00
|
|
|
vector<State> meminit_bits;
|
2021-05-20 19:27:06 -05:00
|
|
|
vector<State> en_bits;
|
2015-08-14 15:22:17 -05:00
|
|
|
int meminit_size=0;
|
2015-07-31 03:40:09 -05:00
|
|
|
|
2021-05-20 19:27:06 -05:00
|
|
|
for (int i = 0; i < mem_width; i++)
|
|
|
|
en_bits.push_back(State::S1);
|
|
|
|
|
2014-10-26 14:33:10 -05:00
|
|
|
std::ifstream f;
|
2020-01-31 19:10:51 -06:00
|
|
|
f.open(mem_filename.c_str());
|
|
|
|
if (f.fail()) {
|
2020-02-06 07:10:29 -06:00
|
|
|
#ifdef _WIN32
|
|
|
|
char slash = '\\';
|
|
|
|
#else
|
|
|
|
char slash = '/';
|
|
|
|
#endif
|
|
|
|
std::string path = filename.substr(0, filename.find_last_of(slash)+1);
|
2020-01-31 19:10:51 -06:00
|
|
|
f.open(path + mem_filename.c_str());
|
|
|
|
yosys_input_files.insert(path + mem_filename);
|
|
|
|
} else {
|
|
|
|
yosys_input_files.insert(mem_filename);
|
|
|
|
}
|
2020-02-03 07:30:33 -06:00
|
|
|
if (f.fail() || GetSize(mem_filename) == 0)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Can not open file `%s` for %s.\n", mem_filename.c_str(), str.c_str());
|
2014-10-26 14:33:10 -05:00
|
|
|
|
2014-10-26 17:29:36 -05:00
|
|
|
log_assert(GetSize(memory->children) == 2 && memory->children[1]->type == AST_RANGE && memory->children[1]->range_valid);
|
|
|
|
int range_left = memory->children[1]->range_left, range_right = memory->children[1]->range_right;
|
2015-10-25 13:30:49 -05:00
|
|
|
int range_min = min(range_left, range_right), range_max = max(range_left, range_right);
|
2014-10-26 17:29:36 -05:00
|
|
|
|
|
|
|
if (start_addr < 0)
|
|
|
|
start_addr = range_min;
|
|
|
|
|
|
|
|
if (finish_addr < 0)
|
2015-09-25 06:49:48 -05:00
|
|
|
finish_addr = range_max + 1;
|
2014-10-26 14:33:10 -05:00
|
|
|
|
|
|
|
bool in_comment = false;
|
2014-10-26 17:29:36 -05:00
|
|
|
int increment = start_addr <= finish_addr ? +1 : -1;
|
|
|
|
int cursor = start_addr;
|
2014-10-26 14:33:10 -05:00
|
|
|
|
|
|
|
while (!f.eof())
|
|
|
|
{
|
|
|
|
std::string line, token;
|
|
|
|
std::getline(f, line);
|
|
|
|
|
|
|
|
for (int i = 0; i < GetSize(line); i++) {
|
2019-08-07 14:20:08 -05:00
|
|
|
if (in_comment && line.compare(i, 2, "*/") == 0) {
|
2014-10-26 14:33:10 -05:00
|
|
|
line[i] = ' ';
|
|
|
|
line[i+1] = ' ';
|
|
|
|
in_comment = false;
|
|
|
|
continue;
|
|
|
|
}
|
2019-08-07 14:20:08 -05:00
|
|
|
if (!in_comment && line.compare(i, 2, "/*") == 0)
|
2014-10-26 14:33:10 -05:00
|
|
|
in_comment = true;
|
|
|
|
if (in_comment)
|
|
|
|
line[i] = ' ';
|
|
|
|
}
|
|
|
|
|
|
|
|
while (1)
|
|
|
|
{
|
|
|
|
token = next_token(line, " \t\r\n");
|
2019-08-07 14:20:08 -05:00
|
|
|
if (token.empty() || token.compare(0, 2, "//") == 0)
|
2014-10-26 14:33:10 -05:00
|
|
|
break;
|
|
|
|
|
|
|
|
if (token[0] == '@') {
|
|
|
|
token = token.substr(1);
|
|
|
|
const char *nptr = token.c_str();
|
|
|
|
char *endptr;
|
|
|
|
cursor = strtol(nptr, &endptr, 16);
|
|
|
|
if (!*nptr || *endptr)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Can not parse address `%s` for %s.\n", nptr, str.c_str());
|
2014-10-26 14:33:10 -05:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2015-09-25 06:49:48 -05:00
|
|
|
AstNode *value = VERILOG_FRONTEND::const2ast(stringf("%d'%c", mem_width, is_readmemh ? 'h' : 'b') + token);
|
2014-10-26 14:33:10 -05:00
|
|
|
|
2015-07-31 03:40:09 -05:00
|
|
|
if (unconditional_init)
|
|
|
|
{
|
|
|
|
if (meminit == nullptr || cursor != next_meminit_cursor)
|
|
|
|
{
|
|
|
|
if (meminit != nullptr) {
|
|
|
|
meminit->children[1] = AstNode::mkconst_bits(meminit_bits, false);
|
2021-05-20 19:27:06 -05:00
|
|
|
meminit->children[3] = AstNode::mkconst_int(meminit_size, false);
|
2015-07-31 03:40:09 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
meminit = new AstNode(AST_MEMINIT);
|
|
|
|
meminit->children.push_back(AstNode::mkconst_int(cursor, false));
|
|
|
|
meminit->children.push_back(nullptr);
|
2021-05-20 19:27:06 -05:00
|
|
|
meminit->children.push_back(AstNode::mkconst_bits(en_bits, false));
|
2015-07-31 03:40:09 -05:00
|
|
|
meminit->children.push_back(nullptr);
|
|
|
|
meminit->str = memory->str;
|
|
|
|
meminit->id2ast = memory;
|
|
|
|
meminit_bits.clear();
|
|
|
|
meminit_size = 0;
|
|
|
|
|
|
|
|
current_ast_mod->children.push_back(meminit);
|
|
|
|
next_meminit_cursor = cursor;
|
|
|
|
}
|
|
|
|
|
|
|
|
meminit_size++;
|
|
|
|
next_meminit_cursor++;
|
|
|
|
meminit_bits.insert(meminit_bits.end(), value->bits.begin(), value->bits.end());
|
|
|
|
delete value;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
block->children.push_back(new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER, new AstNode(AST_RANGE, AstNode::mkconst_int(cursor, false))), value));
|
|
|
|
block->children.back()->children[0]->str = memory->str;
|
|
|
|
block->children.back()->children[0]->id2ast = memory;
|
2018-09-17 17:23:40 -05:00
|
|
|
block->children.back()->children[0]->was_checked = true;
|
2015-07-31 03:40:09 -05:00
|
|
|
}
|
2014-10-26 14:33:10 -05:00
|
|
|
|
|
|
|
cursor += increment;
|
2016-08-20 06:47:46 -05:00
|
|
|
if ((cursor == finish_addr+increment) || (increment > 0 && cursor > range_max) || (increment < 0 && cursor < range_min))
|
|
|
|
break;
|
2014-10-26 14:33:10 -05:00
|
|
|
}
|
|
|
|
|
2016-08-20 06:47:46 -05:00
|
|
|
if ((cursor == finish_addr+increment) || (increment > 0 && cursor > range_max) || (increment < 0 && cursor < range_min))
|
2014-10-26 14:33:10 -05:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2015-07-31 03:40:09 -05:00
|
|
|
if (meminit != nullptr) {
|
|
|
|
meminit->children[1] = AstNode::mkconst_bits(meminit_bits, false);
|
2021-05-20 19:27:06 -05:00
|
|
|
meminit->children[3] = AstNode::mkconst_int(meminit_size, false);
|
2015-07-31 03:40:09 -05:00
|
|
|
}
|
|
|
|
|
2014-10-26 14:33:10 -05:00
|
|
|
return block;
|
|
|
|
}
|
|
|
|
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
// annotate the names of all wires and other named objects in a named generate
|
|
|
|
// or procedural block; nested blocks are themselves annotated such that the
|
|
|
|
// prefix is carried forward, but resolution of their children is deferred
|
|
|
|
void AstNode::expand_genblock(const std::string &prefix)
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
2021-08-02 19:42:34 -05:00
|
|
|
if (type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL || type == AST_WIRETYPE || type == AST_PREFIX) {
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
log_assert(!str.empty());
|
|
|
|
|
|
|
|
// search starting in the innermost scope and then stepping outward
|
|
|
|
for (size_t ppos = prefix.size() - 1; ppos; --ppos) {
|
|
|
|
if (prefix.at(ppos) != '.') continue;
|
|
|
|
|
|
|
|
std::string new_prefix = prefix.substr(0, ppos + 1);
|
|
|
|
auto attempt_resolve = [&new_prefix](const std::string &ident) -> std::string {
|
|
|
|
std::string new_name = prefix_id(new_prefix, ident);
|
|
|
|
if (current_scope.count(new_name))
|
|
|
|
return new_name;
|
|
|
|
return {};
|
|
|
|
};
|
|
|
|
|
|
|
|
// attempt to resolve the full identifier
|
|
|
|
std::string resolved = attempt_resolve(str);
|
|
|
|
if (!resolved.empty()) {
|
|
|
|
str = resolved;
|
|
|
|
break;
|
2020-07-31 21:13:05 -05:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
// attempt to resolve hierarchical prefixes within the identifier,
|
|
|
|
// as the prefix could refer to a local scope which exists but
|
|
|
|
// hasn't yet been elaborated
|
|
|
|
for (size_t spos = str.size() - 1; spos; --spos) {
|
|
|
|
if (str.at(spos) != '.') continue;
|
|
|
|
resolved = attempt_resolve(str.substr(0, spos));
|
|
|
|
if (!resolved.empty()) {
|
|
|
|
str = resolved + str.substr(spos);
|
|
|
|
ppos = 1; // break outer loop
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2020-07-31 21:13:05 -05:00
|
|
|
|
|
|
|
}
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
}
|
2020-07-31 21:13:05 -05:00
|
|
|
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
auto prefix_node = [&prefix](AstNode* child) {
|
|
|
|
if (child->str.empty()) return;
|
|
|
|
std::string new_name = prefix_id(prefix, child->str);
|
2020-07-31 21:13:05 -05:00
|
|
|
if (child->type == AST_FUNCTION)
|
2020-12-31 18:23:36 -06:00
|
|
|
child->replace_result_wire_name_in_function(child->str, new_name);
|
2020-07-31 21:13:05 -05:00
|
|
|
else
|
|
|
|
child->str = new_name;
|
|
|
|
current_scope[new_name] = child;
|
|
|
|
};
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
for (size_t i = 0; i < children.size(); i++) {
|
|
|
|
AstNode *child = children[i];
|
2020-07-31 21:13:05 -05:00
|
|
|
|
|
|
|
switch (child->type) {
|
|
|
|
case AST_WIRE:
|
|
|
|
case AST_MEMORY:
|
2024-01-04 10:22:07 -06:00
|
|
|
case AST_STRUCT:
|
|
|
|
case AST_UNION:
|
2020-07-31 21:13:05 -05:00
|
|
|
case AST_PARAMETER:
|
|
|
|
case AST_LOCALPARAM:
|
|
|
|
case AST_FUNCTION:
|
|
|
|
case AST_TASK:
|
|
|
|
case AST_CELL:
|
|
|
|
case AST_TYPEDEF:
|
|
|
|
case AST_ENUM_ITEM:
|
|
|
|
case AST_GENVAR:
|
|
|
|
prefix_node(child);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_BLOCK:
|
|
|
|
case AST_GENBLOCK:
|
|
|
|
if (!child->str.empty())
|
|
|
|
prefix_node(child);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_ENUM:
|
2020-02-03 00:12:24 -06:00
|
|
|
current_scope[child->str] = child;
|
2020-01-16 16:05:45 -06:00
|
|
|
for (auto enode : child->children){
|
|
|
|
log_assert(enode->type == AST_ENUM_ITEM);
|
2020-07-31 21:13:05 -05:00
|
|
|
prefix_node(enode);
|
2020-01-16 16:05:45 -06:00
|
|
|
}
|
2020-07-31 21:13:05 -05:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
2020-01-16 16:05:45 -06:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
for (size_t i = 0; i < children.size(); i++) {
|
|
|
|
AstNode *child = children[i];
|
2021-08-02 19:42:34 -05:00
|
|
|
// AST_PREFIX member names should not be prefixed; we recurse into them
|
|
|
|
// as normal to ensure indices and ranges are properly resolved, and
|
|
|
|
// then restore the previous string
|
|
|
|
if (type == AST_PREFIX && i == 1) {
|
|
|
|
std::string backup_scope_name = child->str;
|
|
|
|
child->expand_genblock(prefix);
|
|
|
|
child->str = backup_scope_name;
|
2019-03-18 19:34:21 -05:00
|
|
|
continue;
|
2021-08-02 19:42:34 -05:00
|
|
|
}
|
2020-07-31 21:13:05 -05:00
|
|
|
// functions/tasks may reference wires, constants, etc. in this scope
|
|
|
|
if (child->type == AST_FUNCTION || child->type == AST_TASK)
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
continue;
|
|
|
|
// named blocks pick up the current prefix and will expanded later
|
|
|
|
if ((child->type == AST_GENBLOCK || child->type == AST_BLOCK) && !child->str.empty())
|
|
|
|
continue;
|
2019-09-19 14:43:13 -05:00
|
|
|
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
child->expand_genblock(prefix);
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
// add implicit AST_GENBLOCK names according to IEEE 1364-2005 Section 12.4.3 or
|
|
|
|
// IEEE 1800-2017 Section 27.6
|
|
|
|
void AstNode::label_genblks(std::set<std::string>& existing, int &counter)
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
switch (type) {
|
|
|
|
case AST_GENIF:
|
|
|
|
case AST_GENFOR:
|
|
|
|
case AST_GENCASE:
|
|
|
|
// seeing a proper generate control flow construct increments the
|
|
|
|
// counter once
|
|
|
|
++counter;
|
|
|
|
for (AstNode *child : children)
|
|
|
|
child->label_genblks(existing, counter);
|
|
|
|
break;
|
2014-08-05 05:15:53 -05:00
|
|
|
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
case AST_GENBLOCK: {
|
|
|
|
// if this block is unlabeled, generate its corresponding unique name
|
|
|
|
for (int padding = 0; str.empty(); ++padding) {
|
|
|
|
std::string candidate = "\\genblk";
|
|
|
|
for (int i = 0; i < padding; ++i)
|
|
|
|
candidate += '0';
|
|
|
|
candidate += std::to_string(counter);
|
|
|
|
if (!existing.count(candidate))
|
|
|
|
str = candidate;
|
|
|
|
}
|
|
|
|
// within a genblk, the counter starts fresh
|
|
|
|
std::set<std::string> existing_local = existing;
|
|
|
|
int counter_local = 0;
|
|
|
|
for (AstNode *child : children)
|
|
|
|
child->label_genblks(existing_local, counter_local);
|
|
|
|
break;
|
2014-08-05 05:15:53 -05:00
|
|
|
}
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
|
|
|
|
default:
|
|
|
|
// track names which could conflict with implicit genblk names
|
|
|
|
if (str.rfind("\\genblk", 0) == 0)
|
|
|
|
existing.insert(str);
|
|
|
|
for (AstNode *child : children)
|
|
|
|
child->label_genblks(existing, counter);
|
|
|
|
break;
|
2014-08-05 05:15:53 -05:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
2014-06-17 14:39:25 -05:00
|
|
|
// helper function for mem2reg_as_needed_pass1
|
2014-12-28 20:11:50 -06:00
|
|
|
static void mark_memories_assign_lhs_complex(dict<AstNode*, pool<std::string>> &mem2reg_places,
|
|
|
|
dict<AstNode*, uint32_t> &mem2reg_candidates, AstNode *that)
|
2014-06-17 14:39:25 -05:00
|
|
|
{
|
|
|
|
for (auto &child : that->children)
|
|
|
|
mark_memories_assign_lhs_complex(mem2reg_places, mem2reg_candidates, child);
|
|
|
|
|
|
|
|
if (that->type == AST_IDENTIFIER && that->id2ast && that->id2ast->type == AST_MEMORY) {
|
|
|
|
AstNode *mem = that->id2ast;
|
|
|
|
if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_CMPLX_LHS))
|
2022-08-08 09:13:33 -05:00
|
|
|
mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(that->filename).c_str(), that->location.first_line));
|
2014-06-17 14:39:25 -05:00
|
|
|
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_CMPLX_LHS;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
// find memories that should be replaced by registers
|
2014-12-28 20:11:50 -06:00
|
|
|
void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg_places,
|
|
|
|
dict<AstNode*, uint32_t> &mem2reg_candidates, dict<AstNode*, uint32_t> &proc_flags, uint32_t &flags)
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
2013-11-21 06:49:00 -06:00
|
|
|
uint32_t children_flags = 0;
|
2019-03-12 14:12:02 -05:00
|
|
|
int lhs_children_counter = 0;
|
2013-11-21 06:49:00 -06:00
|
|
|
|
2019-09-20 05:39:15 -05:00
|
|
|
if (type == AST_TYPEDEF)
|
|
|
|
return; // don't touch content of typedefs
|
|
|
|
|
2013-11-21 06:49:00 -06:00
|
|
|
if (type == AST_ASSIGN || type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ)
|
|
|
|
{
|
2014-06-17 14:39:25 -05:00
|
|
|
// mark all memories that are used in a complex expression on the left side of an assignment
|
|
|
|
for (auto &lhs_child : children[0]->children)
|
|
|
|
mark_memories_assign_lhs_complex(mem2reg_places, mem2reg_candidates, lhs_child);
|
|
|
|
|
2013-11-21 06:49:00 -06:00
|
|
|
if (children[0]->type == AST_IDENTIFIER && children[0]->id2ast && children[0]->id2ast->type == AST_MEMORY)
|
|
|
|
{
|
|
|
|
AstNode *mem = children[0]->id2ast;
|
|
|
|
|
|
|
|
// activate mem2reg if this is assigned in an async proc
|
|
|
|
if (flags & AstNode::MEM2REG_FL_ASYNC) {
|
|
|
|
if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_ASYNC))
|
2022-08-08 09:13:33 -05:00
|
|
|
mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line));
|
2013-11-21 06:49:00 -06:00
|
|
|
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_ASYNC;
|
|
|
|
}
|
|
|
|
|
|
|
|
// remember if this is assigned blocking (=)
|
|
|
|
if (type == AST_ASSIGN_EQ) {
|
|
|
|
if (!(proc_flags[mem] & AstNode::MEM2REG_FL_EQ1))
|
2022-08-08 09:13:33 -05:00
|
|
|
mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line));
|
2013-11-21 06:49:00 -06:00
|
|
|
proc_flags[mem] |= AstNode::MEM2REG_FL_EQ1;
|
|
|
|
}
|
|
|
|
|
2019-03-12 14:09:47 -05:00
|
|
|
// for proper (non-init) writes: remember if this is a constant index or not
|
|
|
|
if ((flags & MEM2REG_FL_INIT) == 0) {
|
|
|
|
if (children[0]->children.size() && children[0]->children[0]->type == AST_RANGE && children[0]->children[0]->children.size()) {
|
|
|
|
if (children[0]->children[0]->children[0]->type == AST_CONSTANT)
|
|
|
|
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_CONST_LHS;
|
|
|
|
else
|
|
|
|
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_VAR_LHS;
|
|
|
|
}
|
2019-03-01 15:35:09 -06:00
|
|
|
}
|
|
|
|
|
2013-11-21 06:49:00 -06:00
|
|
|
// remember where this is
|
|
|
|
if (flags & MEM2REG_FL_INIT) {
|
|
|
|
if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_INIT))
|
2022-08-08 09:13:33 -05:00
|
|
|
mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line));
|
2013-11-21 06:49:00 -06:00
|
|
|
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_INIT;
|
|
|
|
} else {
|
|
|
|
if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_ELSE))
|
2022-08-08 09:13:33 -05:00
|
|
|
mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line));
|
2013-11-21 06:49:00 -06:00
|
|
|
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_ELSE;
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
}
|
2013-11-21 06:49:00 -06:00
|
|
|
|
2019-03-12 14:12:02 -05:00
|
|
|
lhs_children_counter = 1;
|
2013-11-21 06:49:00 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
if (type == AST_IDENTIFIER && id2ast && id2ast->type == AST_MEMORY)
|
|
|
|
{
|
|
|
|
AstNode *mem = id2ast;
|
|
|
|
|
2024-01-25 00:28:15 -06:00
|
|
|
if (integer < (unsigned)mem->unpacked_dimensions)
|
|
|
|
input_error("Insufficient number of array indices for %s.\n", log_id(str));
|
|
|
|
|
2013-11-21 06:49:00 -06:00
|
|
|
// flag if used after blocking assignment (in same proc)
|
|
|
|
if ((proc_flags[mem] & AstNode::MEM2REG_FL_EQ1) && !(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_EQ2)) {
|
2022-08-08 09:13:33 -05:00
|
|
|
mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line));
|
2013-11-21 06:49:00 -06:00
|
|
|
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_EQ2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-05-04 23:11:16 -05:00
|
|
|
// also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg' or 'logic'
|
|
|
|
if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !(is_reg || is_logic)))
|
2013-11-21 06:49:00 -06:00
|
|
|
mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED;
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2023-02-12 17:25:39 -06:00
|
|
|
if ((type == AST_MODULE || type == AST_INTERFACE) && get_bool_attribute(ID::mem2reg))
|
2013-11-21 06:49:00 -06:00
|
|
|
children_flags |= AstNode::MEM2REG_FL_ALL;
|
|
|
|
|
2014-12-28 20:11:50 -06:00
|
|
|
dict<AstNode*, uint32_t> *proc_flags_p = NULL;
|
2013-03-24 05:13:32 -05:00
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
if (type == AST_ALWAYS) {
|
2013-11-21 14:26:56 -06:00
|
|
|
int count_edge_events = 0;
|
|
|
|
for (auto child : children)
|
2013-01-05 04:13:26 -06:00
|
|
|
if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE)
|
2013-11-21 14:26:56 -06:00
|
|
|
count_edge_events++;
|
|
|
|
if (count_edge_events != 1)
|
2013-11-21 06:49:00 -06:00
|
|
|
children_flags |= AstNode::MEM2REG_FL_ASYNC;
|
2014-12-28 20:11:50 -06:00
|
|
|
proc_flags_p = new dict<AstNode*, uint32_t>;
|
2013-11-21 06:49:00 -06:00
|
|
|
}
|
2023-01-17 05:58:08 -06:00
|
|
|
else if (type == AST_INITIAL) {
|
2013-11-21 06:49:00 -06:00
|
|
|
children_flags |= AstNode::MEM2REG_FL_INIT;
|
2014-12-28 20:11:50 -06:00
|
|
|
proc_flags_p = new dict<AstNode*, uint32_t>;
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
2013-11-21 06:49:00 -06:00
|
|
|
uint32_t backup_flags = flags;
|
|
|
|
flags |= children_flags;
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert((flags & ~0x000000ff) == 0);
|
2013-11-21 06:49:00 -06:00
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
for (auto child : children)
|
2019-03-12 14:12:02 -05:00
|
|
|
{
|
|
|
|
if (lhs_children_counter > 0) {
|
|
|
|
lhs_children_counter--;
|
|
|
|
if (child->children.size() && child->children[0]->type == AST_RANGE && child->children[0]->children.size()) {
|
|
|
|
for (auto c : child->children[0]->children) {
|
|
|
|
if (proc_flags_p)
|
|
|
|
c->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, *proc_flags_p, flags);
|
|
|
|
else
|
|
|
|
c->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, proc_flags, flags);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
if (proc_flags_p)
|
2013-11-21 06:49:00 -06:00
|
|
|
child->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, *proc_flags_p, flags);
|
|
|
|
else
|
|
|
|
child->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, proc_flags, flags);
|
2019-03-12 14:12:02 -05:00
|
|
|
}
|
2013-11-21 06:49:00 -06:00
|
|
|
|
|
|
|
flags &= ~children_flags | backup_flags;
|
|
|
|
|
|
|
|
if (proc_flags_p) {
|
2015-01-24 05:16:46 -06:00
|
|
|
#ifndef NDEBUG
|
2013-11-21 06:49:00 -06:00
|
|
|
for (auto it : *proc_flags_p)
|
2014-02-06 15:49:14 -06:00
|
|
|
log_assert((it.second & ~0xff000000) == 0);
|
2015-01-24 05:16:46 -06:00
|
|
|
#endif
|
2013-11-21 06:49:00 -06:00
|
|
|
delete proc_flags_p;
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
2014-12-28 20:11:50 -06:00
|
|
|
bool AstNode::mem2reg_check(pool<AstNode*> &mem2reg_set)
|
2014-10-15 17:44:23 -05:00
|
|
|
{
|
|
|
|
if (type != AST_IDENTIFIER || !id2ast || !mem2reg_set.count(id2ast))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (children.empty() || children[0]->type != AST_RANGE || GetSize(children[0]->children) != 1)
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Invalid array access.\n");
|
2014-10-15 17:44:23 -05:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-05-27 10:25:33 -05:00
|
|
|
void AstNode::mem2reg_remove(pool<AstNode*> &mem2reg_set, vector<AstNode*> &delnodes)
|
|
|
|
{
|
|
|
|
log_assert(mem2reg_set.count(this) == 0);
|
|
|
|
|
|
|
|
if (mem2reg_set.count(id2ast))
|
|
|
|
id2ast = nullptr;
|
|
|
|
|
|
|
|
for (size_t i = 0; i < children.size(); i++) {
|
|
|
|
if (mem2reg_set.count(children[i]) > 0) {
|
|
|
|
delnodes.push_back(children[i]);
|
|
|
|
children.erase(children.begin() + (i--));
|
|
|
|
} else {
|
|
|
|
children[i]->mem2reg_remove(mem2reg_set, delnodes);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
// actually replace memories with registers
|
2016-08-21 06:23:58 -05:00
|
|
|
bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block, AstNode *&async_block)
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
2015-07-29 09:37:08 -05:00
|
|
|
bool did_something = false;
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
if (type == AST_BLOCK)
|
|
|
|
block = this;
|
|
|
|
|
2016-08-21 06:23:58 -05:00
|
|
|
if (type == AST_FUNCTION || type == AST_TASK)
|
|
|
|
return false;
|
|
|
|
|
2019-09-20 05:39:15 -05:00
|
|
|
if (type == AST_TYPEDEF)
|
|
|
|
return false;
|
|
|
|
|
2019-03-02 11:58:20 -06:00
|
|
|
if (type == AST_MEMINIT && id2ast && mem2reg_set.count(id2ast))
|
|
|
|
{
|
|
|
|
log_assert(children[0]->type == AST_CONSTANT);
|
|
|
|
log_assert(children[1]->type == AST_CONSTANT);
|
|
|
|
log_assert(children[2]->type == AST_CONSTANT);
|
2021-05-20 19:27:06 -05:00
|
|
|
log_assert(children[3]->type == AST_CONSTANT);
|
2019-03-02 11:58:20 -06:00
|
|
|
|
|
|
|
int cursor = children[0]->asInt(false);
|
|
|
|
Const data = children[1]->bitsAsConst();
|
2021-05-20 19:27:06 -05:00
|
|
|
Const en = children[2]->bitsAsConst();
|
|
|
|
int length = children[3]->asInt(false);
|
2019-03-02 11:58:20 -06:00
|
|
|
|
|
|
|
if (length != 0)
|
|
|
|
{
|
|
|
|
AstNode *block = new AstNode(AST_INITIAL, new AstNode(AST_BLOCK));
|
|
|
|
mod->children.push_back(block);
|
|
|
|
block = block->children[0];
|
|
|
|
|
|
|
|
int wordsz = GetSize(data) / length;
|
|
|
|
|
|
|
|
for (int i = 0; i < length; i++) {
|
2021-05-20 19:27:06 -05:00
|
|
|
int pos = 0;
|
|
|
|
while (pos < wordsz) {
|
|
|
|
if (en[pos] != State::S1) {
|
|
|
|
pos++;
|
|
|
|
} else {
|
|
|
|
int epos = pos + 1;
|
|
|
|
while (epos < wordsz && en[epos] == State::S1)
|
|
|
|
epos++;
|
|
|
|
int clen = epos - pos;
|
|
|
|
AstNode *range = new AstNode(AST_RANGE, AstNode::mkconst_int(cursor+i, false));
|
|
|
|
if (pos != 0 || epos != wordsz) {
|
|
|
|
int left;
|
|
|
|
int right;
|
|
|
|
AstNode *mrange = id2ast->children[0];
|
|
|
|
if (mrange->range_left < mrange->range_right) {
|
|
|
|
right = mrange->range_right - pos;
|
|
|
|
left = mrange->range_right - epos + 1;
|
|
|
|
} else {
|
|
|
|
right = mrange->range_right + pos;
|
|
|
|
left = mrange->range_right + epos - 1;
|
|
|
|
}
|
|
|
|
range = new AstNode(AST_MULTIRANGE, range, new AstNode(AST_RANGE, AstNode::mkconst_int(left, true), AstNode::mkconst_int(right, true)));
|
|
|
|
}
|
|
|
|
AstNode *target = new AstNode(AST_IDENTIFIER, range);
|
|
|
|
target->str = str;
|
|
|
|
target->id2ast = id2ast;
|
|
|
|
target->was_checked = true;
|
|
|
|
block->children.push_back(new AstNode(AST_ASSIGN_EQ, target, mkconst_bits(data.extract(i*wordsz + pos, clen).bits, false)));
|
|
|
|
pos = epos;
|
|
|
|
}
|
|
|
|
}
|
2019-03-02 11:58:20 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
AstNode *newNode = new AstNode(AST_NONE);
|
|
|
|
newNode->cloneInto(this);
|
|
|
|
delete newNode;
|
|
|
|
|
|
|
|
did_something = true;
|
|
|
|
}
|
|
|
|
|
2016-08-21 06:23:58 -05:00
|
|
|
if (type == AST_ASSIGN && block == NULL && children[0]->mem2reg_check(mem2reg_set))
|
|
|
|
{
|
|
|
|
if (async_block == NULL) {
|
|
|
|
async_block = new AstNode(AST_ALWAYS, new AstNode(AST_BLOCK));
|
|
|
|
mod->children.push_back(async_block);
|
|
|
|
}
|
|
|
|
|
|
|
|
AstNode *newNode = clone();
|
|
|
|
newNode->type = AST_ASSIGN_EQ;
|
2018-09-24 16:32:57 -05:00
|
|
|
newNode->children[0]->was_checked = true;
|
2016-08-21 06:23:58 -05:00
|
|
|
async_block->children[0]->children.push_back(newNode);
|
|
|
|
|
|
|
|
newNode = new AstNode(AST_NONE);
|
|
|
|
newNode->cloneInto(this);
|
|
|
|
delete newNode;
|
|
|
|
|
|
|
|
did_something = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && children[0]->mem2reg_check(mem2reg_set) &&
|
|
|
|
children[0]->children[0]->children[0]->type != AST_CONSTANT)
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
|
|
|
std::stringstream sstr;
|
2022-08-08 09:13:33 -05:00
|
|
|
sstr << "$mem2reg_wr$" << children[0]->str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
|
2013-01-05 04:13:26 -06:00
|
|
|
std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";
|
|
|
|
|
|
|
|
int mem_width, mem_size, addr_bits;
|
2016-11-01 17:17:43 -05:00
|
|
|
bool mem_signed = children[0]->id2ast->is_signed;
|
2013-01-05 04:13:26 -06:00
|
|
|
children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits);
|
|
|
|
|
|
|
|
AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true)));
|
|
|
|
wire_addr->str = id_addr;
|
|
|
|
wire_addr->is_reg = true;
|
2018-06-05 09:44:24 -05:00
|
|
|
wire_addr->was_checked = true;
|
2023-04-05 04:00:07 -05:00
|
|
|
wire_addr->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
|
2013-01-05 04:13:26 -06:00
|
|
|
mod->children.push_back(wire_addr);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (wire_addr->simplify(true, 1, -1, false)) { }
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
|
|
|
|
wire_data->str = id_data;
|
|
|
|
wire_data->is_reg = true;
|
2018-06-05 09:44:24 -05:00
|
|
|
wire_data->was_checked = true;
|
2016-11-01 17:17:43 -05:00
|
|
|
wire_data->is_signed = mem_signed;
|
2023-04-05 04:00:07 -05:00
|
|
|
wire_data->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
|
2013-01-05 04:13:26 -06:00
|
|
|
mod->children.push_back(wire_data);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (wire_data->simplify(true, 1, -1, false)) { }
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(block != NULL);
|
2013-01-05 04:13:26 -06:00
|
|
|
size_t assign_idx = 0;
|
|
|
|
while (assign_idx < block->children.size() && block->children[assign_idx] != this)
|
|
|
|
assign_idx++;
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(assign_idx < block->children.size());
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
AstNode *assign_addr = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), children[0]->children[0]->children[0]->clone());
|
|
|
|
assign_addr->children[0]->str = id_addr;
|
2018-09-24 16:32:57 -05:00
|
|
|
assign_addr->children[0]->was_checked = true;
|
2013-01-05 04:13:26 -06:00
|
|
|
block->children.insert(block->children.begin()+assign_idx+1, assign_addr);
|
|
|
|
|
|
|
|
AstNode *case_node = new AstNode(AST_CASE, new AstNode(AST_IDENTIFIER));
|
|
|
|
case_node->children[0]->str = id_addr;
|
|
|
|
for (int i = 0; i < mem_size; i++) {
|
|
|
|
if (children[0]->children[0]->children[0]->type == AST_CONSTANT && int(children[0]->children[0]->children[0]->integer) != i)
|
|
|
|
continue;
|
|
|
|
AstNode *cond_node = new AstNode(AST_COND, AstNode::mkconst_int(i, false, addr_bits), new AstNode(AST_BLOCK));
|
2013-03-24 04:42:08 -05:00
|
|
|
AstNode *assign_reg = new AstNode(type, new AstNode(AST_IDENTIFIER), new AstNode(AST_IDENTIFIER));
|
2014-07-17 06:49:32 -05:00
|
|
|
if (children[0]->children.size() == 2)
|
|
|
|
assign_reg->children[0]->children.push_back(children[0]->children[1]->clone());
|
2013-01-05 04:13:26 -06:00
|
|
|
assign_reg->children[0]->str = stringf("%s[%d]", children[0]->str.c_str(), i);
|
|
|
|
assign_reg->children[1]->str = id_data;
|
|
|
|
cond_node->children[1]->children.push_back(assign_reg);
|
|
|
|
case_node->children.push_back(cond_node);
|
|
|
|
}
|
2023-04-05 04:00:07 -05:00
|
|
|
|
|
|
|
// fixup on the full hierarchy below case_node
|
|
|
|
case_node->fixup_hierarchy_flags(true);
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
block->children.insert(block->children.begin()+assign_idx+2, case_node);
|
|
|
|
|
|
|
|
children[0]->delete_children();
|
|
|
|
children[0]->range_valid = false;
|
|
|
|
children[0]->id2ast = NULL;
|
|
|
|
children[0]->str = id_data;
|
2013-03-24 04:42:08 -05:00
|
|
|
type = AST_ASSIGN_EQ;
|
2018-09-17 17:23:40 -05:00
|
|
|
children[0]->was_checked = true;
|
2015-07-29 09:37:08 -05:00
|
|
|
|
2023-04-05 04:00:07 -05:00
|
|
|
fixup_hierarchy_flags();
|
2015-07-29 09:37:08 -05:00
|
|
|
did_something = true;
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
2014-10-15 17:44:23 -05:00
|
|
|
if (mem2reg_check(mem2reg_set))
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
2014-07-17 06:49:32 -05:00
|
|
|
AstNode *bit_part_sel = NULL;
|
|
|
|
if (children.size() == 2)
|
|
|
|
bit_part_sel = children[1]->clone();
|
|
|
|
|
2013-11-21 06:49:00 -06:00
|
|
|
if (children[0]->children[0]->type == AST_CONSTANT)
|
|
|
|
{
|
|
|
|
int id = children[0]->children[0]->integer;
|
2021-05-26 17:22:31 -05:00
|
|
|
int left = id2ast->children[1]->children[0]->integer;
|
|
|
|
int right = id2ast->children[1]->children[1]->integer;
|
|
|
|
bool valid_const_access =
|
|
|
|
(left <= id && id <= right) ||
|
|
|
|
(right <= id && id <= left);
|
|
|
|
if (valid_const_access)
|
|
|
|
{
|
|
|
|
str = stringf("%s[%d]", str.c_str(), id);
|
|
|
|
delete_children();
|
|
|
|
range_valid = false;
|
|
|
|
id2ast = NULL;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
int width;
|
|
|
|
if (bit_part_sel)
|
|
|
|
{
|
2024-01-25 00:28:15 -06:00
|
|
|
// bit_part_sel->dumpAst(nullptr, "? ");
|
2021-05-26 17:22:31 -05:00
|
|
|
if (bit_part_sel->children.size() == 1)
|
|
|
|
width = 0;
|
|
|
|
else
|
|
|
|
width = bit_part_sel->children[0]->integer -
|
|
|
|
bit_part_sel->children[1]->integer;
|
|
|
|
delete bit_part_sel;
|
|
|
|
bit_part_sel = nullptr;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
width = id2ast->children[0]->children[0]->integer -
|
|
|
|
id2ast->children[0]->children[1]->integer;
|
|
|
|
}
|
|
|
|
width = abs(width) + 1;
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2021-05-26 17:22:31 -05:00
|
|
|
delete_children();
|
|
|
|
|
|
|
|
std::vector<RTLIL::State> x_bits;
|
|
|
|
for (int i = 0; i < width; i++)
|
|
|
|
x_bits.push_back(RTLIL::State::Sx);
|
|
|
|
AstNode *constant = AstNode::mkconst_bits(x_bits, false);
|
|
|
|
constant->cloneInto(this);
|
|
|
|
delete constant;
|
|
|
|
}
|
2013-11-21 06:49:00 -06:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
std::stringstream sstr;
|
2022-08-08 09:13:33 -05:00
|
|
|
sstr << "$mem2reg_rd$" << str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
|
2013-11-21 06:49:00 -06:00
|
|
|
std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";
|
|
|
|
|
|
|
|
int mem_width, mem_size, addr_bits;
|
2016-11-01 17:17:43 -05:00
|
|
|
bool mem_signed = id2ast->is_signed;
|
2013-11-21 06:49:00 -06:00
|
|
|
id2ast->meminfo(mem_width, mem_size, addr_bits);
|
|
|
|
|
|
|
|
AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true)));
|
|
|
|
wire_addr->str = id_addr;
|
|
|
|
wire_addr->is_reg = true;
|
2018-06-05 09:44:24 -05:00
|
|
|
wire_addr->was_checked = true;
|
2013-11-21 06:49:00 -06:00
|
|
|
if (block)
|
2023-04-05 04:00:07 -05:00
|
|
|
wire_addr->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
|
2013-11-21 06:49:00 -06:00
|
|
|
mod->children.push_back(wire_addr);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (wire_addr->simplify(true, 1, -1, false)) { }
|
2013-11-21 06:49:00 -06:00
|
|
|
|
|
|
|
AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
|
|
|
|
wire_data->str = id_data;
|
|
|
|
wire_data->is_reg = true;
|
2018-06-05 09:44:24 -05:00
|
|
|
wire_data->was_checked = true;
|
2016-11-01 17:17:43 -05:00
|
|
|
wire_data->is_signed = mem_signed;
|
2013-11-21 06:49:00 -06:00
|
|
|
if (block)
|
2023-04-05 04:00:07 -05:00
|
|
|
wire_data->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
|
2013-11-21 06:49:00 -06:00
|
|
|
mod->children.push_back(wire_data);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (wire_data->simplify(true, 1, -1, false)) { }
|
2013-11-21 06:49:00 -06:00
|
|
|
|
|
|
|
AstNode *assign_addr = new AstNode(block ? AST_ASSIGN_EQ : AST_ASSIGN, new AstNode(AST_IDENTIFIER), children[0]->children[0]->clone());
|
|
|
|
assign_addr->children[0]->str = id_addr;
|
2018-06-05 09:44:24 -05:00
|
|
|
assign_addr->children[0]->was_checked = true;
|
2013-11-21 06:49:00 -06:00
|
|
|
|
|
|
|
AstNode *case_node = new AstNode(AST_CASE, new AstNode(AST_IDENTIFIER));
|
|
|
|
case_node->children[0]->str = id_addr;
|
|
|
|
|
|
|
|
for (int i = 0; i < mem_size; i++) {
|
|
|
|
if (children[0]->children[0]->type == AST_CONSTANT && int(children[0]->children[0]->integer) != i)
|
|
|
|
continue;
|
|
|
|
AstNode *cond_node = new AstNode(AST_COND, AstNode::mkconst_int(i, false, addr_bits), new AstNode(AST_BLOCK));
|
|
|
|
AstNode *assign_reg = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), new AstNode(AST_IDENTIFIER));
|
|
|
|
assign_reg->children[0]->str = id_data;
|
2018-06-05 09:44:24 -05:00
|
|
|
assign_reg->children[0]->was_checked = true;
|
2013-11-21 06:49:00 -06:00
|
|
|
assign_reg->children[1]->str = stringf("%s[%d]", str.c_str(), i);
|
|
|
|
cond_node->children[1]->children.push_back(assign_reg);
|
|
|
|
case_node->children.push_back(cond_node);
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2013-11-21 06:49:00 -06:00
|
|
|
std::vector<RTLIL::State> x_bits;
|
|
|
|
for (int i = 0; i < mem_width; i++)
|
|
|
|
x_bits.push_back(RTLIL::State::Sx);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2013-11-21 06:49:00 -06:00
|
|
|
AstNode *cond_node = new AstNode(AST_COND, new AstNode(AST_DEFAULT), new AstNode(AST_BLOCK));
|
|
|
|
AstNode *assign_reg = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), AstNode::mkconst_bits(x_bits, false));
|
2013-01-05 04:13:26 -06:00
|
|
|
assign_reg->children[0]->str = id_data;
|
2018-06-05 09:44:24 -05:00
|
|
|
assign_reg->children[0]->was_checked = true;
|
2013-01-05 04:13:26 -06:00
|
|
|
cond_node->children[1]->children.push_back(assign_reg);
|
|
|
|
case_node->children.push_back(cond_node);
|
2013-03-24 04:42:08 -05:00
|
|
|
|
2023-04-05 04:00:07 -05:00
|
|
|
// fixup on the full hierarchy below case_node
|
|
|
|
case_node->fixup_hierarchy_flags(true);
|
|
|
|
|
2013-11-21 06:49:00 -06:00
|
|
|
if (block)
|
|
|
|
{
|
|
|
|
size_t assign_idx = 0;
|
|
|
|
while (assign_idx < block->children.size() && !block->children[assign_idx]->contains(this))
|
|
|
|
assign_idx++;
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(assign_idx < block->children.size());
|
2013-11-21 06:49:00 -06:00
|
|
|
block->children.insert(block->children.begin()+assign_idx, case_node);
|
|
|
|
block->children.insert(block->children.begin()+assign_idx, assign_addr);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2023-04-05 04:00:07 -05:00
|
|
|
AstNode *proc = new AstNode(AST_ALWAYS, new AstNode(AST_BLOCK, case_node));
|
2013-11-21 06:49:00 -06:00
|
|
|
mod->children.push_back(proc);
|
|
|
|
mod->children.push_back(assign_addr);
|
2023-04-05 04:00:07 -05:00
|
|
|
mod->fixup_hierarchy_flags();
|
2013-11-21 06:49:00 -06:00
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2013-11-21 06:49:00 -06:00
|
|
|
delete_children();
|
|
|
|
range_valid = false;
|
|
|
|
id2ast = NULL;
|
|
|
|
str = id_data;
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
2014-07-17 06:49:32 -05:00
|
|
|
|
2023-04-05 04:00:07 -05:00
|
|
|
if (bit_part_sel) {
|
2014-07-17 06:49:32 -05:00
|
|
|
children.push_back(bit_part_sel);
|
2023-04-05 04:00:07 -05:00
|
|
|
fixup_hierarchy_flags();
|
|
|
|
}
|
2017-01-15 06:52:50 -06:00
|
|
|
|
|
|
|
did_something = true;
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(id2ast == NULL || mem2reg_set.count(id2ast) == 0);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2013-03-24 03:27:01 -05:00
|
|
|
auto children_list = children;
|
2013-03-25 11:13:14 -05:00
|
|
|
for (size_t i = 0; i < children_list.size(); i++)
|
2016-08-21 06:23:58 -05:00
|
|
|
if (children_list[i]->mem2reg_as_needed_pass2(mem2reg_set, mod, block, async_block))
|
2015-07-29 09:37:08 -05:00
|
|
|
did_something = true;
|
|
|
|
|
|
|
|
return did_something;
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
|
2015-08-14 03:56:05 -05:00
|
|
|
// calculate memory dimensions
|
2013-01-05 04:13:26 -06:00
|
|
|
void AstNode::meminfo(int &mem_width, int &mem_size, int &addr_bits)
|
|
|
|
{
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(type == AST_MEMORY);
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
mem_width = children[0]->range_left - children[0]->range_right + 1;
|
|
|
|
mem_size = children[1]->range_left - children[1]->range_right;
|
|
|
|
|
|
|
|
if (mem_size < 0)
|
|
|
|
mem_size *= -1;
|
2015-10-25 13:30:49 -05:00
|
|
|
mem_size += min(children[1]->range_left, children[1]->range_right) + 1;
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
addr_bits = 1;
|
|
|
|
while ((1 << addr_bits) < mem_size)
|
|
|
|
addr_bits++;
|
|
|
|
}
|
|
|
|
|
2020-06-04 16:10:03 -05:00
|
|
|
bool AstNode::detect_latch(const std::string &var)
|
|
|
|
{
|
|
|
|
switch (type)
|
|
|
|
{
|
|
|
|
case AST_ALWAYS:
|
|
|
|
for (auto &c : children)
|
|
|
|
{
|
|
|
|
switch (c->type)
|
|
|
|
{
|
|
|
|
case AST_POSEDGE:
|
|
|
|
case AST_NEGEDGE:
|
|
|
|
return false;
|
2020-07-10 11:41:13 -05:00
|
|
|
case AST_EDGE:
|
|
|
|
break;
|
2020-06-04 16:10:03 -05:00
|
|
|
case AST_BLOCK:
|
|
|
|
if (!c->detect_latch(var))
|
|
|
|
return false;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
log_abort();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
case AST_BLOCK:
|
|
|
|
for (auto &c : children)
|
|
|
|
if (!c->detect_latch(var))
|
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
case AST_CASE:
|
|
|
|
{
|
|
|
|
bool r = true;
|
|
|
|
for (auto &c : children) {
|
|
|
|
if (c->type == AST_COND) {
|
|
|
|
if (c->children.at(1)->detect_latch(var))
|
|
|
|
return true;
|
|
|
|
r = false;
|
|
|
|
}
|
|
|
|
if (c->type == AST_DEFAULT) {
|
|
|
|
if (c->children.at(0)->detect_latch(var))
|
|
|
|
return true;
|
|
|
|
r = false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
case AST_ASSIGN_EQ:
|
|
|
|
case AST_ASSIGN_LE:
|
|
|
|
if (children.at(0)->type == AST_IDENTIFIER &&
|
|
|
|
children.at(0)->children.empty() && children.at(0)->str == var)
|
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-01-27 12:21:13 -06:00
|
|
|
bool AstNode::has_const_only_constructs()
|
2014-06-06 15:55:02 -05:00
|
|
|
{
|
|
|
|
if (type == AST_WHILE || type == AST_REPEAT)
|
|
|
|
return true;
|
|
|
|
for (auto child : children)
|
2021-01-27 12:21:13 -06:00
|
|
|
if (child->has_const_only_constructs())
|
2014-06-06 15:55:02 -05:00
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2019-03-02 14:36:46 -06:00
|
|
|
bool AstNode::is_simple_const_expr()
|
|
|
|
{
|
|
|
|
if (type == AST_IDENTIFIER)
|
|
|
|
return false;
|
|
|
|
for (auto child : children)
|
|
|
|
if (!child->is_simple_const_expr())
|
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2014-02-14 12:56:44 -06:00
|
|
|
// helper function for AstNode::eval_const_function()
|
2021-01-27 12:21:13 -06:00
|
|
|
bool AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &variables, AstNode *fcall, bool must_succeed)
|
2014-02-14 12:56:44 -06:00
|
|
|
{
|
|
|
|
if (type == AST_IDENTIFIER && variables.count(str)) {
|
|
|
|
int offset = variables.at(str).offset, width = variables.at(str).val.bits.size();
|
|
|
|
if (!children.empty()) {
|
2021-01-27 12:21:13 -06:00
|
|
|
if (children.size() != 1 || children.at(0)->type != AST_RANGE) {
|
|
|
|
if (!must_succeed)
|
|
|
|
return false;
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Memory access in constant function is not supported\n%s: ...called from here.\n",
|
2021-02-23 12:22:53 -06:00
|
|
|
fcall->loc_string().c_str());
|
2021-01-27 12:21:13 -06:00
|
|
|
}
|
|
|
|
if (!children.at(0)->replace_variables(variables, fcall, must_succeed))
|
|
|
|
return false;
|
2023-04-04 15:59:44 -05:00
|
|
|
while (simplify(true, 1, -1, false)) { }
|
2021-01-27 12:21:13 -06:00
|
|
|
if (!children.at(0)->range_valid) {
|
|
|
|
if (!must_succeed)
|
|
|
|
return false;
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Non-constant range\n%s: ... called from here.\n",
|
2021-02-23 12:22:53 -06:00
|
|
|
fcall->loc_string().c_str());
|
2021-01-27 12:21:13 -06:00
|
|
|
}
|
2015-10-25 13:30:49 -05:00
|
|
|
offset = min(children.at(0)->range_left, children.at(0)->range_right);
|
|
|
|
width = min(std::abs(children.at(0)->range_left - children.at(0)->range_right) + 1, width);
|
2014-02-14 12:56:44 -06:00
|
|
|
}
|
|
|
|
offset -= variables.at(str).offset;
|
2022-01-12 00:51:08 -06:00
|
|
|
if (variables.at(str).range_swapped)
|
|
|
|
offset = -offset;
|
2014-02-14 12:56:44 -06:00
|
|
|
std::vector<RTLIL::State> &var_bits = variables.at(str).val.bits;
|
|
|
|
std::vector<RTLIL::State> new_bits(var_bits.begin() + offset, var_bits.begin() + offset + width);
|
|
|
|
AstNode *newNode = mkconst_bits(new_bits, variables.at(str).is_signed);
|
|
|
|
newNode->cloneInto(this);
|
|
|
|
delete newNode;
|
2021-01-27 12:21:13 -06:00
|
|
|
return true;
|
2014-02-14 12:56:44 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
for (auto &child : children)
|
2021-01-27 12:21:13 -06:00
|
|
|
if (!child->replace_variables(variables, fcall, must_succeed))
|
|
|
|
return false;
|
|
|
|
return true;
|
2014-02-14 12:56:44 -06:00
|
|
|
}
|
|
|
|
|
2021-01-27 12:21:13 -06:00
|
|
|
// attempt to statically evaluate a functions with all-const arguments
|
|
|
|
AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
|
2014-02-14 12:56:44 -06:00
|
|
|
{
|
2021-01-27 12:21:13 -06:00
|
|
|
std::map<std::string, AstNode*> backup_scope = current_scope;
|
2014-02-14 12:56:44 -06:00
|
|
|
std::map<std::string, AstNode::varinfo_t> variables;
|
2021-03-16 18:14:27 -05:00
|
|
|
std::vector<AstNode*> to_delete;
|
2019-08-06 11:06:14 -05:00
|
|
|
AstNode *block = new AstNode(AST_BLOCK);
|
2021-01-27 12:21:13 -06:00
|
|
|
AstNode *result = nullptr;
|
2014-02-14 12:56:44 -06:00
|
|
|
|
|
|
|
size_t argidx = 0;
|
|
|
|
for (auto child : children)
|
|
|
|
{
|
2014-06-06 14:29:23 -05:00
|
|
|
block->children.push_back(child->clone());
|
2014-02-14 12:56:44 -06:00
|
|
|
}
|
2023-04-05 04:00:07 -05:00
|
|
|
block->set_in_param_flag(true);
|
2014-02-14 12:56:44 -06:00
|
|
|
|
|
|
|
while (!block->children.empty())
|
|
|
|
{
|
|
|
|
AstNode *stmt = block->children.front();
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
log("-----------------------------------\n");
|
|
|
|
for (auto &it : variables)
|
|
|
|
log("%20s %40s\n", it.first.c_str(), log_signal(it.second.val));
|
|
|
|
stmt->dumpAst(NULL, "stmt> ");
|
|
|
|
#endif
|
|
|
|
|
2020-07-25 11:16:12 -05:00
|
|
|
if (stmt->type == AST_WIRE)
|
|
|
|
{
|
2023-04-04 15:59:44 -05:00
|
|
|
while (stmt->simplify(true, 1, -1, false)) { }
|
2021-01-27 12:21:13 -06:00
|
|
|
if (!stmt->range_valid) {
|
|
|
|
if (!must_succeed)
|
|
|
|
goto finished;
|
2023-04-04 04:53:50 -05:00
|
|
|
stmt->input_error("Can't determine size of variable %s\n%s: ... called from here.\n",
|
2021-02-23 12:22:53 -06:00
|
|
|
stmt->str.c_str(), fcall->loc_string().c_str());
|
2021-01-27 12:21:13 -06:00
|
|
|
}
|
2021-02-21 13:45:21 -06:00
|
|
|
AstNode::varinfo_t &variable = variables[stmt->str];
|
|
|
|
int width = abs(stmt->range_left - stmt->range_right) + 1;
|
|
|
|
// if this variable has already been declared as an input, check the
|
|
|
|
// sizes match if it already had an explicit size
|
|
|
|
if (variable.arg && variable.explicitly_sized && variable.val.size() != width) {
|
2023-04-04 04:53:50 -05:00
|
|
|
input_error("Incompatible re-declaration of constant function wire %s.\n", stmt->str.c_str());
|
2021-02-21 13:45:21 -06:00
|
|
|
}
|
|
|
|
variable.val = RTLIL::Const(RTLIL::State::Sx, width);
|
2022-01-12 00:51:08 -06:00
|
|
|
variable.offset = stmt->range_swapped ? stmt->range_left : stmt->range_right;
|
|
|
|
variable.range_swapped = stmt->range_swapped;
|
2021-02-21 13:45:21 -06:00
|
|
|
variable.is_signed = stmt->is_signed;
|
|
|
|
variable.explicitly_sized = stmt->children.size() &&
|
|
|
|
stmt->children.back()->type == AST_RANGE;
|
|
|
|
// identify the argument corresponding to this wire, if applicable
|
2020-08-18 10:27:51 -05:00
|
|
|
if (stmt->is_input && argidx < fcall->children.size()) {
|
2021-02-21 13:45:21 -06:00
|
|
|
variable.arg = fcall->children.at(argidx++);
|
|
|
|
}
|
|
|
|
// load the constant arg's value into this variable
|
|
|
|
if (variable.arg) {
|
|
|
|
if (variable.arg->type == AST_CONSTANT) {
|
|
|
|
variable.val = variable.arg->bitsAsConst(width);
|
2020-08-18 10:27:51 -05:00
|
|
|
} else {
|
2021-02-21 13:45:21 -06:00
|
|
|
log_assert(variable.arg->type == AST_REALVALUE);
|
|
|
|
variable.val = variable.arg->realAsConst(width);
|
2020-08-18 10:27:51 -05:00
|
|
|
}
|
|
|
|
}
|
2020-07-25 11:16:12 -05:00
|
|
|
current_scope[stmt->str] = stmt;
|
|
|
|
|
|
|
|
block->children.erase(block->children.begin());
|
2021-03-16 18:14:27 -05:00
|
|
|
to_delete.push_back(stmt);
|
2020-07-25 11:16:12 -05:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
log_assert(variables.count(str) != 0);
|
|
|
|
|
2020-08-20 19:09:54 -05:00
|
|
|
if (stmt->type == AST_LOCALPARAM)
|
|
|
|
{
|
2023-04-04 15:59:44 -05:00
|
|
|
while (stmt->simplify(true, 1, -1, false)) { }
|
2020-08-20 19:09:54 -05:00
|
|
|
|
|
|
|
current_scope[stmt->str] = stmt;
|
|
|
|
|
|
|
|
block->children.erase(block->children.begin());
|
2021-03-16 18:14:27 -05:00
|
|
|
to_delete.push_back(stmt);
|
2020-08-20 19:09:54 -05:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2014-02-14 12:56:44 -06:00
|
|
|
if (stmt->type == AST_ASSIGN_EQ)
|
|
|
|
{
|
2015-10-01 05:15:35 -05:00
|
|
|
if (stmt->children.at(0)->type == AST_IDENTIFIER && stmt->children.at(0)->children.size() != 0 &&
|
|
|
|
stmt->children.at(0)->children.at(0)->type == AST_RANGE)
|
2021-01-27 12:21:13 -06:00
|
|
|
if (!stmt->children.at(0)->children.at(0)->replace_variables(variables, fcall, must_succeed))
|
|
|
|
goto finished;
|
|
|
|
if (!stmt->children.at(1)->replace_variables(variables, fcall, must_succeed))
|
|
|
|
goto finished;
|
2023-04-04 15:59:44 -05:00
|
|
|
while (stmt->simplify(true, 1, -1, false)) { }
|
2014-02-14 12:56:44 -06:00
|
|
|
|
2014-06-06 10:40:45 -05:00
|
|
|
if (stmt->type != AST_ASSIGN_EQ)
|
|
|
|
continue;
|
|
|
|
|
2021-01-27 12:21:13 -06:00
|
|
|
if (stmt->children.at(1)->type != AST_CONSTANT) {
|
|
|
|
if (!must_succeed)
|
|
|
|
goto finished;
|
2023-04-04 04:53:50 -05:00
|
|
|
stmt->input_error("Non-constant expression in constant function\n%s: ... called from here. X\n",
|
2021-02-23 12:22:53 -06:00
|
|
|
fcall->loc_string().c_str());
|
2021-01-27 12:21:13 -06:00
|
|
|
}
|
2014-02-14 12:56:44 -06:00
|
|
|
|
2021-01-27 12:21:13 -06:00
|
|
|
if (stmt->children.at(0)->type != AST_IDENTIFIER) {
|
|
|
|
if (!must_succeed)
|
|
|
|
goto finished;
|
2023-04-04 04:53:50 -05:00
|
|
|
stmt->input_error("Unsupported composite left hand side in constant function\n%s: ... called from here.\n",
|
2021-02-23 12:22:53 -06:00
|
|
|
fcall->loc_string().c_str());
|
2021-01-27 12:21:13 -06:00
|
|
|
}
|
2014-02-14 12:56:44 -06:00
|
|
|
|
2021-01-27 12:21:13 -06:00
|
|
|
if (!variables.count(stmt->children.at(0)->str)) {
|
|
|
|
if (!must_succeed)
|
|
|
|
goto finished;
|
2023-04-04 04:53:50 -05:00
|
|
|
stmt->input_error("Assignment to non-local variable in constant function\n%s: ... called from here.\n",
|
2021-02-23 12:22:53 -06:00
|
|
|
fcall->loc_string().c_str());
|
2021-01-27 12:21:13 -06:00
|
|
|
}
|
2014-02-14 12:56:44 -06:00
|
|
|
|
2014-06-06 15:55:02 -05:00
|
|
|
if (stmt->children.at(0)->children.empty()) {
|
|
|
|
variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.bits.size());
|
|
|
|
} else {
|
|
|
|
AstNode *range = stmt->children.at(0)->children.at(0);
|
2021-01-27 12:21:13 -06:00
|
|
|
if (!range->range_valid) {
|
|
|
|
if (!must_succeed)
|
|
|
|
goto finished;
|
2023-04-04 04:53:50 -05:00
|
|
|
range->input_error("Non-constant range\n%s: ... called from here.\n", fcall->loc_string().c_str());
|
2021-01-27 12:21:13 -06:00
|
|
|
}
|
2015-10-25 13:30:49 -05:00
|
|
|
int offset = min(range->range_left, range->range_right);
|
2014-07-23 13:45:27 -05:00
|
|
|
int width = std::abs(range->range_left - range->range_right) + 1;
|
2014-06-06 15:55:02 -05:00
|
|
|
varinfo_t &v = variables[stmt->children.at(0)->str];
|
|
|
|
RTLIL::Const r = stmt->children.at(1)->bitsAsConst(v.val.bits.size());
|
2022-01-12 00:51:08 -06:00
|
|
|
for (int i = 0; i < width; i++) {
|
|
|
|
int index = i + offset - v.offset;
|
|
|
|
if (v.range_swapped)
|
|
|
|
index = -index;
|
|
|
|
v.val.bits.at(index) = r.bits.at(i);
|
|
|
|
}
|
2014-06-06 15:55:02 -05:00
|
|
|
}
|
2014-02-14 12:56:44 -06:00
|
|
|
|
2014-02-14 13:33:22 -06:00
|
|
|
delete block->children.front();
|
2014-02-14 12:56:44 -06:00
|
|
|
block->children.erase(block->children.begin());
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2014-02-14 13:33:22 -06:00
|
|
|
if (stmt->type == AST_FOR)
|
|
|
|
{
|
|
|
|
block->children.insert(block->children.begin(), stmt->children.at(0));
|
|
|
|
stmt->children.at(3)->children.push_back(stmt->children.at(2));
|
|
|
|
stmt->children.erase(stmt->children.begin() + 2);
|
|
|
|
stmt->children.erase(stmt->children.begin());
|
|
|
|
stmt->type = AST_WHILE;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (stmt->type == AST_WHILE)
|
|
|
|
{
|
|
|
|
AstNode *cond = stmt->children.at(0)->clone();
|
2021-01-27 12:21:13 -06:00
|
|
|
if (!cond->replace_variables(variables, fcall, must_succeed))
|
|
|
|
goto finished;
|
2023-04-05 04:00:07 -05:00
|
|
|
cond->set_in_param_flag(true);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (cond->simplify(true, 1, -1, false)) { }
|
2014-02-14 13:33:22 -06:00
|
|
|
|
2021-01-27 12:21:13 -06:00
|
|
|
if (cond->type != AST_CONSTANT) {
|
|
|
|
if (!must_succeed)
|
|
|
|
goto finished;
|
2023-04-04 04:53:50 -05:00
|
|
|
stmt->input_error("Non-constant expression in constant function\n%s: ... called from here.\n",
|
2021-02-23 12:22:53 -06:00
|
|
|
fcall->loc_string().c_str());
|
2021-01-27 12:21:13 -06:00
|
|
|
}
|
2014-02-14 13:33:22 -06:00
|
|
|
|
|
|
|
if (cond->asBool()) {
|
|
|
|
block->children.insert(block->children.begin(), stmt->children.at(1)->clone());
|
|
|
|
} else {
|
|
|
|
delete block->children.front();
|
|
|
|
block->children.erase(block->children.begin());
|
|
|
|
}
|
|
|
|
|
|
|
|
delete cond;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2014-06-07 03:47:53 -05:00
|
|
|
if (stmt->type == AST_REPEAT)
|
|
|
|
{
|
|
|
|
AstNode *num = stmt->children.at(0)->clone();
|
2021-01-27 12:21:13 -06:00
|
|
|
if (!num->replace_variables(variables, fcall, must_succeed))
|
|
|
|
goto finished;
|
2023-04-05 04:00:07 -05:00
|
|
|
num->set_in_param_flag(true);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (num->simplify(true, 1, -1, false)) { }
|
2014-06-07 03:47:53 -05:00
|
|
|
|
2021-01-27 12:21:13 -06:00
|
|
|
if (num->type != AST_CONSTANT) {
|
|
|
|
if (!must_succeed)
|
|
|
|
goto finished;
|
2023-04-04 04:53:50 -05:00
|
|
|
stmt->input_error("Non-constant expression in constant function\n%s: ... called from here.\n",
|
2021-02-23 12:22:53 -06:00
|
|
|
fcall->loc_string().c_str());
|
2021-01-27 12:21:13 -06:00
|
|
|
}
|
2014-06-07 03:47:53 -05:00
|
|
|
|
|
|
|
block->children.erase(block->children.begin());
|
|
|
|
for (int i = 0; i < num->bitsAsConst().as_int(); i++)
|
|
|
|
block->children.insert(block->children.begin(), stmt->children.at(1)->clone());
|
|
|
|
|
|
|
|
delete stmt;
|
|
|
|
delete num;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2014-02-16 06:16:38 -06:00
|
|
|
if (stmt->type == AST_CASE)
|
|
|
|
{
|
|
|
|
AstNode *expr = stmt->children.at(0)->clone();
|
2021-01-27 12:21:13 -06:00
|
|
|
if (!expr->replace_variables(variables, fcall, must_succeed))
|
|
|
|
goto finished;
|
2023-04-05 04:00:07 -05:00
|
|
|
expr->set_in_param_flag(true);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (expr->simplify(true, 1, -1, false)) { }
|
2014-02-16 06:16:38 -06:00
|
|
|
|
|
|
|
AstNode *sel_case = NULL;
|
|
|
|
for (size_t i = 1; i < stmt->children.size(); i++)
|
|
|
|
{
|
|
|
|
bool found_match = false;
|
2016-04-21 08:31:54 -05:00
|
|
|
log_assert(stmt->children.at(i)->type == AST_COND || stmt->children.at(i)->type == AST_CONDX || stmt->children.at(i)->type == AST_CONDZ);
|
2014-02-16 06:16:38 -06:00
|
|
|
|
|
|
|
if (stmt->children.at(i)->children.front()->type == AST_DEFAULT) {
|
|
|
|
sel_case = stmt->children.at(i)->children.back();
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (size_t j = 0; j+1 < stmt->children.at(i)->children.size() && !found_match; j++)
|
|
|
|
{
|
|
|
|
AstNode *cond = stmt->children.at(i)->children.at(j)->clone();
|
2021-01-27 12:21:13 -06:00
|
|
|
if (!cond->replace_variables(variables, fcall, must_succeed))
|
|
|
|
goto finished;
|
2014-02-16 06:16:38 -06:00
|
|
|
|
|
|
|
cond = new AstNode(AST_EQ, expr->clone(), cond);
|
2023-04-05 04:00:07 -05:00
|
|
|
cond->set_in_param_flag(true);
|
2023-04-04 15:59:44 -05:00
|
|
|
while (cond->simplify(true, 1, -1, false)) { }
|
2014-02-16 06:16:38 -06:00
|
|
|
|
2021-01-27 12:21:13 -06:00
|
|
|
if (cond->type != AST_CONSTANT) {
|
|
|
|
if (!must_succeed)
|
|
|
|
goto finished;
|
2023-04-04 04:53:50 -05:00
|
|
|
stmt->input_error("Non-constant expression in constant function\n%s: ... called from here.\n",
|
2021-02-23 12:22:53 -06:00
|
|
|
fcall->loc_string().c_str());
|
2021-01-27 12:21:13 -06:00
|
|
|
}
|
2014-02-16 06:16:38 -06:00
|
|
|
|
|
|
|
found_match = cond->asBool();
|
|
|
|
delete cond;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (found_match) {
|
|
|
|
sel_case = stmt->children.at(i)->children.back();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
block->children.erase(block->children.begin());
|
|
|
|
if (sel_case)
|
|
|
|
block->children.insert(block->children.begin(), sel_case->clone());
|
|
|
|
delete stmt;
|
|
|
|
delete expr;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2014-02-14 13:33:22 -06:00
|
|
|
if (stmt->type == AST_BLOCK)
|
|
|
|
{
|
verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-27 12:30:22 -06:00
|
|
|
if (!stmt->str.empty())
|
|
|
|
stmt->expand_genblock(stmt->str + ".");
|
|
|
|
|
2014-02-14 13:33:22 -06:00
|
|
|
block->children.erase(block->children.begin());
|
|
|
|
block->children.insert(block->children.begin(), stmt->children.begin(), stmt->children.end());
|
|
|
|
stmt->children.clear();
|
2023-04-05 04:00:07 -05:00
|
|
|
block->fixup_hierarchy_flags();
|
2014-02-14 13:33:22 -06:00
|
|
|
delete stmt;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2021-01-27 12:21:13 -06:00
|
|
|
if (!must_succeed)
|
|
|
|
goto finished;
|
2023-04-04 04:53:50 -05:00
|
|
|
stmt->input_error("Unsupported language construct in constant function\n%s: ... called from here.\n",
|
2021-02-23 12:22:53 -06:00
|
|
|
fcall->loc_string().c_str());
|
2014-02-14 12:56:44 -06:00
|
|
|
log_abort();
|
|
|
|
}
|
|
|
|
|
2021-01-27 12:21:13 -06:00
|
|
|
result = AstNode::mkconst_bits(variables.at(str).val.bits, variables.at(str).is_signed);
|
2014-06-06 10:40:45 -05:00
|
|
|
|
2021-01-27 12:21:13 -06:00
|
|
|
finished:
|
|
|
|
delete block;
|
|
|
|
current_scope = backup_scope;
|
2014-02-14 12:56:44 -06:00
|
|
|
|
2021-03-16 18:14:27 -05:00
|
|
|
for (auto it : to_delete) {
|
|
|
|
delete it;
|
|
|
|
}
|
|
|
|
to_delete.clear();
|
|
|
|
|
2021-01-27 12:21:13 -06:00
|
|
|
return result;
|
2014-02-14 12:56:44 -06:00
|
|
|
}
|
|
|
|
|
2018-03-09 06:47:11 -06:00
|
|
|
void AstNode::allocateDefaultEnumValues()
|
|
|
|
{
|
|
|
|
log_assert(type==AST_ENUM);
|
2021-06-17 14:59:59 -05:00
|
|
|
log_assert(children.size() > 0);
|
|
|
|
if (children.front()->attributes.count(ID::enum_base_type))
|
|
|
|
return; // already elaborated
|
2018-03-09 06:47:11 -06:00
|
|
|
int last_enum_int = -1;
|
|
|
|
for (auto node : children) {
|
|
|
|
log_assert(node->type==AST_ENUM_ITEM);
|
2023-04-05 04:00:07 -05:00
|
|
|
node->set_attribute(ID::enum_base_type, mkconst_str(str));
|
2018-03-09 06:47:11 -06:00
|
|
|
for (size_t i = 0; i < node->children.size(); i++) {
|
|
|
|
switch (node->children[i]->type) {
|
|
|
|
case AST_NONE:
|
|
|
|
// replace with auto-incremented constant
|
|
|
|
delete node->children[i];
|
|
|
|
node->children[i] = AstNode::mkconst_int(++last_enum_int, true);
|
|
|
|
break;
|
|
|
|
case AST_CONSTANT:
|
|
|
|
// explicit constant (or folded expression)
|
|
|
|
// TODO: can't extend 'x or 'z item
|
|
|
|
last_enum_int = node->children[i]->integer;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
// ignore ranges
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// TODO: range check
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-02-12 13:25:34 -06:00
|
|
|
bool AstNode::is_recursive_function() const
|
|
|
|
{
|
|
|
|
std::set<const AstNode *> visited;
|
|
|
|
std::function<bool(const AstNode *node)> visit = [&](const AstNode *node) {
|
|
|
|
if (visited.count(node))
|
|
|
|
return node == this;
|
|
|
|
visited.insert(node);
|
|
|
|
if (node->type == AST_FCALL) {
|
|
|
|
auto it = current_scope.find(node->str);
|
|
|
|
if (it != current_scope.end() && visit(it->second))
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
for (const AstNode *child : node->children) {
|
|
|
|
if (visit(child))
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
};
|
|
|
|
|
|
|
|
log_assert(type == AST_FUNCTION);
|
|
|
|
return visit(this);
|
|
|
|
}
|
|
|
|
|
|
|
|
std::pair<AstNode*, AstNode*> AstNode::get_tern_choice()
|
|
|
|
{
|
|
|
|
if (!children[0]->isConst())
|
|
|
|
return {};
|
|
|
|
|
|
|
|
bool found_sure_true = false;
|
|
|
|
bool found_maybe_true = false;
|
|
|
|
|
|
|
|
if (children[0]->type == AST_CONSTANT)
|
|
|
|
for (auto &bit : children[0]->bits) {
|
|
|
|
if (bit == RTLIL::State::S1)
|
|
|
|
found_sure_true = true;
|
|
|
|
if (bit > RTLIL::State::S1)
|
|
|
|
found_maybe_true = true;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
found_sure_true = children[0]->asReal(true) != 0;
|
|
|
|
|
|
|
|
AstNode *choice = nullptr, *not_choice = nullptr;
|
|
|
|
if (found_sure_true)
|
|
|
|
choice = children[1], not_choice = children[2];
|
|
|
|
else if (!found_maybe_true)
|
|
|
|
choice = children[2], not_choice = children[1];
|
|
|
|
|
|
|
|
return {choice, not_choice};
|
|
|
|
}
|
|
|
|
|
2021-06-05 15:21:09 -05:00
|
|
|
std::string AstNode::try_pop_module_prefix() const
|
|
|
|
{
|
|
|
|
AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod;
|
|
|
|
size_t pos = str.find('.', 1);
|
|
|
|
if (str[0] == '\\' && pos != std::string::npos) {
|
|
|
|
std::string new_str = "\\" + str.substr(pos + 1);
|
|
|
|
if (current_scope.count(new_str)) {
|
|
|
|
std::string prefix = str.substr(0, pos);
|
|
|
|
auto it = current_scope_ast->attributes.find(ID::hdlname);
|
2024-02-13 14:38:41 -06:00
|
|
|
if ((it != current_scope_ast->attributes.end() && it->second->str == prefix.substr(1))
|
2021-06-05 15:21:09 -05:00
|
|
|
|| prefix == current_scope_ast->str)
|
|
|
|
return new_str;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return str;
|
|
|
|
}
|
|
|
|
|
2014-07-31 06:19:47 -05:00
|
|
|
YOSYS_NAMESPACE_END
|