mirror of https://github.com/YosysHQ/yosys.git
Do not generate "reg assigned in a continuous assignment" warnings for "rand reg"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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parent
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commit
d86ea6badd
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@ -450,8 +450,21 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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children[0]->id2ast->is_reg = true; // if logic type is used in a block asignment
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if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && !children[0]->id2ast->is_reg)
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log_warning("wire '%s' is assigned in a block at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum);
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if (type == AST_ASSIGN && children[0]->id2ast->is_reg)
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log_warning("reg '%s' is assigned in a continuous assignment at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum);
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if (type == AST_ASSIGN && children[0]->id2ast->is_reg) {
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bool is_rand_reg = false;
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if (children[1]->type == AST_FCALL) {
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if (children[1]->str == "\\$anyconst")
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is_rand_reg = true;
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if (children[1]->str == "\\$anyseq")
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is_rand_reg = true;
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if (children[1]->str == "\\$allconst")
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is_rand_reg = true;
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if (children[1]->str == "\\$allseq")
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is_rand_reg = true;
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}
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if (!is_rand_reg)
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log_warning("reg '%s' is assigned in a continuous assignment at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum);
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}
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children[0]->was_checked = true;
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}
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break;
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