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caravel
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98 Commits 140 Branches 61 Tags 15 GiB
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98 Commits

Author SHA1 Message Date
manarabdelaty abc8031729 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-18 15:28:25 +02:00
Tim Edwards 488d8fc5bb Fixed another missing line from the management protect block call 
in caravel.v.
 2021-11-18 08:25:13 -05:00
manarabdelaty b71c8bbb36 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-17 21:09:58 +02:00
Tim Edwards 7b82c143b7 Fixed two signals on the mgmt_protect in caravel that got merged 
and scrambled somehow.
 2021-11-17 14:08:47 -05:00
Tim Edwards 96ef5c83fd Corrected the corner pad connections to vssd and vccd, which were 
still pointing to vssd1/vccd1/vssd2/vccd2, variously in chip_io.v
and chip_io_alt.v
 2021-11-17 11:44:32 -05:00
manarabdelaty 3cc88cd7fd Add USE POWER/USE GROUND properties to the simple_port lef view 2021-11-17 17:57:23 +02:00
manarabdelaty 979d34b7a9 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-17 16:43:59 +02:00
manarabdelaty 1f55f46596 [DATA] Add chip_io views with the fixed clamped3 pad 2021-11-17 16:42:36 +02:00
Tim Edwards 5f1a0029f5 Made the same corrections to caravan as were made to caravel 
(clock -> clock_core in caravel_clocking, VPWR -> vccd_core and
VGND -> vssd_core in the instances of modules that were pulled from
the management SoC to the top level).
 2021-11-17 09:06:42 -05:00
manarabdelaty b5fe87304a [RTL] Fix power connection to HK/digital_pll/caravel clocking, also fix resetb connection 2021-11-17 13:17:23 +02:00
manarabdelaty 1b300d7b59 [DATA] Add digital user project wrapper 2021-11-17 13:13:11 +02:00
manarabdelaty d7ae2e1ac1 [RTL] Move inverter from top level to HK 
- fixed clock connection to the digital_pll and caravel_clocking
- renamed power pins of the HK/caravel_clocking to VPWR/VGND
 2021-11-16 13:59:17 +02:00
Tim Edwards bb1c9fe528 Removed two references for single-macro verilog files that are no 
longer in the PDK but have been folded into larger library files.
With the most recent push to open_pdks to fix an error in the I/O
verilog library, the verilog testbenches once again pass.
 2021-11-15 17:53:48 -05:00
Tim Edwards 559675d392 Corrected chip_io and chip_io_alt layouts to restore the accidentally 
deleted "resetb_core_h" port label.  Corrected the chip_io and chip_io_alt
verilog RTL files to replace the user area power supply clamp cells with
the new clamped3 cell from open_pdks.
 2021-11-15 17:13:43 -05:00
Tim Edwards f18a219be4 Modified the set_user_id script so that if it happens to be run on 
a repository where the user_id_programming GDS has been compressed,
it will handle it correctly.
 2021-11-15 16:41:04 -05:00
manarabdelaty 098b4befb2 Add gds view for chip_io 2021-11-15 23:02:01 +02:00
manarabdelaty a5dbe91965 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-15 21:19:43 +02:00
Tim Edwards f28950695d Made adjustments to the padframe routing to move all routes closer 
to the padframe and free up more space for routing in the chip
interior.
 2021-11-15 11:52:08 -05:00
manarabdelaty 46540437af [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
manarabdelaty 10cf11fbf5 Add gds/lef views for simple_por 2021-11-15 18:08:22 +02:00
manarabdelaty 6203460f57 [DATA] Add views for xres_buf 2021-11-15 18:07:02 +02:00
Tim Edwards aefa72281c Added the files for the simple_por block design, and placed the latest 
hardened macro components into the caravel and caravan layouts.
 2021-11-15 10:34:52 -05:00
manarabdelaty 72b2c724c9 [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
manarabdelaty 4c9f7630ff Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-15 13:24:42 +02:00
manarabdelaty 56f672bbd8 [DATA] Add HK views 2021-11-15 13:23:54 +02:00
manarabdelaty 85a1ffc5aa [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
Tim Edwards 67e48e53c5 Corrected minor DRC errors around the padframe cell and in the new 
caravan logo layout.  Current design is DRC clean with the new
open_pdks maglef views of the I/O cells.
 2021-11-12 16:12:12 -05:00
Tim Edwards 46dd9493f6 Removed some vestiges of top-level routing that were left over 
from the previous version of the caravel and caravan layouts.
 2021-11-12 13:45:58 -05:00
Tim Edwards d5ef31e391 Added an empty management core wrapper to the caravel top level. 2021-11-12 12:17:52 -05:00
manarabdelaty 856539ca59 Update storage testbench to work with one 2K block 2021-11-12 17:14:21 +02:00
Tim Edwards 112ed53751 Modified the Makefile so that "make lvs-gds-" works better (maybe 
not perfectly) when run on chip-io or anything with a pad cell.
 2021-11-11 08:48:14 -05:00
Tim Edwards 27fdba364b Added user 1.8V power supply rails to the chip_io and chip_io_alt 
layouts.  Because the 1.8V domains are no longer within the pad
ring buses, they need to be connected together in the cell.  These
internal lines were previously in the power routing cells.
 2021-11-10 17:13:43 -05:00
Tim Edwards 7820f7a969 Updated the floorplan. 2021-11-10 12:21:22 -05:00
Tim Edwards 38dbd8d5d9 Added logo graphic for Caravan. 2021-11-09 22:47:31 -05:00
Tim Edwards 8da7d5124b Added a logo for Caravel. 2021-11-09 17:18:20 -05:00
manarabdelaty 89bb33fbc0 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-08 13:35:16 +02:00
manarabdelaty bee7b4ed78 Add initial config for the digital_pll 2021-11-08 13:34:59 +02:00
Tim Edwards 4a27ea4c6b Finished first draft of the gen_gpio_defaults.py script, which now 
makes backup copies of caravel and caravan layouts and replaces the
cell name of any gpio defaults block that is changed from the
contents of user_defines.v.  NOTE:  user_defines.v ultimately must
reside in the user project.  The Makefile should copy the user's
version into the caravel directory space before running the script,
or else the script should be rewritten to reference the user's
project area when reading user_defines.v.
 2021-11-07 21:51:00 -05:00
Tim Edwards 27e0c94997 Added caravan top level and seeded with the GPIO control blocks, 
default blocks, and updated copyright.
 2021-11-06 22:34:49 -04:00
Tim Edwards cd906cbf8a Updated the copyright block for the new designs. Added caravel 
layout and placed the GPIO control blocks and default blocks.
 2021-11-06 22:13:19 -04:00
Tim Edwards 6a93ea582d Added a script which parses the file "user_defines.v" in 
verilog/rtl/, and creates all the layout files needed to represent
all unique combinations of defaults used in the file.  Not done:
Modifying the top level layout to use the correct defaults (because
the top level layout does not yet exist).
 2021-11-06 21:19:42 -04:00
Tim Edwards f53590d4b5 Split the layout of the GPIO defaults block into three versions, for the 
three parameterized values used in the RTL verilog.  Modified the
"user_defines.v" file to create verilog definitions that match the C-style
definitions from "defs.h", for convenience/simplicity.
 2021-11-06 13:28:26 -04:00
Tim Edwards 33140b67a5 Edited the gpio_defaults_block layout like the user_id_programming 
cell to have landing sites for vias on both the HI and LO pins of
each conb_1 cell, in preparation for via programming.
 2021-11-06 12:59:49 -04:00
manarabdelaty 59076d499a Update gpio_defaults_block to align the pins with the gpio_control_block 2021-11-05 23:27:32 +02:00
manarabdelaty 49c506f052 Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency 2021-11-05 18:36:43 +02:00
manarabdelaty e68664101c Update gpio_control_block 2021-11-05 16:54:55 +02:00
manarabdelaty 53b09f43d1 Add gpio_defaults_block views 2021-11-05 12:33:36 +02:00
manarabdelaty 78ce7265c1 Update gpio_control block 2021-11-04 17:58:58 +02:00
manarabdelaty cb9990f97e harden gpio_control_block 2021-11-04 16:19:12 +02:00
manarabdelaty 8b055a380c Add top level makefile 2021-11-04 16:16:39 +02:00