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caravel
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195 Commits

Author SHA1 Message Date
M0stafaRady 8e21a2f722 Add test pll 2022-10-05 13:58:36 -07:00
M0stafaRady b31efbdeea IO[0] affects the uart selecting btw system and debug 2022-10-05 13:47:23 -07:00
M0stafaRady fca511f306 change docker mount from the home to repo directory and pdk root 2022-10-05 11:10:24 -07:00
M0stafaRady a741ec4525 Merge branch 'caravel_redesign' into cocotb 2022-10-05 08:24:30 -07:00
M0stafaRady 4610f6b004 Add trial of test gpio_all_i_pu still not work 2022-10-05 08:22:51 -07:00
M0stafaRady 650483eaa2 fix some typos on mgmt_protect 2022-10-05 03:27:46 -07:00
M0stafaRady 4b762da8e6 merge with caravel_redesign 2022-10-04 10:57:56 -07:00
M0stafaRady e2b345dcbb Add new test user_pass_thru_rd 2022-10-04 10:55:53 -07:00
M0stafaRady 0bd6c73b7b update verify_cocotb script to merge coverage 2022-10-04 10:47:07 -07:00
M0stafaRady 5e523bce5b Add spi master temp created to simulate the silicon validation test and to be removed after 2022-10-04 10:46:34 -07:00
Mohamed Shalan 599ee23610
Merge pull request #137 from efabless/fix_caravan_gpio_default 
Changed gpio_defaults_block_14 to gpio_defaults_block_25
 2022-10-04 19:03:46 +02:00
Mohamed Shalan df08268f8a
Merge pull request #142 from efabless/remove_mgmt_protect_tristates 
Remove mgmt protect tristates
 2022-10-04 12:55:34 +02:00
M0stafaRady 11330823b7 Add hk_regs_wr_wb_cpu test 2022-10-04 03:24:15 -07:00
Tim Edwards de9605a01b Modified the mgmt_protect module to change the tristate outputs to 
zero level outputs when the user project area is powered down.
That allows the synthesis tools to buffer these outputs.  The
protection from floating inputs is left as-is, but all logic that
was unnecessary to be specified by gate instances has been changed
to RTL.  This leaves only a handful of signals (logic analyzer input,
user IRQ, and wishbone data out and acknowledge out) to be handled
by explicit logic gate instances.
 2022-10-03 16:11:02 -04:00
M0stafaRady ef9c2e408b fix bug at IRQ_uart 2022-10-03 09:49:51 -07:00
M0stafaRady 37244a2514 add 3 regressions r_rtl , r_gl,r_sdf 2022-10-03 09:01:08 -07:00
M0stafaRady c4859c8789 fix bug at reading from debug registers 2022-10-03 08:57:23 -07:00
M0stafaRady e81416bb51 add new test mgmt_gpio_bidir 2022-10-03 08:56:46 -07:00
M0stafaRady e945c3b882 fix bug at mgmt_gpio_out by increasing the number of phases 2022-10-03 05:45:55 -07:00
M0stafaRady 79f26f6b38 add new test spi_master_rd 2022-10-03 05:36:36 -07:00
M0stafaRady 55f6f56921 update verify_cocotb script to run iverilog inside a docker 2022-10-03 01:56:08 -07:00
M0stafaRady de2f4a3707 Add bitbang_spi_i test 2022-10-02 08:38:00 -07:00
M0stafaRady e661740208 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-02 06:55:52 -07:00
M0stafaRady f3792b8421 merge with caravel_redesign 2022-10-02 06:55:41 -07:00
M0stafaRady 9812aedaa1
Update README.md 2022-10-02 15:50:18 +02:00
M0stafaRady f0494ef4b1 update make file to take user_project_wrapper file as input for iverilog 2022-10-02 06:48:29 -07:00
M0stafaRady 927c216a6b Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-02 06:38:32 -07:00
M0stafaRady 752d12928b fix iverlog command for the new structure 2022-10-02 06:38:22 -07:00
M0stafaRady d8a4b812e8 update script to make hex_files directory if not exists and to take argument -vcs if it will work in vcs mode 2022-10-02 06:37:12 -07:00
M0stafaRady 00a029fec3
Update README.md 2022-10-02 15:17:21 +02:00
M0stafaRady bf9b363f68
Update README.md 2022-10-02 15:01:15 +02:00
M0stafaRady 32607cc118 delete uart_rx hex 2022-10-02 05:40:44 -07:00
M0stafaRady b045977af0 merge with remote branch 2022-10-02 05:39:23 -07:00
M0stafaRady cb929cb329 Fix housekeeping spi tests 2022-10-02 05:37:27 -07:00
M0stafaRady bc9eb2eb31
Update README.md 2022-10-02 14:35:49 +02:00
M0stafaRady 928fc6a2a5
Update README.md 2022-10-02 14:27:42 +02:00
M0stafaRady a0da0fc906
add photo of cocotb structure 2022-10-02 14:10:17 +02:00
M0stafaRady ad053568e7
Create README.md 
add READme in doc file
 2022-10-02 14:09:49 +02:00
M0stafaRady bd712f64d4 rename cocotb.py to verify_cocotb.py 2022-10-02 04:29:48 -07:00
M0stafaRady b5fb97e5f4 rename run.py to cocotb.py 2022-10-02 04:22:44 -07:00
M0stafaRady 9e0be5473d remove hex files from directory 2022-10-02 04:20:32 -07:00
M0stafaRady 1c48f527b8 add bitbang_spi_o tests 2022-10-01 12:39:54 -07:00
M0stafaRady 199d5c0f5c fix bug assert csb before reset for the GL sim to work 2022-10-01 12:36:02 -07:00
M0stafaRady 53e868abdf add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
M0stafaRady d12fac2ad1 update run script to delete vcs files before test run 2022-10-01 12:28:52 -07:00
M0stafaRady 555488c832 fix timeout values to the passing number of cycles required + 10% 2022-10-01 04:11:46 -07:00
M0stafaRady 9615629a42 fix bug bit time calculation 2022-10-01 02:53:24 -07:00
M0stafaRady 68c88b116a increase the clock period to 25ns 2022-10-01 02:52:30 -07:00
M0stafaRady 18b4f36525 add test uart_rx 2022-10-01 02:23:47 -07:00
M0stafaRady 407b0be306 Update script to return fatal error when hex generation fails 2022-10-01 01:48:55 -07:00