which had not been correctly annotated for ports and so were
marked only as plain labels, causing issues when using the cell
as a macro inside mgmt_protect.
+ add custom interactive script to insert a buffer on user_clk output
and have a large buffer on core_clk
~ change pdn config to match top level
~ change sdc
~ change openlane configuration
~ reimplement based on updated views of the macros
~ change interactive script to call label_macro_pins
~ extract all spef and sdf corners using timing-scripts repo
!important same work arounds as before
- reimplement using a sparecell
- reimplement using newest open_pdks
!important using openlane pre odb with some local patches which
most if not all are merged in the current head of openlane however
still takes effort to update the interactive script to be latest
openlane compatible
!important override abstract lef generated by openlane. openlane
generates lef and mag that contain def BLOCKAGE layers that cause
congestions during top level routing
~ update the following views:
def
mag
verilog
spef(all corners)
+ add the ability to override the interactive script filename
+ add the ability to run openlane regression using regression.config
file
~ change GRT ADJUSTMENT values
~ change pointers to some files for workarounds
!important the interactive script still needs updates
!important this was done using old openlane v0.22 and its matching
pdk
!important known workarounds:
- a custom techlef is used where large metal spacing rules are the
only ones present to avoid violations by the router
- some odd behaviour happening when a macro has a lef view
with a non zero origin. so the power routing cell is (temporarily)
modified to have a zero origin and its placement has been shifted
which doesn't match the power routing mag.
- the old openlane doesn't generate multi spef corners. they
are generated using timing-scripts repo
view of constant_block which was recently merged into the repository.
The constant_block instance positions and connections were modified
slightly to avoid routing over obstruction areas.
fork of caravel (layout .mag file not copied into this commit).
The layouts of both chip_io and chip_io_alt are believed to be
complete, but need verification (with LVS).
includes RTL change inside the padframe definition to remove one
previously unnoticed hard-wired connection between VDDIO and a
3.3V domain digital input pin.
- rtl updated
~ add one column to the right to pass placement congestion
~ density adjusted (probably has no effect)
+ manually add isosubstrate layer in mag and gds from older iterations
!important still need to run dynamic simulations
!important depends on some updates to openlane
!important need to be able to recreate using newer openlane versions
kareem
Marwan Abbas
mo-hosni
passant5
Tim Edwards
Mohamed Shalan
marwaneltoukhy
Mohamed Hosni