manarabdelaty
72b2c724c9
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 15:50:43 +02:00
manarabdelaty
4c9f7630ff
Merge branch 'main' of https://github.com/efabless/caravel_openframe into main
2021-11-15 13:24:42 +02:00
manarabdelaty
56f672bbd8
[DATA] Add HK views
2021-11-15 13:23:54 +02:00
manarabdelaty
85a1ffc5aa
[DATA] Add views for the mgmt_protect
2021-11-15 13:21:52 +02:00
Tim Edwards
67e48e53c5
Corrected minor DRC errors around the padframe cell and in the new
...
caravan logo layout. Current design is DRC clean with the new
open_pdks maglef views of the I/O cells.
2021-11-12 16:12:12 -05:00
Tim Edwards
46dd9493f6
Removed some vestiges of top-level routing that were left over
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from the previous version of the caravel and caravan layouts.
2021-11-12 13:45:58 -05:00
Tim Edwards
d5ef31e391
Added an empty management core wrapper to the caravel top level.
2021-11-12 12:17:52 -05:00
Tim Edwards
27fdba364b
Added user 1.8V power supply rails to the chip_io and chip_io_alt
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layouts. Because the 1.8V domains are no longer within the pad
ring buses, they need to be connected together in the cell. These
internal lines were previously in the power routing cells.
2021-11-10 17:13:43 -05:00
Tim Edwards
38dbd8d5d9
Added logo graphic for Caravan.
2021-11-09 22:47:31 -05:00
Tim Edwards
8da7d5124b
Added a logo for Caravel.
2021-11-09 17:18:20 -05:00
manarabdelaty
89bb33fbc0
Merge branch 'main' of https://github.com/efabless/caravel_openframe into main
2021-11-08 13:35:16 +02:00
manarabdelaty
bee7b4ed78
Add initial config for the digital_pll
2021-11-08 13:34:59 +02:00
Tim Edwards
27e0c94997
Added caravan top level and seeded with the GPIO control blocks,
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default blocks, and updated copyright.
2021-11-06 22:34:49 -04:00
Tim Edwards
cd906cbf8a
Updated the copyright block for the new designs. Added caravel
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layout and placed the GPIO control blocks and default blocks.
2021-11-06 22:13:19 -04:00
Tim Edwards
6a93ea582d
Added a script which parses the file "user_defines.v" in
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verilog/rtl/, and creates all the layout files needed to represent
all unique combinations of defaults used in the file. Not done:
Modifying the top level layout to use the correct defaults (because
the top level layout does not yet exist).
2021-11-06 21:19:42 -04:00
Tim Edwards
f53590d4b5
Split the layout of the GPIO defaults block into three versions, for the
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three parameterized values used in the RTL verilog. Modified the
"user_defines.v" file to create verilog definitions that match the C-style
definitions from "defs.h", for convenience/simplicity.
2021-11-06 13:28:26 -04:00
Tim Edwards
33140b67a5
Edited the gpio_defaults_block layout like the user_id_programming
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cell to have landing sites for vias on both the HI and LO pins of
each conb_1 cell, in preparation for via programming.
2021-11-06 12:59:49 -04:00
manarabdelaty
59076d499a
Update gpio_defaults_block to align the pins with the gpio_control_block
2021-11-05 23:27:32 +02:00
manarabdelaty
49c506f052
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 18:36:43 +02:00
manarabdelaty
e68664101c
Update gpio_control_block
2021-11-05 16:54:55 +02:00
manarabdelaty
53b09f43d1
Add gpio_defaults_block views
2021-11-05 12:33:36 +02:00
manarabdelaty
78ce7265c1
Update gpio_control block
2021-11-04 17:58:58 +02:00
manarabdelaty
cb9990f97e
harden gpio_control_block
2021-11-04 16:19:12 +02:00
Tim Edwards
ba932643e6
Changed the chip_io and chip_io_alt layouts to implement the
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continuous ring of vccd and vssd. The clamp connections for the
vccd1/vssd1 and vccd2/vssd2 pads still need to be done, although
the pads themselves have been changed to the base cell, matching
the new verilog RTL.
2021-11-03 15:57:46 -04:00
Tim Edwards
9fb3925649
Updated the OSHW (open source hardware) icon graphic layout, which was
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badly digitized, and not taking advantage of the allowance of 45 degree
angles on metal5.
2021-11-01 17:25:34 -04:00
Tim Edwards
dd66d1e5ca
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
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cell to the simpler (and easier to remember) "xres_buf".
2021-10-31 21:43:09 -04:00
Tim Edwards
3a57940371
Revised the management protect block to include protections against
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an unconnected wishbone bus (unconnected inputs). Added the missing
signals for the user IRQ enables to management protect (which have
to come from the management SoC).
2021-10-27 19:36:43 -04:00
Tim Edwards
a7148378a0
Added as many of the magic database layout files as are expected to remain
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unchanged between the caravel and caravel_openframe repositories.
2021-10-26 10:27:03 -04:00