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caravel
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422 Commits

Author SHA1 Message Date
Marwan Abbas 35ec52aa72
Merge pull request #260 from efabless/fix_top_buffers_again 
More changes to the GPIO buffer cell
 2022-10-17 03:35:25 +02:00
Tim Edwards 9f54b2ecec Added a gate-level version of gpio_signal_buffering derived from 
the RTL, but cleaned up for macro definitions;  this can be used
for LVS.  The decap cells were hand-edited in because there is
no way to devine them from the RTL source.
 2022-10-16 21:20:12 -04:00
Tim Edwards 69d353f65c Corrected the verilog and the layout for the caravan version of the 
signal buffering (verilog was missing one of the buffers, and the
layout had some of the labels at the top accidentally erased).
 2022-10-16 21:06:27 -04:00
Marwan Abbas 37d2a9d463 connected rest of buffers to power 2022-10-17 01:15:46 +02:00
kareem 2409207178 reharden: caravel 
~ add non functional blocks - like caravel_motto
 2022-10-16 15:44:27 -07:00
Marwan Abbas 04a55c695f
Merge pull request #252 from efabless/fix_top_buffers_again 
Adjustments to the top level buffering cells
 2022-10-16 23:38:13 +02:00
kareem 704f19b6c7 reharden: caravel 
~ correct placement for spare_logic_block
~ add changes from buffering macro
 2022-10-16 12:56:41 -07:00
Marwan Abbas 4a7031c479
Merge pull request #258 from efabless/cocotb 
Cocotb tests and script updates
 2022-10-16 19:10:49 +02:00
kareem 2a3493ed65 Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 10:03:54 -07:00
M0stafaRady 0542485ae9 remove file buff_flash_clkrst.nl.v 2022-10-16 09:57:54 -07:00
M0stafaRady 8526aadd4a Revert "remove unpowered netlist" 
This reverts commit dd482cb099.
 2022-10-16 09:56:24 -07:00
Tim Edwards c5e7c67d60 Once again. . . Rewrote the RTL verilog so that only signals 
being buffered pass through the buffer macros.  Removed the
straight-through signals from the layout, and renumbered the
vectors in the buffer cells, which no longer match the numbering
at the top level (unfortunately).
 2022-10-16 12:49:44 -04:00
kareem fc0701003c reharden: caravel 
- based on second iteration of the buffer macro
- change config with updated placement of spare logic macros
and power routing cell
 2022-10-16 06:58:46 -07:00
M0stafaRady 8aaeb5bad8 rearrange testlist to test most number of features as quickly as possible 2022-10-16 05:43:04 -07:00
mo-hosni 22dde425ac add mgmt_protect views and openlane files 2022-10-16 03:14:55 -07:00
M0stafaRady 55671cded1 fix bug at bit bang tests 2022-10-15 18:10:33 -07:00
Passant dd482cb099 remove unpowered netlist 2022-10-15 13:46:21 -07:00
M0stafaRady aac5408dfe initial version of debug test 2022-10-15 11:40:39 -07:00
M0stafaRady fb1259dd56 Fix gpio control block access in gatelevel 2022-10-15 09:30:11 -07:00
kareem 5d5d019ea1 Revert "add buff_flash_clkrst" 
This reverts commit 2675487322.
 2022-10-15 08:47:02 -07:00
mo-hosni 2675487322 add buff_flash_clkrst 2022-10-15 06:38:42 -07:00
M0stafaRady 2794932853 Merge branch 'caravel_redesign' into cocotb 2022-10-15 04:37:47 -07:00
M0stafaRady 4fe8416c85 Add time consumed to the txt file 2022-10-15 04:36:55 -07:00
Marwan Abbas 696eddcc7b
Merge branch 'caravel_redesign' into buff_power_connection 2022-10-15 13:34:21 +02:00
M0stafaRady 14ebfa5259 fix bug in bitbang_no_cpu_all_o testbench 2022-10-15 04:18:05 -07:00
Marwan Abbas 40c7776b57 added power connection to buffer rtl 2022-10-15 12:56:40 +02:00
Marwan Abbas 1559e7c41d
Merge pull request #240 from efabless/cocotb 
Cocotb script updates
 2022-10-15 11:55:41 +02:00
M0stafaRady 2d56c68ef2 fix script to not create directory annotation_logs 2022-10-15 02:54:35 -07:00
Marwan Abbas d025944505
Merge branch 'caravel_redesign' into buff_power_connection 2022-10-15 11:48:51 +02:00
M0stafaRady 9be1caa84d Merge branch 'caravel_redesign' into cocotb 2022-10-15 02:40:55 -07:00
M0stafaRady 83e692e176 Merge branch 'caravel_redesign' into cocotb 2022-10-15 02:28:00 -07:00
Marwan Abbas 316f2dbb58
Merge pull request #238 from mo-hosni/update_mgmt_protect 
Update mgmt protect
 2022-10-15 11:27:59 +02:00
Marwan Abbas 6c19140590 added power connection to buffer top level rtl 2022-10-15 11:27:30 +02:00
M0stafaRady 267dfd0965 Add new regression for gpios gpio_rtl and gpio_gl 2022-10-15 02:26:36 -07:00
M0stafaRady 16f55976a9 fix bug at generating new linker script for memory tests 2022-10-15 02:22:21 -07:00
mo-hosni 3361c8787d Add mgmt_protect views and openlane files 2022-10-15 01:46:22 -07:00
M0stafaRady 5d6af67724 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-14 17:13:23 -07:00
M0stafaRady 422bb26ca0 Optimize and update mem tests - script is generating new linker script for the test to be all to test the whole dff or dff2 memory 2022-10-14 17:12:45 -07:00
M0stafaRady 5e044fc505 Merge branch 'caravel_redesign' into cocotb 2022-10-14 16:18:53 -07:00
M0stafaRady 5f046793e4 update verify cocotb script to delete waves if test passed 2022-10-14 16:18:33 -07:00
passant5 8c0e4f7403
Merge branch 'caravel_redesign' into add_top_level_buffers 2022-10-15 00:28:14 +02:00
Passant 653e7fa561 update top-level rtl to resolve conflict with adding top level buffers between housekeeping and `gpio_control_block` https://github.com/efabless/caravel/pull/213 2022-10-14 15:02:16 -07:00
Passant f499b8b75f update top-level rtl with 7 pass through signals to be buffered inside the SoC 2022-10-14 13:11:42 -07:00
mo-hosni 0e01725608 add housekeeping views 2022-10-14 09:26:34 -07:00
Tim Edwards ac209d2397 Corrected a bunch of typos (different signal names used in the 
same file), errors (buffer output pin name, power supplies not
passed at the top level).  Corrected a major error that prevented
the use of the buffers in simulation, so this was not previously
verified by simulation.  The buffering has now been properly
verified.
 2022-10-14 10:51:29 -04:00
Passant 4609abd7e2 remove unpowered gate level netlist 2022-10-14 02:42:37 -07:00
kareem 6452f14de0 reimplement caravel with latest blocks updates and a buffer macro 2022-10-13 13:34:47 -07:00
Marwan Abbas b8651328f9
Merge branch 'caravel_redesign' into cocotb 2022-10-13 21:14:42 +02:00
marwaneltoukhy b07d91ef7a resolve conflict 2022-10-13 12:11:42 -07:00
Passant c3a2c8650e update caravel top-level rtl to add `buff_flash_clkrst` module 2022-10-13 12:11:22 -07:00
Marwan Abbas f7299933ee
Merge pull request #217 from mo-hosni/buff_flash_clkrst 
Buff flash clkrst
 2022-10-13 20:53:18 +02:00
Marwan Abbas 14856fea6d
Merge pull request #216 from mo-hosni/housekeeping_final_views 
Housekeeping final views
 2022-10-13 20:47:09 +02:00
passant5 acd6aeb0dc
Delete housekeeping.nl.v 2022-10-13 20:35:24 +02:00
Marwan Abbas e72f819020
Merge pull request #210 from mo-hosni/final_views 
mgmt_protect final views
 2022-10-13 20:33:57 +02:00
passant5 dd2c99b3de
Delete mgmt_protect.nl.v 2022-10-13 20:31:42 +02:00
Marwan Abbas 08ac55bed8
Merge pull request #214 from efabless/caravel_clocking-buffering 
Caravel clocking reharden
 2022-10-13 20:13:45 +02:00
passant5 9b009167a4
Delete mgmt_protect.nl.v 2022-10-13 20:09:00 +02:00
kareem d5379ab6f9 fix power pins assignment of clockp buffers again 2022-10-13 11:02:35 -07:00
kareem fdf1f11ece fix power pins assignment of clockp buffers 2022-10-13 11:00:04 -07:00
kareem c922241c3f reharden: caravel_clocking 
+ add custom interactive script to insert a buffer on user_clk output
and have a large buffer on core_clk
~ change pdn config to match top level
~ change sdc
~ change openlane configuration
 2022-10-13 10:54:04 -07:00
mo-hosni 889aa7e308 add buff_flash_clkrst 2022-10-13 10:35:51 -07:00
Tim Edwards f7ec0cd012 Added buffers to the top level, inside a macro called 
gpio_signal_buffering (gpio_signal_buffering_alt in caravan).
Note that this macro requires manual placement and routing, like
the padframe, and the top level will need to route around its own
internal routes.
 2022-10-13 13:29:27 -04:00
mo-hosni 0389423ea6 add housekeeping 2022-10-13 10:15:05 -07:00
mo-hosni 1aaebf5cbb add mgmt_protect 2022-10-13 10:11:45 -07:00
M0stafaRady 1bae9af845 delete trash files 2022-10-13 09:55:18 -07:00
M0stafaRady c538f2923d Remove wrong sys.exit from cocotb script 2022-10-13 08:55:01 -07:00
M0stafaRady a8a3be6a8c Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-13 08:43:56 -07:00
M0stafaRady ae249eb8db update sdf files location 2022-10-13 08:43:50 -07:00
M0stafaRady 1d8eac5f48 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-13 08:18:17 -07:00
M0stafaRady 86f2c04d3e Add mem_dff2 test and update script to change the linker script 2022-10-13 08:18:08 -07:00
M0stafaRady 27e6272987 move primetime sdfs under signoff/caravel/primetime_signoff/ 2022-10-13 07:00:03 -07:00
kareem 59743f4832 change buf16 to clkbuf16 and reimplement 2022-10-13 06:54:55 -07:00
kareem 0eed96f33f reharden: digital_pll 
~ reimplement digital_pll using updated RTL
~ changes in config to generate same PDN
~ change deprecated variables
 2022-10-13 06:21:08 -07:00
kareem bb2d983e03 + add a size 16 buf for clockp signal in digital_pll 2022-10-13 05:57:09 -07:00
M0stafaRady 8991af8ff1 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-13 04:25:18 -07:00
M0stafaRady 5d3766edf7 update script and top level testbench for sdf 2022-10-13 04:25:14 -07:00
M0stafaRady f5e1060c6d Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-13 04:05:38 -07:00
M0stafaRady ceac6defa1 fix some tests for gatelevel 2022-10-13 04:05:12 -07:00
M0stafaRady 95cca2dec0 optimize bitbang tests 2022-10-12 16:06:02 -07:00
M0stafaRady 7e6ec8d394 Merge branch 'caravel_redesign' into cocotb 2022-10-12 14:49:27 -07:00
M0stafaRady dce509ab11 update script and testbench top level to include sdf 2022-10-12 14:41:37 -07:00
kareem 8c95a58e0d ~ regenerate chip_io netlist to fix missing power pins from constant blocks 2022-10-12 11:40:05 -07:00
M0stafaRady ac6284599d Merge branch 'caravel_redesign' into cocotb 2022-10-12 10:42:57 -07:00
M0stafaRady e8870d6a8b fix errors for gate level 2022-10-12 10:29:56 -07:00
kareem 9ccb0ff2ed reharden!: caravel 
~ reimplement based on updated views of the macros
~ change interactive script to call label_macro_pins
~ extract all spef and sdf corners using timing-scripts repo

!important same work arounds as before
 2022-10-12 04:45:08 -07:00
mo-hosni db2cc848b2 Added constant block openlane files and powered gl and modified housekeeping config.tcl 2022-10-12 04:12:27 -07:00
M0stafaRady 471e150167 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-12 03:57:56 -07:00
M0stafaRady d994a2e741 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-12 03:57:33 -07:00
M0stafaRady d464a475e0 update gpio tests to release housekeeping spi csb 2022-10-12 03:57:22 -07:00
M0stafaRady 10618bd41c Merge branch 'caravel_redesign' into cocotb 2022-10-12 02:05:27 -07:00
M0stafaRady 685518477d add folder to store important sessions 2022-10-12 02:03:06 -07:00
mo-hosni 76f8d37496 Rehardened housekeeping to fix Antenna violations. 2022-10-11 16:41:50 -07:00
M0stafaRady 71829abbc5 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-11 14:00:58 -07:00
M0stafaRady 2a5c7b876b fix some timeout and errors due to cpu became slower and sram interface are deleted 2022-10-11 14:00:49 -07:00
M0stafaRady de6d55f3ee trial for increase SPI clock 2022-10-11 13:44:56 -07:00
M0stafaRady bd40646465 Update caravel to force high at gpio3 at the start of test 2022-10-11 08:30:02 -07:00
kareem b0abb4e164 add chip_io gl 
~ update interactive script for chip_io.v for recent openlane
~ update config.tcl for recent openlane
~ add a verilog stub for sky130_fd_io__top_xres4v2 as
the io verilog models are not readable by yosys
 2022-10-11 07:35:13 -07:00
M0stafaRady 9cc8ebf28a update verify_cocotb script to include sdf 2022-10-11 07:30:37 -07:00
M0stafaRady 3fe7f3f38b fix tests timeout 2022-10-11 06:04:16 -07:00
M0stafaRady 327900b526 fix bug of wrapper ack 2022-10-11 06:02:44 -07:00