tangxifan
|
fcd8a3cf4d
|
update doc format
|
2020-07-27 13:59:36 -06:00 |
|
tangxifan
|
a24754611c
|
update documentation about the 'width' syntax of fabric dependent bitstream
|
2020-07-27 13:56:57 -06:00 |
|
Xifan Tang
|
aef1d7ba63
|
bug fix in doc about showing example fabric bitstream
|
2020-07-26 22:50:06 -06:00 |
|
tangxifan
|
872a35fc60
|
update doc to fix format problem; add frame_view to doc
|
2020-07-26 22:39:33 -06:00 |
|
tangxifan
|
1f39540672
|
update documentation about fabric bitstream file formats
|
2020-07-26 21:38:33 -06:00 |
|
tangxifan
|
c3fd817bae
|
update documentation about new XML syntax max width
|
2020-07-24 16:33:01 -06:00 |
|
tangxifan
|
c26c268dcd
|
update documentation on fast configuration support for configuration chain
|
2020-07-15 13:55:32 -06:00 |
|
tangxifan
|
862d71f57a
|
remove obselete vpr7 XML syntax from documentation
|
2020-07-15 11:13:47 -06:00 |
|
tangxifan
|
cb0df2c1c6
|
update doc about technology binding between circuit library and device library
|
2020-07-15 11:05:33 -06:00 |
|
tangxifan
|
65dfc545c1
|
update documentation for fabric key
|
2020-07-07 10:28:29 -06:00 |
|
tangxifan
|
7615db2be6
|
update documentation for the new fabric key rules
|
2020-07-06 16:44:21 -06:00 |
|
tangxifan
|
ece262f544
|
remove debug mode in compilation guidelines as we can use release in default now
|
2020-07-04 19:19:06 -06:00 |
|
tangxifan
|
933801cfa7
|
update documentation about alias support in fabric key
|
2020-06-27 15:04:04 -06:00 |
|
tangxifan
|
db5397fa75
|
update tutorial about architecture to synchronize with latest file organization
|
2020-06-24 10:51:26 -06:00 |
|
tangxifan
|
161d1474c1
|
keep tutorial updated to the latest regression test organization
|
2020-06-24 10:36:08 -06:00 |
|
tangxifan
|
8b8d92d186
|
update documentation for new bitstream file format
|
2020-06-20 18:59:45 -06:00 |
|
tangxifan
|
91b072d7c5
|
documentation update on the bitstream file format to synchronize with the latest codes
|
2020-06-17 11:56:40 -06:00 |
|
tangxifan
|
ba38120093
|
add documentation for fabric key and reorganize command references
|
2020-06-12 16:15:16 -06:00 |
|
tangxifan
|
1a006f2ddb
|
update documentation for separated XML files
|
2020-06-11 19:31:16 -06:00 |
|
tangxifan
|
b9dd47d465
|
update documentation about memory bank configuration protocol
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
c00653961e
|
minor format fix in documentation
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
0931eccbf6
|
update documentation for the fast configuration options
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
fe2ba7d50a
|
update documentation for standalone configuration protocol
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
de07712a3a
|
update documentation about the frame-based configuration protocol
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
1150b903a5
|
add quick start tutorial for architecture modeling
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
339bf87c43
|
add missing file
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
aa77ee9af6
|
add tutorial for full testbench run
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
35536ee594
|
renaming design flows in documentation
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
011ce5cdf6
|
minor fix on the documentation
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
f079c61bd3
|
re organize tutorials
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
dcce782a46
|
update documentation about Verilog testbenches
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
c5a3e44e61
|
Update Verilog fabric netlist documentation
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
cae7fe0fed
|
minor fix on the manual subtree
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
c27d77a418
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
f6895fcc14
|
update documentation for new options of Verilog testbench writer
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
c2a81c76e1
|
update doc for new options
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
f4dd882f0f
|
documentation updated for new command
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
df9cf32b49
|
update documenation for configuration chain writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
a41c8dbcb3
|
change to use default sphinx build version
|
2020-06-11 19:31:06 -06:00 |
|
Xifan Tang
|
24934aff86
|
update documentation on the depth option for fabric hierarchy writer
|
2020-06-11 19:31:04 -06:00 |
|
Xifan Tang
|
752470c2da
|
update documentation on write hierarchy command and options
|
2020-06-11 19:31:04 -06:00 |
|
Xifan Tang
|
ac378febef
|
update doc about time units in SDC generator
|
2020-06-11 19:31:03 -06:00 |
|
Xifan Tang
|
d18e924a89
|
Update documentation on new fpga_sdc option
|
2020-06-11 19:31:03 -06:00 |
|
Xifan Tang
|
ecdbdcb592
|
update documentation on new SDC options
|
2020-06-11 19:31:02 -06:00 |
|
Xifan Tang
|
52adebacfb
|
update doc for file options in openfpga bitstream
|
2020-04-21 14:40:53 -06:00 |
|
Xifan Tang
|
b4542ea34b
|
minor fix on doc about the global and general purpose port
|
2020-04-09 17:10:04 -06:00 |
|
Xifan Tang
|
d99776b260
|
update documentation on the global I/O ports
|
2020-04-08 18:18:53 -06:00 |
|
Xifan Tang
|
b9ade3fcb6
|
documentation update to introduce new features in script mode of OpenFPGA shell
|
2020-04-08 14:13:28 -06:00 |
|
Xifan Tang
|
55e68896d6
|
doc update for the support on std cell MUX2 and examples
|
2020-04-07 12:01:13 -06:00 |
|
Xifan Tang
|
7a4137fdcf
|
doc update for packable XML syntax in VPR
|
2020-04-06 18:37:05 -06:00 |
|
Xifan Tang
|
1a3a748dd2
|
update documentation with the support on spypads and global I/O ports
|
2020-04-05 20:12:28 -06:00 |
|
Xifan Tang
|
6ce0fe4ef2
|
doc update for FPGA-bitstream to better motivate the different types of bitstream
|
2020-04-01 12:57:28 -06:00 |
|
Xifan Tang
|
fd8248d9dd
|
update documentation: the addon syntax on VPR and configuration protocols
|
2020-04-01 12:35:52 -06:00 |
|
tangxifan
|
78964ce71c
|
update documentation on the through channel
|
2020-03-27 11:34:39 -06:00 |
|
Xifan Tang
|
b4221e94bb
|
add documentation on the tileable routing and thru channel support
|
2020-03-25 16:52:42 -06:00 |
|
Xifan Tang
|
cb6afea07c
|
update documentation on a new option in FPGA-SDC to constrain zero-delay paths
|
2020-03-25 16:00:25 -06:00 |
|
Xifan Tang
|
3a74fb7a04
|
update documentation for the new options
|
2020-03-25 15:23:21 -06:00 |
|
Xifan Tang
|
7e3a8e5794
|
typo fixed in fpga-bitstream documentation
|
2020-03-22 16:27:12 -06:00 |
|
Xifan Tang
|
75dfe6a045
|
update documentation for write_gsb_to_xml functionality
|
2020-03-22 16:21:35 -06:00 |
|
tangxifan
|
1d766d2a70
|
minor format fix on documentation
|
2020-03-11 10:22:30 -06:00 |
|
Xifan Tang
|
b941ac8a4a
|
remove deprecated options
|
2020-03-10 20:58:00 -06:00 |
|
Xifan Tang
|
8037d1ad93
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-03-10 20:55:02 -06:00 |
|
Xifan Tang
|
9f743f7f4e
|
add openfpga shell documentation
|
2020-03-10 20:54:42 -06:00 |
|
tangxifan
|
0da6f00af5
|
start reworking the openfpga tool documentation
|
2020-03-10 17:29:35 -06:00 |
|
tangxifan
|
089cc5e86e
|
update documentation on circuit model annotation on VPR architecture
|
2020-03-10 16:51:50 -06:00 |
|
tangxifan
|
7195564455
|
reworked circuit model examples in documentation. Now we are consistent to latest syntax
|
2020-03-10 16:17:20 -06:00 |
|
tangxifan
|
54dfdc0cc1
|
update general documentation on circuit library
|
2020-03-10 12:18:12 -06:00 |
|
tangxifan
|
2a3c5b98a5
|
minor format fix in documentation
|
2020-03-09 21:25:13 -06:00 |
|
Xifan Tang
|
d14fa16905
|
finish documentation update on technology library
|
2020-03-09 21:17:25 -06:00 |
|
Xifan Tang
|
cb7e4a1dfa
|
finish documentation the simulation settings in VPR8 integration
|
2020-03-09 20:03:37 -06:00 |
|
tangxifan
|
751735bf41
|
update documentation in simulation setting syntax
|
2020-03-09 17:40:33 -06:00 |
|
tangxifan
|
3c7fd30e12
|
merged tutorial to online documentation and reworked compilation guidelines
|
2020-03-09 13:58:24 -06:00 |
|
tangxifan
|
af6319a6b0
|
reworked motivation in documentation
|
2020-03-09 11:27:25 -06:00 |
|
tangxifan
|
73da4a1d6e
|
rework motivation for FPGA-Verilog and FPGA-Bitstream in documentation
|
2020-03-09 10:32:03 -06:00 |
|
tangxifan
|
f821e60405
|
clean up deadlinks in doc
|
2020-03-09 10:15:16 -06:00 |
|
tangxifan
|
d61ae5561b
|
start cleanup the documentation for openfpga shell
|
2020-03-09 09:44:19 -06:00 |
|
tangxifan
|
f67981afa8
|
update ducoumentation to explain lib_name XML syntax
|
2020-01-08 14:22:17 -07:00 |
|
tangxifan
|
13f964ea72
|
add bitstream file format introduction
|
2019-12-04 13:41:31 -07:00 |
|
tangxifan
|
40bddd4ed7
|
add FPL'19 paper to documentation reference
|
2019-12-04 12:05:30 -07:00 |
|
tangxifan
|
323c4fdc9a
|
clean up documentation build warnings and add guidelines for port naming
|
2019-12-04 11:59:10 -07:00 |
AurelienUoU
|
36f7624b95
|
Point to point truth table typo fix
|
2019-10-01 13:07:27 -06:00 |
|
AurelienUoU
|
e2867019e1
|
Typo fixing
|
2019-09-30 10:38:02 -06:00 |
|
AurelienUoU
|
74f7a3cfb2
|
Doc fixing
|
2019-09-30 10:29:42 -06:00 |
|
AurelienUoU
|
5ac79f4805
|
Point to point documentation
|
2019-09-30 10:00:46 -06:00 |
Ganesh Gore
|
48ec1eefcd
|
Added fpga_task cmd options in doc [ci skip]
|
2019-09-02 02:45:05 -06:00 |
|
Ganesh Gore
|
241b001282
|
Added openfpga_task doc
|
2019-09-01 22:15:53 -06:00 |
|
Ganesh Gore
|
32d47d6b8b
|
Update document + Travis cache check
|
2019-08-31 16:13:47 -06:00 |
|
Ganesh Gore
|
06c0dbb328
|
Added docuementation for fpga_flow
|
2019-08-31 15:19:34 -06:00 |
|
Ganesh Gore
|
937ebd1b85
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2019-08-25 00:53:18 -06:00 |
|
Ganesh Gore
|
c4180fad6d
|
Added .gitignore to build docs locally
|
2019-08-25 00:49:04 -06:00 |
|
tangxifan
|
42b528be57
|
doc updates
|
2019-08-21 15:11:25 -06:00 |
|
tangxifan
|
9c43b1b753
|
complete refacotriing the inv and buf part in submodules
|
2019-08-21 14:54:05 -06:00 |
|
tangxifan
|
b207050b03
|
minor fix in documentation
|
2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
fc93a4941a
|
update documentation
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
7603850d72
|
complete documentation for new features
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
8a046394f8
|
add documentation for multi-mode configurable block support
|
2019-07-30 16:47:41 -06:00 |
|
Xifan Tang
|
afd78604c9
|
Merge branch 'dev' into documentation: resolved conflicts and add logo files
|
2019-07-17 17:50:11 -04:00 |
|
Xifan Tang
|
e7b40f06b0
|
Add documentation for fracturable LUTs
|
2019-07-17 15:21:07 -04:00 |
|
AurelienUoU
|
1cf4e78502
|
Update documentation and help
|
2019-07-15 21:16:15 -06:00 |
|
AurelienUoU
|
df53f6da2c
|
Updates FPGA-Verilog command lines
|
2019-07-05 13:41:34 -06:00 |