Ganesh Gore
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ec3854a648
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-14 00:14:17 -06:00 |
tangxifan
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f69ce708ca
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rework on the order of top-level functions
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2019-09-13 21:59:52 -06:00 |
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tangxifan
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29e80d157c
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Start developing BitstreamContext
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2019-09-13 21:27:47 -06:00 |
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tangxifan
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e64cfc5852
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start refactoring memory decoders
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2019-09-13 20:58:55 -06:00 |
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tangxifan
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d6fc9c1c71
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Find out the mem circuit is so correlated to the new MUX Verilog. Plug-in later
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2019-09-13 15:36:35 -06:00 |
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tangxifan
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009c0d63b5
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refactored the memory bank. Ready to plug-in the test
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2019-09-13 15:05:31 -06:00 |
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tangxifan
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99c30fa7dd
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keep refactoring the memory Verilog generation
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2019-09-13 14:02:04 -06:00 |
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tangxifan
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56f40cf46c
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light modification on Verilog Mux generation and start refactoring memory Verilog generation
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2019-09-13 12:22:57 -06:00 |
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tangxifan
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d8b9349066
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remove legacy codes
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2019-09-13 11:48:25 -06:00 |
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tangxifan
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b920f0fc38
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refactored user template Verilog generation
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2019-09-13 11:41:54 -06:00 |
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tangxifan
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0e6c88dd52
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delete legacy codes for wire Verilog generation
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2019-09-12 21:06:53 -06:00 |
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tangxifan
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c20e182484
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plugged in the refactored wire Verilog generation
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2019-09-12 20:56:30 -06:00 |
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tangxifan
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2b829238b5
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refactored wire Verilog generation
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2019-09-12 20:49:02 -06:00 |
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tangxifan
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79fa858f36
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remove unused ports for Verilog modules
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2019-09-11 19:39:59 -06:00 |
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tangxifan
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2bed51bf29
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minor bug fix for echo
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2019-09-11 17:41:45 -06:00 |
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tangxifan
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0399319212
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refactored LUT Verilog generation
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2019-09-11 17:04:43 -06:00 |
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tangxifan
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6a5b50facf
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refactored RRAM MUX verilog generation
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2019-09-10 20:45:44 -06:00 |
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tangxifan
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0711aa1bd6
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minor bug fixing
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2019-09-10 16:56:14 -06:00 |
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tangxifan
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82683d49cf
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remove legacy codes of local encoders
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2019-09-10 15:34:20 -06:00 |
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tangxifan
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5f561ef5e3
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pass regression test when plug in refactored local encoders
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2019-09-10 15:26:47 -06:00 |
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tangxifan
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62853c092f
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refactoring local encoders. Ready to plug in
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2019-09-10 15:16:29 -06:00 |
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Ganesh Gore
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d64bb18346
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Separated Modelsim tcl script generation
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2019-09-07 12:36:22 -04:00 |
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tangxifan
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59edd49862
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refactored CMOS MUX buffering
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2019-09-06 16:39:34 -06:00 |
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tangxifan
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bc9d95408e
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bug fixed and refactored intermediate buffer addition
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2019-09-05 16:09:28 -06:00 |
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tangxifan
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e623c19055
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implementing mux Verilog generation. Bugs detected, fixing ongoing
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2019-09-04 23:54:53 -06:00 |
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tangxifan
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fde9c8b4ec
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add frac_lut outputs to mux_graph generation
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2019-09-03 23:19:24 -06:00 |
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tangxifan
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b6bb433edc
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bug fixing for datapath mux size in Verilog generation
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2019-09-03 18:09:21 -06:00 |
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tangxifan
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4d183a3fe4
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start developing mux Verilog module generation
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2019-09-03 16:59:03 -06:00 |
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tangxifan
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a8c803f08f
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try to fix bugs in explicit port mapping
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2019-09-02 16:37:43 -06:00 |
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tangxifan
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d2d750a15c
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debugged rram mux branch Verilog generation
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2019-09-02 16:21:29 -06:00 |
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tangxifan
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395bf4fbdf
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refactored rram mux generation
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2019-09-02 14:30:18 -06:00 |
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tangxifan
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f04565386f
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refactored behavioral mux branch verilog generation
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2019-08-27 18:39:25 -06:00 |
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tangxifan
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ab6f1a5461
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add mux output ids for mux_graph
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2019-08-26 21:21:50 -06:00 |
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tangxifan
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b6617a5adf
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fix bugs in verilog comment lines
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2019-08-25 16:37:46 -06:00 |
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tangxifan
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14db2bf1a9
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minor fixing on comment
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2019-08-25 16:35:49 -06:00 |
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tangxifan
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706b7f3427
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Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-08-25 15:52:04 -06:00 |
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tangxifan
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1cfc117b32
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developed verilog instance writer. refactoring on mux ongoing
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2019-08-25 15:47:57 -06:00 |
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tangxifan
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056c45321b
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plug in module manager
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2019-08-25 15:44:31 -06:00 |
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tangxifan
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8fc258cc93
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develop and plug mux_lib_builder, refactoring the mux submodule generation
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2019-08-25 15:33:37 -06:00 |
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tangxifan
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c43fabb43c
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developed verilog instance writer. refactoring on mux ongoing
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2019-08-25 10:31:45 -06:00 |
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tangxifan
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fe7dfd59c3
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Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-08-24 23:54:37 -06:00 |
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tangxifan
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63f40f48fa
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develop and plug mux_lib_builder, refactoring the mux submodule generation
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2019-08-24 19:23:33 -06:00 |
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tangxifan
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27b619554d
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add stats for verilog modules
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2019-08-23 20:23:42 -06:00 |
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tangxifan
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ad06e9c98c
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plug in module manager
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2019-08-23 20:23:41 -06:00 |
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tangxifan
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39853408dd
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add recursive global port searching for circuit library
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2019-08-23 20:23:41 -06:00 |
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tangxifan
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fcb31e4c24
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add stats for verilog modules
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2019-08-23 18:41:16 -06:00 |
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tangxifan
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8eebca9daa
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plug in module manager
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2019-08-23 17:39:29 -06:00 |
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tangxifan
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37a092e885
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add recursive global port searching for circuit library
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2019-08-23 16:36:30 -06:00 |
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tangxifan
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931b042750
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refactoring module manager
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2019-08-23 12:52:01 -06:00 |
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tangxifan
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732e24767f
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developing module manager
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2019-08-22 23:49:35 -06:00 |