tangxifan
|
dba48fb171
|
[test] reworking adder mapping flow to validate carry chain mapping
|
2023-06-20 16:57:08 -07:00 |
|
tangxifan
|
efc9bf9907
|
[test] added new test case to validate bitstream generation
|
2023-06-19 12:40:37 -07:00 |
|
tangxifan
|
97b089ae3c
|
[test] added new testcases to validate fpga core wrapper
|
2023-06-18 21:01:37 -07:00 |
|
tangxifan
|
1ef8eed589
|
[test] update no time stamp golden outputs
|
2023-06-08 15:38:15 -07:00 |
|
tangxifan
|
31b16ba9d7
|
[test] fixed a few bugs
|
2023-05-27 12:47:57 -07:00 |
|
tangxifan
|
27b8007d1b
|
[test] rework pcf support testcase for mock wrapper
|
2023-05-27 12:45:29 -07:00 |
|
tangxifan
|
b3471f2703
|
[test] swap test name
|
2023-05-27 12:34:10 -07:00 |
|
tangxifan
|
89f184e779
|
[test] fixed a few bugs
|
2023-05-27 12:19:28 -07:00 |
|
tangxifan
|
e1feebc96d
|
[core] fixing bugs on pcf and bgf support for mock efpga wrapper
|
2023-05-26 21:54:08 -07:00 |
|
tangxifan
|
205e9aa67b
|
[test] add a new test case
|
2023-05-26 20:55:52 -07:00 |
|
tangxifan
|
7fbe567d4c
|
[test] add more testcases
|
2023-05-25 20:24:02 -07:00 |
|
tangxifan
|
812553e13d
|
[test] adding more test cases
|
2023-05-25 20:17:23 -07:00 |
|
tangxifan
|
11832ad22c
|
[test] add a new testcase to validate mock wrapper
|
2023-05-25 20:02:10 -07:00 |
|
tangxifan
|
8d02a6e600
|
[test] now testcases are using proper arch
|
2023-05-03 21:47:21 +08:00 |
|
tangxifan
|
df771cb33a
|
[test] add a new testcase for subtile and deploy it to basic regression test
|
2023-05-03 15:41:29 +08:00 |
|
tangxifan
|
f06248a1b0
|
[test] add a new testcase to validate the ccff v2
|
2023-04-24 14:55:22 +08:00 |
|
tangxifan
|
02e964b16f
|
[test] add a new test case for ccffv2
|
2023-04-22 15:41:19 +08:00 |
|
tangxifan
|
fba0a83679
|
[test] debugging 2-clock network
|
2023-04-20 14:44:01 +08:00 |
|
tangxifan
|
02b02d18a5
|
[test] fixed a bug in clock arch
|
2023-04-20 11:35:36 +08:00 |
|
tangxifan
|
b242fd97d6
|
[test] adding new arch and testcase for 2-clock network
|
2023-04-20 11:31:49 +08:00 |
|
tangxifan
|
03cb664049
|
[test] now clock network example script supports multiple clocks
|
2023-04-20 10:56:36 +08:00 |
|
tangxifan
|
7d333b3669
|
[test] add a new test for clock network: validate full testbench is working
|
2023-04-20 10:36:08 +08:00 |
|
tangxifan
|
1f9c1fe7e1
|
[test] clean up clock network task config
|
2023-04-20 10:31:22 +08:00 |
|
tangxifan
|
fd1c4039d3
|
[test] typo
|
2023-03-02 21:37:24 -08:00 |
|
tangxifan
|
02b50e3464
|
[lib] now clock spine requires explicit definition of track type and direction when coordinate is vague
|
2023-03-02 21:33:32 -08:00 |
|
tangxifan
|
b9f7c72a96
|
[test] fixed some bugs in arch
|
2023-03-02 18:16:59 -08:00 |
|
tangxifan
|
780dec6b1b
|
[test] add a new test to validate the programmable clock arch
|
2023-02-28 21:46:57 -08:00 |
Ganesh Gore
|
f7c710e95e
|
renamed yosys_vpr_template fabric_netlist_gen_template
|
2023-02-11 18:33:06 -07:00 |
|
Ganesh Gore
|
b2bdfb7475
|
Strip down task
|
2023-02-11 18:32:06 -07:00 |
|
Ganesh Gore
|
b71a1014e8
|
renamed vpr_blif_template to fabric_verification_template
|
2023-02-11 18:29:21 -07:00 |
|
Ganesh Gore
|
6a48f1eb05
|
Updated demo projects
|
2023-02-11 18:24:20 -07:00 |
|
tangxifan
|
d1e951e52e
|
[test] debugging
|
2023-01-24 17:57:34 -08:00 |
|
tangxifan
|
f964c9ed67
|
[test] debug
|
2023-01-24 15:48:57 -08:00 |
|
tangxifan
|
8174f53796
|
[test] deploy new test to fpga bitstream regression
|
2023-01-24 15:42:01 -08:00 |
|
tangxifan
|
fec84d76d1
|
[arch] adding tech lib;
|
2023-01-24 15:22:34 -08:00 |
|
tangxifan
|
d60d0540da
|
[test] adding a new test case to validate the bitstream overloading for DSP blocks
|
2023-01-24 14:58:52 -08:00 |
|
tangxifan
|
f586229b97
|
[test] enable rst_on_lut benchmark
|
2023-01-18 19:45:41 -08:00 |
|
tangxifan
|
b7a66705e0
|
[test] now use yosys_vpr flow; add rst_on_lut benchmark
|
2023-01-18 19:42:50 -08:00 |
|
tangxifan
|
e974e5ddf7
|
[test] now allow to select vpr device layout for test cases that ignores global nets on regular CLB inputs
|
2023-01-18 18:31:36 -08:00 |
|
tangxifan
|
03273371c0
|
[test] add a new test to validate local reset
|
2023-01-18 18:17:14 -08:00 |
|
tangxifan
|
2c9593c1d4
|
[test] now use a new benchmark: discrete dffn to validate the clk gen locally feature
|
2023-01-15 13:09:40 -08:00 |
|
tangxifan
|
13aed6fff5
|
[test] still commment verification out
|
2023-01-15 12:17:59 -08:00 |
|
tangxifan
|
758cc7a089
|
[test] debugging
|
2023-01-15 11:44:48 -08:00 |
|
tangxifan
|
14bb76ec87
|
[test] remove verification steps for new test but leave a todo
|
2023-01-14 23:06:54 -08:00 |
|
tangxifan
|
9222d085cd
|
[test] now use local clock as one of the pins in a clock bus, but connected to global routing
|
2023-01-13 22:04:56 -08:00 |
|
tangxifan
|
26f71656de
|
[test] update pin constraints
|
2023-01-13 21:12:18 -08:00 |
|
tangxifan
|
93107c752a
|
[test] updating test case
|
2023-01-13 19:53:15 -08:00 |
|
tangxifan
|
1353577351
|
[test] added a new test to validate locally generated clocks
|
2023-01-13 16:45:30 -08:00 |
|
tangxifan
|
c7dc3ce7dc
|
[test] pass
|
2023-01-11 17:10:29 -08:00 |
|
tangxifan
|
f6f153ace4
|
[test] debugging
|
2023-01-11 17:06:31 -08:00 |