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OpenFPGA
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3172 Commits

Author SHA1 Message Date
AurelienUoU 7020d9b4b6 Edit waveform generator + fix clock mapping in autochecked testbench 2018-12-09 15:48:59 -07:00
Baudouin Chauviere afbe5bd3ff need abc_with_bb_support for ace compilation 2018-12-09 15:45:09 -07:00
AurelienUoU 5e94b7093d Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench) 2018-12-08 22:57:54 -07:00
Aur??Lien ALACCHI 10866d1852 Correct verilog syntax error in autocheck testbench 2018-12-08 17:40:23 -07:00
Aur??Lien ALACCHI d716b67e23 Correct syntax error in autocheck testbench 2018-12-08 17:29:56 -07:00
Aur??Lien ALACCHI 0580d8243f Add Autochek testbench option 2018-12-08 17:19:12 -07:00
Baudouin Chauviere b0fcbc0960 remove abc with bb support 2018-12-08 16:40:57 -07:00
Baudouin Chauviere 79930982cf Changed for the naming 2018-12-08 16:19:38 -07:00
Baudouin Chauviere 4440066565 added the script to launch vpr with picorv 2018-12-08 16:01:58 -07:00
Baudouin Chauviere c130404158 add a section for picorv generation through the flow 2018-12-08 11:33:14 -07:00
Aur??Lien ALACCHI 4cc875a5a5 fix a bug in wired LUT 2018-12-06 18:00:17 -07:00
tangxifan b3c1018e28 fixed a bug in wired LUT 2018-12-06 16:50:30 -07:00
Aur??Lien ALACCHI 7795d4e7fd Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA 
unknown merge
 2018-12-06 15:35:22 -07:00
Aur??Lien ALACCHI eebdf7cb10 Add possibility to choose default value for initialization 2018-12-06 15:34:14 -07:00
Baudouin Chauviere 0b6fcc8875 Added the aliases for Yosys-ABC 2018-12-06 15:06:01 -07:00
Baudouin Chauviere 0b1ccf7722 and in the config path as well 2018-12-06 14:57:32 -07:00
Baudouin Chauviere 6a54592a7b removed abc and added yosys in the flow 2018-12-06 14:55:36 -07:00
Baudouin Chauviere b6bb419e1d add a ModelSim option 2018-12-06 14:13:37 -07:00
Baudouin Chauviere fe47b3d21f Changing arch from memory dec to scff. Get the bitstream from go.sh 2018-12-06 14:03:17 -07:00
BaudouinChauviere 88af64c606
Update eda_flow.rst 
Distributions compilable added
 2018-12-05 16:29:07 -07:00
BaudouinChauviere d0ac931daa
Update README.md 
Small correction
 2018-12-05 16:27:37 -07:00
BaudouinChauviere 576feb600f
Update eda_flow.rst 
Completed with FPGA-Verilog/Bitstream and corrected few errors
 2018-12-05 16:24:03 -07:00
Aur??Lien ALACCHI 8281b7346b Edit auto-generated modelsim script 2018-12-05 16:15:29 -07:00
Aur??Lien ALACCHI 44b7f7f3d4 Correct sub_modules.v generation to include decoders.v when necessary 2018-12-05 13:52:25 -07:00
Aur??Lien ALACCHI dc4accedd9 Add forgottent files + add parameter transmission from verilog_api.c 2018-12-05 11:33:14 -07:00
Aur??Lien ALACCHI 9a8c7b391a Add process for modelsim script autogeneration 2018-12-05 09:20:47 -07:00
Aur??Lien ALACCHI 75d64db0f9 Add verilog header sub_module.v file generation 2018-12-04 18:42:47 -07:00
Aur??Lien ALACCHI 8ac566ecc0 Add timing and initialization for simulation 2018-12-04 17:32:09 -07:00
BaudouinChauviere 0f87fb9c3f
Update file_organization.rst 
Correction on the routing
 2018-12-03 14:21:40 -07:00
BaudouinChauviere e541834bd0
Update file_organization.rst 
Made similar to the SPICE one
 2018-12-03 14:20:34 -07:00
BaudouinChauviere cd301a5bb8
Update file_organization.rst 
Correction of the hierarchy
 2018-12-03 14:09:11 -07:00
BaudouinChauviere 9c97125b0d
Update spice_simulation.rst 
typo
 2018-12-03 13:42:45 -07:00
BaudouinChauviere b8f702e16d
Update file_organization.rst 
Creation of the table for better understanding
 2018-12-03 13:40:42 -07:00
BaudouinChauviere 10cbd2efef
Update index.rst 
Commenting the multi mode out until more mature
 2018-12-03 11:50:13 -07:00
BaudouinChauviere 8e7def7f88
Update link_circuit_modules.rst 
Correction of typos
 2018-12-03 11:39:44 -07:00
BaudouinChauviere f8e801b9d1
Merge pull request #1 from LNIS-Projects/Documentation-Update 
Update index.rst
 2018-12-03 11:27:05 -07:00
BaudouinChauviere a4d29aeb1b
Update circuit_model_examples.rst 
Typo correction
 2018-12-03 11:26:04 -07:00
BaudouinChauviere e39e0219e9
Update circuit_modules.rst 
Move the examples from this part to their own
 2018-12-03 10:59:20 -07:00
BaudouinChauviere 7a49ca8ce2
Update index.rst 
New section in the doc
 2018-12-03 10:58:50 -07:00
BaudouinChauviere 99769c1510
Create circuit_model_examples.rst 
Better architecture of the doc
 2018-12-03 10:58:11 -07:00
BaudouinChauviere 47a214520f
Update index.rst 
Skip lines
 2018-12-03 10:32:15 -07:00
BaudouinChauviere 6827549be2
Update index.rst 
Include the links for the external documentation
 2018-12-03 10:31:02 -07:00
tangxifan 70751551b5 fix a bug in wired LUT support 2018-11-30 21:33:31 -07:00
tangxifan 4f5f8de46f Add Yosys and update flow_flow Perl Script 2018-11-30 21:14:43 -07:00
tangxifan e223868df8 fix bugs for wired LUTs 2018-11-27 12:46:30 -07:00
Aur??Lien ALACCHI de2bc18bbb bugs fixed for shift register benchmark 2018-11-26 16:58:45 -07:00
Baudouin Chauviere d55ecd154b Add the PTM to the benchmark flow 2018-11-21 11:32:34 -07:00
Baudouin Chauviere 8ce0a84bc1 Correction of the global make, the fpga_flow and the doc 2018-11-20 14:47:15 -07:00
Baudouin Chauviere 03e902023a Perl script integrated to flow. rm shell one 2018-11-20 13:32:11 -07:00
Baudouin Chauviere 15d69e2bb1 Generation script finished TODO: integration in flow 2018-11-20 13:24:31 -07:00