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Generation script finished TODO: integration in flow

This commit is contained in:
Baudouin Chauviere 2018-11-20 13:24:31 -07:00
parent e74f05a161
commit 15d69e2bb1
4 changed files with 122 additions and 60 deletions
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5
Makefile
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@ -2,7 +2,7 @@
# Makefile to build CAD tools in OpenFPGA inspired by Verilog-to-Routing (VTR) Framework #
##########################################################################################
SUBDIRS = abc_with_bb_support ace2 vpr7_x2p
SUBDIRS = abc abc_with_bb_support ace2 vpr7_x2p
all: notifications subdirs
@ -27,6 +27,7 @@ packages:
@ cd vpr && make packages
clean:
@ cd abc && make clean
@ cd abc_with_bb_support && make clean
@ cd ace2 && make clean
@ cd vpr7_x2p && make clean
@ -35,4 +36,4 @@ clean:
clean_vpr:
@ cd vpr && make clean
.PHONY: packages subdirs $(SUBDIRS)
.PHONY: packages subdirs $(SUBDIRS)

56
fpga_flow/benchmarks/fpga_spice_bench.txt
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@ -1,32 +1,32 @@
# Circuit Names, fixed routing channel width,
# One # worked, ## did not
#s298.blif, 60
#elliptic.blif, 60
#simple_spi.blif, 60
##i2c.blif, 60
#pci_conf_cyc_addr_dec.blif, 60
#sasc.blif, 60
#usb_phy.blif, 60
#steppermotordrive.blif, 60
#stereovision3.blif, 60
#dalu.blif, 60
#C1355.blif, 60
#alu4.blif, 60
#priority.blif, 60
#apex7.blif, 60
#int2float.blif, 60
#planet.blif, 60
#alu2.blif, 60
##mult32a.blif, 60
#tbk.blif, 60
#sqrt8ml.blif, 60
#ss_pcm.blif, 60
#scf.blif, 60
#s820.blif, 60
#ctrl.blif, 60
#cavlc.blif, 60
#router.blif, 60
##traffic.blif, 60
### One # worked, ## did not
s298.blif, 60
elliptic.blif, 60
simple_spi.blif, 60
i2c.blif, 60
pci_conf_cyc_addr_dec.blif, 60
sasc.blif, 60
usb_phy.blif, 60
steppermotordrive.blif, 60
stereovision3.blif, 60
dalu.blif, 60
C1355.blif, 60
alu4.blif, 60
priority.blif, 60
apex7.blif, 60
int2float.blif, 60
planet.blif, 60
alu2.blif, 60
mult32a.blif, 60
tbk.blif, 60
sqrt8ml.blif, 60
ss_pcm.blif, 60
scf.blif, 60
s820.blif, 60
ctrl.blif, 60
cavlc.blif, 60
router.blif, 60
traffic.blif, 60
e64.blif, 60
s1488.blif, 60
fsm8_8_13.blif, 60

33
fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf
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@ -1,27 +1,26 @@
# Standard Configuration Example
[dir_path]
script_base = /home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/fpga_flow/scripts/
benchmark_dir = /home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/fpga_flow/benchmarks/FPGA_SPICE_bench
odin2_path = /home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/fpga_flow/not_used_atm/odin2.exe
cirkit_path = /home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/fpga_flow/not_used_atm/cirkit
abc_path = /home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/fpga_flow/../abc_with_bb_support/abc
abc_mccl_path = /home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/fpga_flow/../abc_with_bb_support/abc
abc_with_bb_support_path = /home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/fpga_flow/../abc_with_bb_support/abc
mpack1_path = /home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/fpga_flow/not_used_atm/mpack1
m2net_path = /home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/fpga_flow/not_used_atm/m2net
mpack2_path = /home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/fpga_flow/not_used_atm/mpack2
vpr_path = /home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/fpga_flow/../vpr7_x2p/vpr/vpr
rpt_dir = /home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/fpga_flow/results
ace_path = /home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/fpga_flow/../ace2/ace
script_base = /research/ece/lnis/USERS/chauviere/OpenFPGA/fpga_flow/scripts/../scripts/
benchmark_dir = /research/ece/lnis/USERS/chauviere/OpenFPGA/fpga_flow/scripts/../benchmarks/FPGA_SPICE_bench
odin2_path = /research/ece/lnis/USERS/chauviere/OpenFPGA/fpga_flow/scripts/../not_used_atm/odin2.exe
cirkit_path = /research/ece/lnis/USERS/chauviere/OpenFPGA/fpga_flow/scripts/../not_used_atm/cirkit
abc_path = /research/ece/lnis/USERS/chauviere/OpenFPGA/fpga_flow/scripts/../../abc_with_bb_support/abc
abc_mccl_path = /research/ece/lnis/USERS/chauviere/OpenFPGA/fpga_flow/scripts/../../abc_with_bb_support/abc
abc_with_bb_support_path = /research/ece/lnis/USERS/chauviere/OpenFPGA/fpga_flow/scripts/../../abc_with_bb_support/abc
mpack1_path = /research/ece/lnis/USERS/chauviere/OpenFPGA/fpga_flow/scripts/../not_used_atm/mpack1
m2net_path = /research/ece/lnis/USERS/chauviere/OpenFPGA/fpga_flow/scripts/../not_used_atm/m2net
mpack2_path = /research/ece/lnis/USERS/chauviere/OpenFPGA/fpga_flow/scripts/../not_used_atm/mpack2
vpr_path = /research/ece/lnis/USERS/chauviere/OpenFPGA/fpga_flow/scripts/../../vpr7_x2p/vpr/vpr
rpt_dir = /research/ece/lnis/USERS/chauviere/OpenFPGA/fpga_flow/scripts/../results
ace_path = /research/ece/lnis/USERS/chauviere/OpenFPGA/fpga_flow/scripts/../../ace2/ace
[flow_conf]
flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr
vpr_arch = /home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml # Use relative path under VPR folder is OK
vpr_arch = /research/ece/lnis/USERS/chauviere/OpenFPGA/fpga_flow/scripts/../arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml # Use relative path under VPR folder is OK
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
m2net_conf = /home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
m2net_conf = /research/ece/lnis/USERS/chauviere/OpenFPGA/fpga_flow/scripts/../m2net_conf/m2x2_SiNWFET.conf
mpack2_arch = K6_pattern7_I24.arch
power_tech_xml = /home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/fpga_flow/tech/tsmc40nm.xml # Use relative path under VPR folder is OK
power_tech_xml = /research/ece/lnis/USERS/chauviere/OpenFPGA/fpga_flow/scripts/../tech/tsmc40nm.xml # Use relative path under VPR folder is OK
[csv_tags]
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:

88
fpga_flow/scripts/generate_config.pl
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@ -1,5 +1,5 @@
#!usr/bin/perl -w
use strict
use strict;
#use Shell;
#Use the time
use Time::gmtime;
@ -7,20 +7,20 @@ use Time::gmtime;
#Get Date
my $mydate = gmctime();
use File::Path;
use Cwd;
my ($FPGA_FLOW_PATH, $DESTINATION);
$FPGA_FLOW_PATH = abs_path();
open($DESTINATION, '>', '../configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf')
use FileHandle;
my $CONF_HANDLE;
my ($SCRIPTS_PATH, $CONFIG_PATH, $FPGA_FLOW_PATH);
$SCRIPTS_PATH = getcwd();
$FPGA_FLOW_PATH = "${SCRIPTS_PATH}/..";
$CONFIG_PATH = "${FPGA_FLOW_PATH}/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf";
sub print_usage()
{
print "This file generates the configuration for the .run_fpga_spice_testbench_study.sh in the parent folder. The output is placed in ../configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf\n"
print $DESTINATION "# Standard Configuration Example\n";
print "\n The configuration file generates the configuration for the .run_fpga_spice_testbench_study.sh in the parent folder. \nThe output is placed in ../configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf\n";
return 1;
}
# Create paths if it does not exist.
@ -35,7 +35,69 @@ sub generate_path($)
return 1;
}
# Opens the file in order to write into it
sub open_file($)
{
my ($mypath) = @_;
open ($CONF_HANDLE, "> $mypath") or die "Can't open $mypath: $!";
return 1;
}
# Generates the content of the configuration file
sub generate_file($)
{
my ($my_path) = @_;
print $CONF_HANDLE "# Standard Configuration Example\n";
print $CONF_HANDLE "[dir_path]\n";
print $CONF_HANDLE "script_base = $FPGA_FLOW_PATH/scripts/\n";
print $CONF_HANDLE "benchmark_dir = ${FPGA_FLOW_PATH}/benchmarks/FPGA_SPICE_bench\n";
print $CONF_HANDLE "odin2_path = ${FPGA_FLOW_PATH}/not_used_atm/odin2.exe\n";
print $CONF_HANDLE "cirkit_path = ${FPGA_FLOW_PATH}/not_used_atm/cirkit\n";
print $CONF_HANDLE "abc_path = ${FPGA_FLOW_PATH}/../abc_with_bb_support/abc\n";
print $CONF_HANDLE "abc_mccl_path = ${FPGA_FLOW_PATH}/../abc_with_bb_support/abc\n";
print $CONF_HANDLE "abc_with_bb_support_path = ${FPGA_FLOW_PATH}/../abc_with_bb_support/abc\n";
print $CONF_HANDLE "mpack1_path = ${FPGA_FLOW_PATH}/not_used_atm/mpack1\n";
print $CONF_HANDLE "m2net_path = ${FPGA_FLOW_PATH}/not_used_atm/m2net\n";
print $CONF_HANDLE "mpack2_path = ${FPGA_FLOW_PATH}/not_used_atm/mpack2\n";
print $CONF_HANDLE "vpr_path = ${FPGA_FLOW_PATH}/../vpr7_x2p/vpr/vpr\n";
print $CONF_HANDLE "rpt_dir = ${FPGA_FLOW_PATH}/results\n";
print $CONF_HANDLE "ace_path = ${FPGA_FLOW_PATH}/../ace2/ace\n";
print $CONF_HANDLE "\n";
print $CONF_HANDLE "[flow_conf]\n";
print $CONF_HANDLE "flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr\n";
print $CONF_HANDLE "vpr_arch = ${FPGA_FLOW_PATH}/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml # Use relative path under VPR folder is OK\n";
print $CONF_HANDLE "mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK\n";
print $CONF_HANDLE "m2net_conf = ${FPGA_FLOW_PATH}/m2net_conf/m2x2_SiNWFET.conf\n";
print $CONF_HANDLE "mpack2_arch = K6_pattern7_I24.arch\n";
print $CONF_HANDLE "power_tech_xml = ${FPGA_FLOW_PATH}/tech/tsmc40nm.xml # Use relative path under VPR folder is OK\n";
print $CONF_HANDLE "\n";
print $CONF_HANDLE "[csv_tags]\n";
print $CONF_HANDLE "mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:\n";
print $CONF_HANDLE "mpack2_tags = BLE Number:|BLE Fill Rate: \n";
print $CONF_HANDLE "vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:\n";
print $CONF_HANDLE "vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff\n";
return 1;
}
# Closes the file after being used
sub close_file($)
{
close ($CONF_HANDLE) || warn "close failed: $!";
return 1;
}
# Main routine
sub main()
{
&print_usage();
&generate_path($CONFIG_PATH);
&open_file($CONFIG_PATH);
&generate_file($CONFIG_PATH);
&close_file($CONFIG_PATH);
return 1;
}
&main();
exit(0);
close $DESTINATION;