tangxifan
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e9154b1f74
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-16 14:42:45 -06:00 |
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tangxifan
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115411941b
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-16 13:15:45 -06:00 |
Baudouin Chauviere
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69014704ef
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Explicit verilog final push
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2019-07-16 13:13:30 -06:00 |
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Baudouin Chauviere
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e602006a07
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-07-16 12:45:13 -06:00 |
AurelienUoU
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b810b5cab9
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fpga_flow bug fix + upload k8 architecture
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2019-07-16 07:04:45 -06:00 |
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AurelienUoU
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35e1962732
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Merge branch 'dev' into documentation
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2019-07-15 21:19:26 -06:00 |
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AurelienUoU
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1cf4e78502
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Update documentation and help
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2019-07-15 21:16:15 -06:00 |
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tangxifan
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bcc6346533
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speeding up identifying unique modules in routing
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2019-07-14 13:49:20 -06:00 |
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tangxifan
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4c6e245885
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speed-up the unique routing process
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2019-07-14 12:22:00 -06:00 |
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tangxifan
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b690e702f6
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adding more info to show the progress bar in backannotating GSBs
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2019-07-13 19:53:44 -06:00 |
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tangxifan
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aa4cd850ae
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try to optimize the runtime of routing uniqueness detection
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2019-07-13 18:10:34 -06:00 |
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tangxifan
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78578f66c5
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bug fixing for heterogeneous blocks. Still we have bugs in 0-driver CHAN nodes in tileable RRG
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2019-07-13 14:48:32 -06:00 |
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Baudouin Chauviere
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f140e08093
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Pre-Merge modifications
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2019-07-12 10:48:43 -06:00 |
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Baudouin Chauviere
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a0f1f8d163
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Fix when explicit verilog is NOT used
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2019-07-12 10:39:31 -06:00 |
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tangxifan
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f0ecc51b51
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bug fixing to resolve the conflicts between explicit port map and standard cell map
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2019-07-12 10:38:20 -06:00 |
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AurelienUoU
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e65cf9f5fd
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Update ERI-demo
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2019-07-12 08:55:19 -06:00 |
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Baudouin Chauviere
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40d3460bac
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Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-07-11 22:13:30 -06:00 |
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Baudouin Chauviere
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e461cd0b99
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Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
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2019-07-11 22:09:49 -06:00 |
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Baudouin Chauviere
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1431ee2f82
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Fix Explicit verilog
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2019-07-11 22:09:34 -06:00 |
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tangxifan
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cffdebd912
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bug fixed for the tileable RR graph generator for heterogeneous blocks
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2019-07-11 21:02:09 -06:00 |
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Baudouin Chauviere
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c9b84f61c9
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Hot fix
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2019-07-11 17:39:02 -06:00 |
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Baudouin Chauviere
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d0cd5a2bc1
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Hot fix
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2019-07-11 17:27:31 -06:00 |
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tangxifan
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9c203ca4d2
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bug fixing in SDC generator
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2019-07-11 17:10:08 -06:00 |
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Baudouin Chauviere
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f4be375637
|
Latest version explicit
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2019-07-11 14:33:56 -06:00 |
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tangxifan
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31749fe62b
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fix bugs in fpga_flow.pl
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2019-07-10 21:12:00 -06:00 |
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tangxifan
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a90316e9f4
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-10 15:13:46 -06:00 |
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tangxifan
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acee0161c7
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Merge branch 'tileable_routing' into dev
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2019-07-10 15:13:24 -06:00 |
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Baudouin Chauviere
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6441f2ebe7
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-10 14:16:55 -06:00 |
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Baudouin Chauviere
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0a978db866
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Fix regression test
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2019-07-10 14:16:34 -06:00 |
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tangxifan
|
b7f9831bd2
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add statistics for unique GSBs
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2019-07-10 13:08:03 -06:00 |
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tangxifan
|
c6a4d29ed8
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Merge branch 'tileable_routing' into dev
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2019-07-10 12:05:43 -06:00 |
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tangxifan
|
57ae5dbbec
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bug fixing for rectangle FPGA sizes
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2019-07-09 20:47:52 -06:00 |
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tangxifan
|
edfe3144c3
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update profiling, found where runtime is lost
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2019-07-09 20:28:01 -06:00 |
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tangxifan
|
737cc2874f
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Merge branch 'tileable_routing' into dev
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2019-07-09 17:42:44 -06:00 |
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tangxifan
|
65f696c1d7
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fix critical bugs in rectangle floorplan
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2019-07-09 17:41:20 -06:00 |
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Baudouin Chauviere
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4ca0967453
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-09 14:35:51 -06:00 |
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Baudouin Chauviere
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792ba23f4f
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Correction pre-merge
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2019-07-09 14:34:34 -06:00 |
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Baudouin Chauviere
|
589f58b55e
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Regression test succeeded
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2019-07-09 09:18:06 -06:00 |
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Baudouin Chauviere
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25f5bc7792
|
Latest version, not stable yet but close
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2019-07-09 08:34:01 -06:00 |
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tangxifan
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5d5e09fcdb
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minor fix in trying to accelerate the unique routing functions
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2019-07-08 17:12:36 -06:00 |
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Baudouin Chauviere
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df0a3d23a3
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Correction top module
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2019-07-08 10:23:14 -06:00 |
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Baudouin Chauviere
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ae05c553d5
|
Top module done
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2019-07-08 09:48:33 -06:00 |
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tangxifan
|
76fefdb876
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bug fixing in Fc_in and be serious in the performance of rr_graph
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2019-07-05 16:23:15 -06:00 |
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tangxifan
|
c62762ce59
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bug fixing in assign ipins to tracks using Fc_in
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2019-07-05 13:42:22 -06:00 |
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tangxifan
|
64d8e9663a
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minor fix to satisfy Fc_in and Fc_out
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2019-07-05 13:13:35 -06:00 |
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tangxifan
|
3077efa74f
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add option to compact tileable routing arch
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2019-07-04 17:13:34 -06:00 |
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tangxifan
|
d64aeef5c4
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add profiling to routing compact process
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2019-07-03 16:57:34 -06:00 |
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tangxifan
|
1a1da30ae9
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fixed a critical bug in using tileable route chan W
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2019-07-03 16:46:43 -06:00 |
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tangxifan
|
b79d276ea9
|
add profiling to fpga_x2p_setup
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2019-07-03 14:44:54 -06:00 |
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tangxifan
|
d5137eb424
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
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2019-07-03 14:31:18 -06:00 |