tangxifan
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7fcd27e000
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now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
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2020-03-03 12:29:58 -07:00 |
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tangxifan
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3241d8bd37
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put analysis sdc writer online. Minor bug in redudant '/' to be fixed
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2020-03-02 19:54:18 -07:00 |
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tangxifan
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037c7e5c43
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adapt top-level function for analysis SDC writer
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2020-03-02 17:58:44 -07:00 |
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tangxifan
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a17c14c363
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clean-up command addition and add fabric bitstream building to sample script
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2020-03-02 10:39:19 -07:00 |
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tangxifan
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aa66042dfb
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move simulation setting annotation to a separated source file
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2020-02-29 15:19:02 -07:00 |
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tangxifan
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7b18f7cd09
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now the auto select number of clocks in simulation is online
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2020-02-29 13:29:16 -07:00 |
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tangxifan
|
542fadaaae
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allow users to use VPR critical path delay in OpenFPGA simulation
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2020-02-28 12:10:27 -07:00 |
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tangxifan
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de8425874c
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use user defined critical path delay in SDC generation
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2020-02-28 11:24:39 -07:00 |
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tangxifan
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092e10afda
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bring pnr sdc generator online and fixed minor bugs in bitstream writing
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2020-02-28 11:14:50 -07:00 |
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tangxifan
|
9b769cd8e4
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bug fix for using renamed i/o names
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2020-02-27 16:37:20 -07:00 |
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tangxifan
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078f72320f
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debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
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2020-02-27 13:24:26 -07:00 |
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tangxifan
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f558405887
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ported verilog testbench generator online. Split from fabric generator. Testing to be done
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2020-02-27 12:33:09 -07:00 |
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tangxifan
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b3796b0818
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build io location map
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2020-02-26 19:58:18 -07:00 |
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tangxifan
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25e0583636
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add io location map data structure and start porting verilog testbench generator
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2020-02-26 17:10:57 -07:00 |
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tangxifan
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a26d31b87f
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make write bitstream online
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2020-02-26 11:09:23 -07:00 |
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tangxifan
|
4024ed63cb
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add truth table build up for physical LUTs
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2020-02-25 22:39:42 -07:00 |
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tangxifan
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8e9660b816
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add mapped block fast look-up as placement annotation
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2020-02-24 16:09:29 -07:00 |
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tangxifan
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2d17395e13
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start integrating fpga_bitstream. Bring data structures online
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2020-02-22 23:04:42 -07:00 |
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tangxifan
|
4abaef14b5
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bug fixed in pb_pin fix-up. This is due to A CRITICAL BUG IN PHYSICAL_TILE PIN MAPPING!!!
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2020-02-20 20:50:59 -07:00 |
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tangxifan
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3e07d7d5e0
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finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset
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2020-02-20 20:26:20 -07:00 |
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tangxifan
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fdb27c5a6b
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move lb_rr_graph construction to repack command
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2020-02-20 13:24:34 -07:00 |
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tangxifan
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409b3f6896
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add lb_rr_graph builder for the refactored version
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2020-02-17 21:11:56 -07:00 |
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tangxifan
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8e97443410
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start working on repack
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2020-02-17 17:57:43 -07:00 |
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tangxifan
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62e4f14e30
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add lb_rr_graph to device annotation
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2020-02-17 17:26:27 -07:00 |
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tangxifan
|
6c69b52ded
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Add missing file
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2020-02-17 17:11:29 -07:00 |
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tangxifan
|
e37ac8a098
|
add grid module Verilog writer
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2020-02-16 16:04:41 -07:00 |
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tangxifan
|
c6c3ef71f3
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adapt all the Verilog submodule writers and bring it onlien
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2020-02-16 13:35:18 -07:00 |
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tangxifan
|
bf54be3d00
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add option data structure for FPGA Verilog
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2020-02-15 21:39:47 -07:00 |
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tangxifan
|
da79ef687c
|
add missing files
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2020-02-15 20:54:37 -07:00 |
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tangxifan
|
8b0df8632c
|
bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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tangxifan
|
539f13720a
|
tile direct supports inter-column/inter-row direct connections
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2020-02-15 13:42:53 -07:00 |
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tangxifan
|
213c611c0b
|
add tile direct builder
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2020-02-14 22:21:32 -07:00 |
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tangxifan
|
afe8278670
|
put routing module builder online
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2020-02-13 17:35:29 -07:00 |
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tangxifan
|
89086ed080
|
add verbose output to build grid module
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2020-02-13 15:38:26 -07:00 |
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tangxifan
|
072965cd64
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make grid module builder online; basic support on physical tiles
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2020-02-13 15:27:16 -07:00 |
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tangxifan
|
895d5b5a0a
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add utils for grid module builder
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2020-02-12 20:25:05 -07:00 |
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tangxifan
|
fddd3c9463
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add mux module builder
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2020-02-12 19:45:14 -07:00 |
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tangxifan
|
f11832b8cf
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start integrating module graph builder
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2020-02-12 17:53:23 -07:00 |
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tangxifan
|
13fadd0f91
|
move compact routing hierarchy to build_fabric command
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2020-02-12 15:49:47 -07:00 |
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tangxifan
|
c78d3e9af1
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add mux library builder
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2020-02-12 14:58:23 -07:00 |
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tangxifan
|
a736e09c29
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add rr_switch binding in link openfpga arch command
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2020-02-12 10:52:20 -07:00 |
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tangxifan
|
a31d6c6d1e
|
rename pb_type annotation to device annotation
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2020-02-12 09:52:18 -07:00 |
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tangxifan
|
175bef014a
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add compact_routing hierarchy command
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2020-02-11 17:40:37 -07:00 |
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tangxifan
|
1372f748f1
|
put GSB builder online
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2020-02-11 16:37:14 -07:00 |
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tangxifan
|
3d7eff64b9
|
bug fixed for lut truth table fixup. Results look good
|
2020-02-06 17:47:25 -07:00 |
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tangxifan
|
ed9e038845
|
add functionality of LUT truth table fix-up
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2020-02-06 17:14:29 -07:00 |
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tangxifan
|
99f5a86b49
|
bug fixed for routing annotation and routing net fix-up
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2020-02-06 12:54:55 -07:00 |
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tangxifan
|
dad204674b
|
done an initial version of clustering net fix-up based on routing results. Debugging on the way
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2020-02-05 21:50:52 -07:00 |
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tangxifan
|
75c3507acf
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add verbose output option for openfpga linking architecture
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2020-01-31 11:36:58 -07:00 |
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tangxifan
|
d62c9fe86f
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adding pb_graph_node annotation
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2020-01-30 16:40:13 -07:00 |