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bug fixed for lut truth table fixup. Results look good

This commit is contained in:
tangxifan 2020-02-06 17:47:25 -07:00
parent ed9e038845
commit 3d7eff64b9
2 changed files with 32 additions and 6 deletions
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34
openfpga/src/base/openfpga_lut_truth_table_fixup.cpp
View File

@ -52,7 +52,7 @@ void fix_up_lut_atom_block_truth_table(const AtomContext& atom_ctx,
/* Port exists (some LUTs may have no input and hence no port in the atom netlist) */
AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, pb_type->ports[iport].model_port);
if (atom_port) {
if (!atom_port) {
continue;
}
@ -90,12 +90,31 @@ void fix_up_lut_atom_block_truth_table(const AtomContext& atom_ctx,
/* Print info is in the verbose mode */
VTR_LOGV(verbose, "Original truth table\n");
VTR_LOGV(verbose, "Index: ");
for (size_t i = 0; i < rotated_pin_map.size(); ++i) {
if (0 < i) {
VTR_LOGV(verbose, ",");
}
VTR_LOGV(verbose, "%lu", i);
}
VTR_LOGV(verbose, "\n");
for (const std::string& tt_line : truth_table_to_string(orig_tt)) {
VTR_LOGV(verbose, "\t%s\n", tt_line.c_str());
}
VTR_LOGV(verbose, "\n");
VTR_LOGV(verbose, "Pin rotation map: ");
for (size_t i = 0; i < rotated_pin_map.size(); ++i) {
if (0 < i) {
VTR_LOGV(verbose, ",");
}
if (-1 == rotated_pin_map[i]) {
VTR_LOGV(verbose, "open");
} else {
VTR_LOGV(verbose, "%lu", rotated_pin_map[i]);
}
}
VTR_LOGV(verbose, "\n");
VTR_LOGV(verbose, "Adapt truth table\n");
VTR_LOGV(verbose, "-----------------\n");
for (const std::string& tt_line : truth_table_to_string(adapt_tt)) {
VTR_LOGV(verbose, "\t%s\n", tt_line.c_str());
}
@ -120,8 +139,15 @@ void rec_adapt_lut_pb_tt(const AtomContext& atom_ctx,
/* If we reach a primitive pb_graph node, we return */
if (true == is_primitive_pb_type(pb_graph_node->pb_type)) {
if (LUT_CLASS == pb_graph_node->pb_type->class_type) {
/* Do fix-up here */
fix_up_lut_atom_block_truth_table(atom_ctx, pb, pb_route, vpr_clustering_annotation, verbose);
/* Do fix-up here.
* Note that LUTs have two modes,
* For wire modes, we should skip the truth table adaption
* mode 0 is reserved for wire, see read_xml_arch_file.cpp
* mode 1 is the regular mode
*/
if (1 == pb->mode) {
fix_up_lut_atom_block_truth_table(atom_ctx, pb->child_pbs[0], pb_route, vpr_clustering_annotation, verbose);
}
}
return;
}

4
openfpga/src/utils/lut_utils.cpp
View File

@ -35,11 +35,11 @@ AtomNetlist::TruthTable lut_truth_table_adaption(const AtomNetlist::TruthTable&
AtomNetlist::TruthTable tt;
for (auto row : orig_tt) {
VTR_ASSERT(row.size() - 1 == rotated_pin_map.size());
VTR_ASSERT(row.size() - 1 <= rotated_pin_map.size());
std::vector<vtr::LogicValue> tt_line;
/* We do not care about the last digit, which is the output value */
for (size_t i = 0; i < row.size() - 1; ++i) {
for (size_t i = 0; i < rotated_pin_map.size(); ++i) {
if (-1 == rotated_pin_map[i]) {
tt_line.push_back(vtr::LogicValue::DONT_CARE);
} else {