add mux library builder
This commit is contained in:
tangxifan
parent
ce63b1cc62
commit
c78d3e9af1
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@ -7,6 +7,7 @@
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#include "vpr_device_annotation.h"
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#include "vpr_clustering_annotation.h"
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#include "vpr_routing_annotation.h"
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#include "mux_library.h"
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#include "device_rr_gsb.h"
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/********************************************************************
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@ -44,6 +45,7 @@ class OpenfpgaContext : public Context {
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const openfpga::VprClusteringAnnotation& vpr_clustering_annotation() const { return vpr_clustering_annotation_; }
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const openfpga::VprRoutingAnnotation& vpr_routing_annotation() const { return vpr_routing_annotation_; }
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const openfpga::DeviceRRGSB& device_rr_gsb() const { return device_rr_gsb_; }
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const openfpga::MuxLibrary& mux_lib() const { return mux_lib_; }
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public: /* Public mutators */
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openfpga::Arch& mutable_arch() { return arch_; }
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openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
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@ -51,6 +53,7 @@ class OpenfpgaContext : public Context {
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openfpga::VprClusteringAnnotation& mutable_vpr_clustering_annotation() { return vpr_clustering_annotation_; }
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openfpga::VprRoutingAnnotation& mutable_vpr_routing_annotation() { return vpr_routing_annotation_; }
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openfpga::DeviceRRGSB& mutable_device_rr_gsb() { return device_rr_gsb_; }
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openfpga::MuxLibrary& mutable_mux_lib() { return mux_lib_; }
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private: /* Internal data */
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/* Data structure to store information from read_openfpga_arch library */
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openfpga::Arch arch_;
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@ -69,6 +72,9 @@ class OpenfpgaContext : public Context {
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/* Device-level annotation */
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openfpga::DeviceRRGSB device_rr_gsb_;
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/* Library of physical implmentation of routing multiplexers */
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openfpga::MuxLibrary mux_lib_;
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};
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#endif
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@ -13,6 +13,7 @@
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#include "annotate_pb_graph.h"
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#include "annotate_routing.h"
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#include "annotate_rr_graph.h"
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#include "mux_library_builder.h"
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#include "openfpga_link_arch.h"
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/* Include global variables of VPR */
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@ -21,6 +22,28 @@
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* A function to identify if the routing resource graph generated by
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* VPR is support by OpenFPGA
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* - Currently we only support uni-directional
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* It means every routing tracks must have a direction
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*******************************************************************/
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static
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bool is_vpr_rr_graph_supported(const RRGraph& rr_graph) {
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/* Check if the rr_graph is uni-directional*/
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for (const RRNodeId& node : rr_graph.nodes()) {
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if (CHANX != rr_graph.node_type(node) && CHANY != rr_graph.node_type(node)) {
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continue;
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}
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if (BI_DIRECTION == rr_graph.node_direction(node)) {
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VTR_LOG_ERROR("Routing resource graph is bi-directional. OpenFPGA currently supports uni-directional routing architecture only.\n");
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return false;
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}
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}
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return true;
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}
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/********************************************************************
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* Top-level function to link openfpga architecture to VPR, including:
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* - physical pb_type
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@ -72,9 +95,17 @@ void link_arch(OpenfpgaContext& openfpga_context,
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* - RRGSB
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* - DeviceRRGSB
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*/
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if (false == is_vpr_rr_graph_supported(g_vpr_ctx.device().rr_graph)) {
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return;
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}
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annotate_device_rr_gsb(g_vpr_ctx.device(),
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openfpga_context.mutable_device_rr_gsb(),
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cmd_context.option_enable(cmd, opt_verbose));
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/* Build multiplexer library */
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openfpga_context.mutable_mux_lib() = build_device_mux_library(g_vpr_ctx.device(),
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const_cast<const OpenfpgaContext&>(openfpga_context));
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}
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} /* end namespace openfpga */
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@ -0,0 +1,228 @@
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/********************************************************************
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* This file includes the functions of builders for MuxLibrary.
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*******************************************************************/
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#include <cmath>
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/* Headers from vtrutil library */
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#include "vtr_time.h"
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from readarchopenfpga library */
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#include "circuit_types.h"
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#include "circuit_library.h"
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#include "mux_utils.h"
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#include "pb_type_utils.h"
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#include "pb_graph_utils.h"
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#include "openfpga_rr_graph_utils.h"
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#include "mux_library.h"
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#include "mux_library_builder.h"
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/* Begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Update MuxLibrary with the unique multiplexer structures
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* found in the global routing architecture
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*******************************************************************/
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static
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void build_routing_arch_mux_library(const DeviceContext& vpr_device_ctx,
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const CircuitLibrary& circuit_lib,
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const VprDeviceAnnotation& vpr_device_annotation,
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MuxLibrary& mux_lib) {
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/* The routing path is.
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* OPIN ----> CHAN ----> ... ----> CHAN ----> IPIN
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* Each edge is a switch, for IPIN, the switch is a connection block,
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* for the rest is a switch box
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*/
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/* Count the sizes of muliplexers in routing architecture */
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for (const RRNodeId& node : vpr_device_ctx.rr_graph.nodes()) {
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switch (vpr_device_ctx.rr_graph.node_type(node)) {
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case IPIN:
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case CHANX:
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case CHANY: {
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/* Have to consider the fan_in only, it is a connection block (multiplexer)*/
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if ( (0 == vpr_device_ctx.rr_graph.node_in_edges(node).size())
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|| (1 == vpr_device_ctx.rr_graph.node_in_edges(node).size()) ) {
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break;
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}
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/* Find the circuit_model for multiplexers in connection blocks */
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std::vector<RRSwitchId> driver_switches = get_rr_graph_driver_switches(vpr_device_ctx.rr_graph, node);
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VTR_ASSERT(1 == driver_switches.size());
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const CircuitModelId& rr_switch_circuit_model = vpr_device_annotation.rr_switch_circuit_model(driver_switches[0]);
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/* we should select a circuit model for the routing resource switch */
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VTR_ASSERT(CircuitModelId::INVALID() != rr_switch_circuit_model);
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/* Add the mux to mux_library */
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mux_lib.add_mux(circuit_lib, rr_switch_circuit_model, vpr_device_ctx.rr_graph.node_in_edges(node).size());
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break;
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}
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default:
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/* We do not care other types of rr_node */
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break;
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}
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}
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}
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/********************************************************************
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* For a given pin of a pb_graph_node
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* - Identify the interconnect implementation
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* - Find the number of inputs for the interconnect implementation
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* - Update the mux_library is the implementation is multiplexers
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********************************************************************/
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static
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void build_pb_graph_pin_interconnect_mux_library(t_pb_graph_pin* pb_graph_pin,
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t_mode* interconnect_mode,
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const CircuitLibrary& circuit_lib,
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const VprDeviceAnnotation& vpr_device_annotation,
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MuxLibrary& mux_lib) {
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/* Find the interconnect in the physical mode that drives this pin */
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t_interconnect* physical_interc = pb_graph_pin_interc(pb_graph_pin, interconnect_mode);
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/* Bypass if the interc does not indicate multiplexers */
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if (MUX_INTERC != vpr_device_annotation.interconnect_physical_type(physical_interc)) {
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return;
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}
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size_t mux_size = pb_graph_pin_inputs(pb_graph_pin, physical_interc).size();
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VTR_ASSERT(true == valid_mux_implementation_num_inputs(mux_size));
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const CircuitModelId& interc_circuit_model = vpr_device_annotation.interconnect_circuit_model(physical_interc);
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VTR_ASSERT(CircuitModelId::INVALID() != interc_circuit_model);
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/* Add the mux model to library */
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mux_lib.add_mux(circuit_lib, interc_circuit_model, mux_size);
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}
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/********************************************************************
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* Update MuxLibrary with the unique multiplexer structures
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* found in programmable logic blocks
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********************************************************************/
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static
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void rec_build_vpr_physical_pb_graph_node_mux_library(t_pb_graph_node* pb_graph_node,
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const CircuitLibrary& circuit_lib,
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const VprDeviceAnnotation& vpr_device_annotation,
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MuxLibrary& mux_lib) {
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/* Find the number of inputs for each interconnect of this pb_graph_node
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* This is only applicable to each interconnect which will be implemented with multiplexers
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*/
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t_mode* parent_physical_mode = nullptr;
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if (false == pb_graph_node->is_root()) {
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parent_physical_mode = vpr_device_annotation.physical_mode(pb_graph_node->parent_pb_graph_node->pb_type);
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}
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for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) {
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for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ++ipin) {
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build_pb_graph_pin_interconnect_mux_library(&(pb_graph_node->input_pins[iport][ipin]),
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parent_physical_mode,
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circuit_lib,
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vpr_device_annotation,
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mux_lib);
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}
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}
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for (int iport = 0; iport < pb_graph_node->num_clock_ports; ++iport) {
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for (int ipin = 0; ipin < pb_graph_node->num_clock_pins[iport]; ++ipin) {
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build_pb_graph_pin_interconnect_mux_library(&(pb_graph_node->clock_pins[iport][ipin]),
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parent_physical_mode,
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circuit_lib,
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vpr_device_annotation,
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mux_lib);
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}
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}
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/* Return if this is a primitive node */
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if (true == is_primitive_pb_type(pb_graph_node->pb_type)) {
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return;
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}
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/* Get the physical mode, primitive node does not have physical mode */
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t_mode* physical_mode = vpr_device_annotation.physical_mode(pb_graph_node->pb_type);
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VTR_ASSERT(nullptr != physical_mode);
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/* Note that the output port interconnect should be considered for non-primitive nodes */
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for (int iport = 0; iport < pb_graph_node->num_output_ports; ++iport) {
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for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ++ipin) {
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build_pb_graph_pin_interconnect_mux_library(&(pb_graph_node->output_pins[iport][ipin]),
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physical_mode,
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circuit_lib,
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vpr_device_annotation,
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mux_lib);
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}
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}
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/* Visit all the child nodes in the physical mode */
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for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
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for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
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rec_build_vpr_physical_pb_graph_node_mux_library(&(pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]),
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circuit_lib, vpr_device_annotation,
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mux_lib);
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}
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}
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}
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/********************************************************************
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* Update MuxLibrary with the unique multiplexers required by
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* LUTs in the circuit library
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********************************************************************/
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static
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void build_lut_mux_library(MuxLibrary& mux_lib,
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const CircuitLibrary& circuit_lib) {
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/* Find all the circuit models which are LUTs in the circuit library */
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for (const auto& circuit_model : circuit_lib.models()) {
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/* Bypass non-LUT circuit models */
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if (CIRCUIT_MODEL_LUT != circuit_lib.model_type(circuit_model)) {
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continue;
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}
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/* Find the MUX size required by the LUT */
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/* Get input ports which are not global ports! */
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std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
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VTR_ASSERT(1 == input_ports.size());
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/* MUX size = 2^lut_size */
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size_t lut_mux_size = (size_t)pow(2., (double)(circuit_lib.port_size(input_ports[0])));
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/* Add mux to the mux library */
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mux_lib.add_mux(circuit_lib, circuit_model, lut_mux_size);
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}
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}
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/* Statistic for all the multiplexers in FPGA
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* We determine the sizes and its structure (according to spice_model) for each type of multiplexers
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* We search multiplexers in Switch Blocks, Connection blocks and Configurable Logic Blocks
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* In additional to multiplexers, this function also consider crossbars.
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* All the statistics are stored in a linked list, as a return value
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*/
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MuxLibrary build_device_mux_library(const DeviceContext& vpr_device_ctx,
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const OpenfpgaContext& openfpga_ctx) {
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vtr::ScopedStartFinishTimer timer("Build a library of physical multiplexers");
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/* MuxLibrary to store the information of Multiplexers*/
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MuxLibrary mux_lib;
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/* Step 1: We should check the multiplexer spice models defined in routing architecture.*/
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build_routing_arch_mux_library(vpr_device_ctx, openfpga_ctx.arch().circuit_lib,
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openfpga_ctx.vpr_device_annotation(),
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mux_lib);
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/* Step 2: Count the sizes of multiplexers in complex logic blocks */
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for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
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/* By pass nullptr for pb_graph head */
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if (nullptr == lb_type.pb_graph_head) {
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continue;
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}
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rec_build_vpr_physical_pb_graph_node_mux_library(lb_type.pb_graph_head,
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openfpga_ctx.arch().circuit_lib,
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openfpga_ctx.vpr_device_annotation(),
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mux_lib);
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}
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/* Step 3: count the size of multiplexer that will be used in LUTs*/
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build_lut_mux_library(mux_lib, openfpga_ctx.arch().circuit_lib);
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VTR_LOG("Built a multiplexer library of %lu physical multiplexers.\n",
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mux_lib.muxes().size());
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VTR_LOG("Maximum multiplexer size is %lu.\n",
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mux_lib.max_mux_size());
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return mux_lib;
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}
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} /* End namespace openfpga*/
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@ -0,0 +1,23 @@
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#ifndef MUX_LIBRARY_BUILDER_H
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#define MUX_LIBRARY_BUILDER_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include "vpr_context.h"
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#include "openfpga_context.h"
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#include "mux_library.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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MuxLibrary build_device_mux_library(const DeviceContext& vpr_device_ctx,
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const OpenfpgaContext& openfpga_ctx);
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} /* end namespace openfpga */
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#endif
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@ -2,6 +2,8 @@
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* This file includes most utilized functions for the rr_graph
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* data structure in the OpenFPGA context
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*******************************************************************/
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#include <algorithm>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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@ -63,4 +65,20 @@ vtr::Point<size_t> get_track_rr_node_end_coordinate(const RRGraph& rr_graph,
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return end_coordinator;
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}
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/************************************************************************
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* Find the driver switches for a node in the rr_graph
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* This function only return unique driver switches
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***********************************************************************/
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std::vector<RRSwitchId> get_rr_graph_driver_switches(const RRGraph& rr_graph,
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const RRNodeId& node) {
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std::vector<RRSwitchId> driver_switches;
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for (const RREdgeId& edge : rr_graph.node_in_edges(node)) {
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if (driver_switches.end() == std::find(driver_switches.begin(), driver_switches.end(), rr_graph.edge_switch(edge))) {
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driver_switches.push_back(rr_graph.edge_switch(edge));
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}
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}
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return driver_switches;
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}
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} /* end namespace openfpga */
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@ -23,6 +23,9 @@ vtr::Point<size_t> get_track_rr_node_start_coordinate(const RRGraph& rr_graph,
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vtr::Point<size_t> get_track_rr_node_end_coordinate(const RRGraph& rr_graph,
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const RRNodeId& track_rr_node);
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std::vector<RRSwitchId> get_rr_graph_driver_switches(const RRGraph& rr_graph,
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const RRNodeId& node);
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} /* end namespace openfpga */
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#endif
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@ -38,4 +38,29 @@ std::vector<t_pb_graph_pin*> pb_graph_pin_inputs(t_pb_graph_pin* pb_graph_pin,
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return inputs;
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}
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/********************************************************************
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* This function aims to find out the interconnect that drives
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* a given pb_graph pin when operating in a select mode
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*******************************************************************/
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t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin,
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t_mode* selected_mode) {
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t_interconnect* interc = nullptr;
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/* Search the input edges only, stats on the size of MUX we may need (fan-in) */
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for (int iedge = 0; iedge < pb_graph_pin->num_input_edges; ++iedge) {
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/* We care the only edges in the selected mode */
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if (selected_mode != pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) {
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continue;
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}
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/* There should be one unique interconnect to be found! */
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if (nullptr != interc) {
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VTR_ASSERT(interc == pb_graph_pin->input_edges[iedge]->interconnect);
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} else {
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interc = pb_graph_pin->input_edges[iedge]->interconnect;
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}
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}
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return interc;
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}
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} /* end namespace openfpga */
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@ -18,6 +18,9 @@ namespace openfpga {
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std::vector<t_pb_graph_pin*> pb_graph_pin_inputs(t_pb_graph_pin* pb_graph_pin,
|
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t_interconnect* selected_interconnect);
|
||||
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||||
t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin,
|
||||
t_mode* selected_mode);
|
||||
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||||
} /* end namespace openfpga */
|
||||
|
||||
#endif
|
||||
|
|
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Loading…
Reference in New Issue