107 Commits

Author	SHA1	Message	Date
tangxifan	d60d0540da	[test] adding a new test case to validate the bitstream overloading for DSP blocks	2023-01-24 14:58:52 -08:00
tangxifan	bc51be4863	[benchmark] syntax	2023-01-18 18:34:24 -08:00
tangxifan	b6ae829518	[benchmark] add a new benchmark to validate dff	2023-01-18 17:59:52 -08:00
tangxifan	2c9593c1d4	[test] now use a new benchmark: discrete dffn to validate the clk gen locally feature	2023-01-15 13:09:40 -08:00
tangxifan	6400605603	[benchmark] add clock divider	2023-01-13 16:39:06 -08:00
tangxifan	ce0fbe1765	[test] fixed a few bugs	2022-09-29 15:32:31 -07:00
tangxifan	9bc9b61d35	[test] fixed a few bugs	2022-09-29 15:11:30 -07:00
tangxifan	df1ae7ba2a	[benchmark] add a new benchmark to enhance the tests for wire-lut features in repacker	2022-09-29 14:23:17 -07:00
tangxifan	a3d070ac6f	[benchmark] Now the rst_on_lut benchmark has a comb output driven by rst	2022-09-12 10:43:21 -07:00
tangxifan	314f5395b4	[benchmark] fixed a bug which causes yosys failed	2022-09-09 17:04:59 -07:00
tangxifan	7a38c7dd18	[benchmark] add a new benchmark to test reset signal to drive both lut and ff	2022-09-09 16:42:55 -07:00
tangxifan	9c7868cfab	[hdl] add a counter design which is triggered by negative edges	2022-05-09 16:41:21 +08:00
tangxifan	430580f138	[HDL] Fix a typo	2022-02-15 16:09:14 -08:00
tangxifan	a7786efde1	[HDL] Now dual-clock counter has only 1 reset pin	2022-02-15 16:07:50 -08:00
tangxifan	7121513396	[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work	2022-02-15 15:21:08 -08:00
tangxifan	48355d1fc3	[Benchmark] Add pipelined multiplier benchmark to test DSP block with registers	2022-01-02 20:16:59 -08:00
Aram Kostanyan	b332a5a1b4	Added 'basic_tests/verific_test' test-case.	2021-11-01 18:20:57 +05:00
tangxifan	5a6874e9f1	[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks	2021-07-02 17:28:17 -06:00
tangxifan	0b6a9b06f5	[Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality	2021-07-02 10:39:07 -06:00
ANDREW HARRIS POND	1d281765ea	fixed tab spacing	2021-07-01 16:42:04 -06:00
ANDREW HARRIS POND	808821bb8c	fixed errors	2021-07-01 16:40:03 -06:00
ANDREW HARRIS POND	8513b8a4ff	Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench	2021-07-01 15:29:39 -06:00
ANDREW HARRIS POND	2567fbee05	ready to merge	2021-07-01 15:28:59 -06:00
tangxifan	04ceeefb0a	Merge branch 'master' into verilog_testbench	2021-07-01 14:43:26 -06:00
ANDREW HARRIS POND	db9231c225	tests failing with initial blocks	2021-07-01 13:52:28 -06:00
Andrew Pond	fab2b069f0	added signal gen regression test to shell script	2021-06-30 16:18:09 -06:00
tangxifan	a898537474	[Benchmark] Remove redundant post-synthesis netlist for ``adder_8``	2021-06-30 15:29:13 -06:00
tangxifan	4d4577bb83	[Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders	2021-06-30 15:13:47 -06:00
tangxifan	477cba1c7e	Merge branch 'master' into verilog_testbench	2021-06-23 09:18:18 -06:00
tangxifan	0a0d10b36d	[HDL] Bug fix in Verilog syntax	2021-06-22 16:18:46 -06:00
tangxifan	07dcf3ad27	[HDL] Add more micro benchmarks for counter, and-gate and mac unit	2021-06-21 16:48:35 -06:00
Andrew Pond	3cfc42cdf9	added testbench CI	2021-06-15 14:16:31 -06:00
Andrew Pond	12b44e0eca	added configuration benchmark files	2021-05-13 10:04:23 -06:00
tangxifan	16fff90607	[Benchmark] Add microbenchmark 1-bit blinking	2021-05-06 15:17:27 -06:00
tangxifan	a571b063b6	[Benchmark] Add 1k DPRAM benchmark which can fit new arch	2021-04-28 11:26:31 -06:00
tangxifan	7d059f7407	[Benchmark] Bug fix in dual port ram 16k benchmark	2021-04-27 23:33:20 -06:00
tangxifan	3c1c33bf1e	[Benchmark] Add a microbenchmark just fit 16k dual port ram	2021-04-27 22:51:43 -06:00
tangxifan	7e2368158e	[Benchmark] move benchmarks to microbenchmark category	2021-04-27 22:12:30 -06:00
tangxifan	5a85ec9fa0	[Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised	2021-04-27 22:09:10 -06:00
tangxifan	1d498bb296	[Benchmark] Add a scalable micro benchmark fifo	2021-04-27 15:26:52 -06:00
tangxifan	200b6d39a6	[Benchmark] Add more micro benchmarks for mac ranging from 8 bit to 32 bit	2021-04-23 20:36:28 -06:00
tangxifan	671394ec2c	[Benchmark] Add microbenchmarks for mac with different sizes for DSP testing	2021-04-23 20:33:43 -06:00
tangxifan	b203ef7bc2	[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs	2021-04-21 14:03:51 -06:00
tangxifan	c020333512	Merge branch 'master' into dff_techmap	2021-04-16 20:54:28 -06:00
tangxifan	bbdc0e53af	[Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures	2021-04-16 20:14:48 -06:00
tangxifan	e46c6e75a3	[Benchmark] Add missing RTL for IWLS2005 benchmarks	2021-04-16 16:50:41 -06:00
tangxifan	26d3b5a954	[Benchmark] Reorganize iwls2005 benchmark: separate the location of rtl and testbenches	2021-04-16 16:08:58 -06:00
tangxifan	86ad572530	[Benchmark] Add opencore RTLs from IWLS 2005 benchmarks	2021-04-16 14:27:54 -06:00
tangxifan	44d97ead86	Merge branch 'master' into hetergeneous_arch	2021-03-23 17:05:03 -06:00
tangxifan	be03eafd66	[Benchmark] Add a micro benchmark: 8-bit multiply and accumulate	2021-03-23 15:33:37 -06:00