tangxifan
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f89b7a82cf
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[arch] fixed a bug where the array size mismatch the layout name
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2023-05-03 22:23:20 +08:00 |
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tangxifan
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8d02a6e600
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[test] now testcases are using proper arch
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2023-05-03 21:47:21 +08:00 |
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tangxifan
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df771cb33a
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[test] add a new testcase for subtile and deploy it to basic regression test
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2023-05-03 15:41:29 +08:00 |
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tangxifan
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a3f2ae3c33
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[arch] format
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2023-05-03 15:23:47 +08:00 |
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tangxifan
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02a5057449
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[arch] add openfpga arch example using subtile; updated documentation
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2023-05-03 15:20:49 +08:00 |
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tangxifan
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68f2d9fe5e
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[arch] add new example arch using subtile in I/O blocks; Updated documentation
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2023-05-03 15:16:39 +08:00 |
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tangxifan
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f06248a1b0
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[test] add a new testcase to validate the ccff v2
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2023-04-24 14:55:22 +08:00 |
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tangxifan
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02e964b16f
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[test] add a new test case for ccffv2
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2023-04-22 15:41:19 +08:00 |
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tangxifan
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087636cefa
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[test] deploy new test to regression tests
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2023-04-20 15:06:47 +08:00 |
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tangxifan
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40598d25a3
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[core] fixed a bug which causes multi-clock programmable network failed in routing
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2023-04-20 15:05:45 +08:00 |
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tangxifan
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fba0a83679
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[test] debugging 2-clock network
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2023-04-20 14:44:01 +08:00 |
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tangxifan
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02b02d18a5
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[test] fixed a bug in clock arch
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2023-04-20 11:35:36 +08:00 |
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tangxifan
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b242fd97d6
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[test] adding new arch and testcase for 2-clock network
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2023-04-20 11:31:49 +08:00 |
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tangxifan
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03cb664049
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[test] now clock network example script supports multiple clocks
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2023-04-20 10:56:36 +08:00 |
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tangxifan
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7d333b3669
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[test] add a new test for clock network: validate full testbench is working
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2023-04-20 10:36:08 +08:00 |
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tangxifan
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1f9c1fe7e1
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[test] clean up clock network task config
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2023-04-20 10:31:22 +08:00 |
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tangxifan
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571a012724
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[test] xml format
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2023-03-07 18:47:55 -08:00 |
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tangxifan
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7e3b656c51
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[test] fixed a bug in arch
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2023-03-06 23:06:32 -08:00 |
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tangxifan
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fd1c4039d3
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[test] typo
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2023-03-02 21:37:24 -08:00 |
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tangxifan
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02b50e3464
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[lib] now clock spine requires explicit definition of track type and direction when coordinate is vague
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2023-03-02 21:33:32 -08:00 |
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tangxifan
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b9f7c72a96
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[test] fixed some bugs in arch
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2023-03-02 18:16:59 -08:00 |
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tangxifan
|
5917446fbe
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[arch] code format
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2023-02-28 22:01:49 -08:00 |
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tangxifan
|
780dec6b1b
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[test] add a new test to validate the programmable clock arch
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2023-02-28 21:46:57 -08:00 |
Ganesh Gore
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4f6b8c0905
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Updated regression tests
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2023-02-11 22:11:06 -07:00 |
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Ganesh Gore
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f7c710e95e
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renamed yosys_vpr_template fabric_netlist_gen_template
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2023-02-11 18:33:06 -07:00 |
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Ganesh Gore
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b2bdfb7475
|
Strip down task
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2023-02-11 18:32:06 -07:00 |
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Ganesh Gore
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b71a1014e8
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renamed vpr_blif_template to fabric_verification_template
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2023-02-11 18:29:21 -07:00 |
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Ganesh Gore
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6a48f1eb05
|
Updated demo projects
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2023-02-11 18:24:20 -07:00 |
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Ganesh Gore
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a6263c44af
|
Updated format
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2023-02-11 18:12:04 -07:00 |
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Ganesh Gore
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2afb91596f
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Refactored run_openfpga_task.py
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2023-02-11 18:04:54 -07:00 |
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tangxifan
|
57cec96d7e
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[script] wrong path to yosys bin
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2023-02-03 22:54:22 -08:00 |
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tangxifan
|
ff31a7b828
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[script] fixed the path to yosys bin for openfpga flow
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2023-02-03 22:12:03 -08:00 |
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tangxifan
|
aff8178581
|
[test] fixed remaining bugs
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2023-01-24 18:00:04 -08:00 |
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tangxifan
|
d1e951e52e
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[test] debugging
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2023-01-24 17:57:34 -08:00 |
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tangxifan
|
f964c9ed67
|
[test] debug
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2023-01-24 15:48:57 -08:00 |
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tangxifan
|
8174f53796
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[test] deploy new test to fpga bitstream regression
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2023-01-24 15:42:01 -08:00 |
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tangxifan
|
499d352cff
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[flow] add yosys rewrite scripts
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2023-01-24 15:39:42 -08:00 |
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tangxifan
|
e7a3b48475
|
[arch] comment on the wrong mode bits
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2023-01-24 15:24:17 -08:00 |
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tangxifan
|
fec84d76d1
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[arch] adding tech lib;
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2023-01-24 15:22:34 -08:00 |
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tangxifan
|
1d8c1a6803
|
[arch] adding a new arch to validate fracturable dsp
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2023-01-24 15:17:50 -08:00 |
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tangxifan
|
d60d0540da
|
[test] adding a new test case to validate the bitstream overloading for DSP blocks
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2023-01-24 14:58:52 -08:00 |
|
tangxifan
|
f586229b97
|
[test] enable rst_on_lut benchmark
|
2023-01-18 19:45:41 -08:00 |
|
tangxifan
|
b7a66705e0
|
[test] now use yosys_vpr flow; add rst_on_lut benchmark
|
2023-01-18 19:42:50 -08:00 |
|
tangxifan
|
bc51be4863
|
[benchmark] syntax
|
2023-01-18 18:34:24 -08:00 |
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tangxifan
|
e974e5ddf7
|
[test] now allow to select vpr device layout for test cases that ignores global nets on regular CLB inputs
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2023-01-18 18:31:36 -08:00 |
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tangxifan
|
acc905fa11
|
[arch] add support to route reset to LUTs
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2023-01-18 18:22:37 -08:00 |
|
tangxifan
|
95dd4fd535
|
[test] deploy new test to basic regression tests
|
2023-01-18 18:17:53 -08:00 |
|
tangxifan
|
03273371c0
|
[test] add a new test to validate local reset
|
2023-01-18 18:17:14 -08:00 |
|
tangxifan
|
c9e00b7abc
|
[arch] add a new example arch that supports local reset
|
2023-01-18 18:05:52 -08:00 |
|
tangxifan
|
b6ae829518
|
[benchmark] add a new benchmark to validate dff
|
2023-01-18 17:59:52 -08:00 |