6024e35f89
[core] fixed a bug
2024-07-05 18:50:14 -07:00
4b53e57c92
[core] fixed a bug
2024-07-04 13:33:04 -07:00
d2a68ff9c5
[core] now corner tile are considered as config child
2024-07-04 13:25:57 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
717906ea17
[core] code format
2023-08-25 15:13:39 -07:00
89b392a51f
[core] adapt changes in is_sb_exist()
2023-08-25 15:13:00 -07:00
94d80a9b7c
[core] code format
2023-08-08 16:28:56 -07:00
867da98d3f
[core] update to use latest api from vpr upstream
2023-08-08 16:28:19 -07:00
d3895c3dc0
[core] code format
2023-08-03 17:34:25 -07:00
f4cbc95053
[core] syntax
2023-08-03 17:33:57 -07:00
2facde2097
[core] reworked fabric generator to use config child type
2023-08-03 12:57:50 -07:00
87f2822ef8
[core] working on logical and physical children
2023-08-02 19:46:27 -07:00
da36b735c6
[core] syntax
2023-07-24 12:13:45 -07:00
327f7f4dab
[core] now adapt to latest API of DeviceGrid
2023-06-07 18:54:48 -07:00
6d31b319a2
[engine] update source files subject to code formatting rules
2022-10-06 17:08:50 -07:00
036933dc14
[engine] fixed more bugs due to the extra modules added to top-level module when using memory bank or frame-based protocols
2022-09-14 16:46:10 -07:00
19a551e641
[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
2021-10-09 16:44:04 -07:00
8f5f30792f
[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
2021-10-08 15:25:37 -07:00
b87b7a99c5
[Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators
2021-09-29 20:21:46 -07:00
be4c850d2d
[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
2021-09-24 12:03:35 -07:00
7e27c0caf3
[Engine] Upgrading top-module fabric generation to support QL memory bank with flatten BL/WLs
2021-09-23 16:16:39 -07:00
7688c0570f
[Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key
2021-09-21 15:08:08 -07:00
36a4da863c
[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
2021-09-20 16:05:36 -07:00
26b1e48723
[Engine] Merge BL/WLs in the Grid/CB/SB modules
2021-09-15 11:27:55 -07:00
4af6413c97
[Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column
2021-09-10 17:03:44 -07:00
ba1e277dc9
[Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine
2021-09-10 15:05:46 -07:00
35c7b09888
[Engine] Bug fix for mistakes in calculating number of BLs/WLs for QL memory bank
2021-09-09 15:23:29 -07:00
b787c4e100
[Engine] Register QL memory bank as a legal protocol
2021-09-09 15:06:51 -07:00
ed80d6b3f4
[Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier
2021-09-05 13:23:38 -07:00
cf2e479d18
[Engine] Refactor the TopModuleNumConfigBits data structure
2021-09-05 12:01:38 -07:00
f75456e304
[Engine] Update BL/WL estimation function for QL memory bank protocol
2021-09-05 11:53:33 -07:00
5759f5f35b
[Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder
2021-09-03 17:55:23 -07:00
088198c861
[Tool] enhance error checking in fabric key parser
2020-11-13 10:56:00 -07:00
5bcd559851
[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
2020-10-30 17:29:04 -06:00
0d77916041
[Tool] Support multi-region frame-based configuration protocol
2020-10-30 10:43:11 -06:00
8ef6ae32fb
[Tool] Bug fix for bitstream estimator due to the current special status of frame-based protocol
2020-10-29 17:35:55 -06:00
987eccf586
[Tool] Bug fix in multi-region memory bank; Basic test passed
2020-10-29 16:26:45 -06:00
448e88645a
[Tool] Support multiple memory banks in top-level module
2020-10-29 12:42:03 -06:00
bd49ea95d4
[Tool] Add function to comput configuration bits by region
2020-10-28 12:37:09 -06:00
e179a58b15
[OpenFPGA Tool] Bug fix for long runtime
2020-09-28 20:42:18 -06:00
f93d46a870
[OpenFPGA Tool] Add multiple configuration chain support in top module builder
2020-09-28 19:03:19 -06:00
552dddffd0
[OpenFPGA Tool] Support configurable regions in module manager
2020-09-28 18:13:07 -06:00
66e5e141a1
improve fabric key loader to reduce runtime
2020-07-07 10:19:34 -06:00
824b56f14c
fabric key can now accept instance name only; decoders are no longer part of the key
2020-07-06 16:42:33 -06:00
e7d5736269
add profile time to top module builder for better spot on runtime/memory overhead sources
2020-06-29 23:17:03 -06:00
9d32a5b81f
add alias name support for fabric key
2020-06-27 14:59:53 -06:00
a5055e9d26
add support about loading external fabric key
2020-06-12 13:03:11 -06:00
9dbf536306
add shuffled configurable children support for top module
2020-06-12 11:16:53 -06:00
3c10af7f2b
bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
2020-06-11 19:31:14 -06:00
5368485bd6
keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
2020-06-11 19:31:14 -06:00
tangxifan
chungshien