tangxifan
|
6fc2924438
|
[core] syntax
|
2023-09-16 18:16:30 -07:00 |
|
tangxifan
|
d61d88f12e
|
[core] fixed some bugs in verilog writer due to renaming
|
2023-09-16 18:13:22 -07:00 |
|
tangxifan
|
37573abc22
|
[core] code format
|
2023-09-15 23:32:40 -07:00 |
|
tangxifan
|
c85c64eb5a
|
[core] syntax
|
2023-09-15 23:30:34 -07:00 |
|
tangxifan
|
bc407e5d69
|
[core] code complete for rename modules
|
2023-09-15 23:22:31 -07:00 |
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tangxifan
|
2a45b49890
|
[core] developing renaming commands. options and functions
|
2023-09-15 19:15:18 -07:00 |
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tangxifan
|
af67b02cca
|
[lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules
|
2023-09-15 13:51:14 -07:00 |
|
tangxifan
|
eaadff3448
|
[core] fixed some bugs
|
2023-09-06 22:49:56 -07:00 |
|
tangxifan
|
bcb82d43af
|
[core] code format
|
2023-09-06 22:40:59 -07:00 |
|
tangxifan
|
2fee56548b
|
[core] fixed some bugs
|
2023-09-06 22:39:59 -07:00 |
|
tangxifan
|
f544953085
|
[core] code format
|
2023-09-06 22:29:30 -07:00 |
|
tangxifan
|
f8b2eec988
|
[core] now default net type wire will not appear. timescale does not show in fabric netlists
|
2023-09-06 22:27:51 -07:00 |
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tangxifan
|
539bcba851
|
[core] now default nettype is reverted to 'wire' at the end of each module; Being compatible with Verilog 2001 standard; Avoid unnecessary impacts on netlists which do not explicitly define default net types
|
2023-09-06 17:23:41 -07:00 |
|
tangxifan
|
dfe5447e2a
|
[core] format
|
2023-08-25 15:21:24 -07:00 |
|
tangxifan
|
b8c66b06a0
|
[core] syntax
|
2023-08-25 15:17:52 -07:00 |
|
tangxifan
|
717906ea17
|
[core] code format
|
2023-08-25 15:13:39 -07:00 |
|
tangxifan
|
89b392a51f
|
[core] adapt changes in is_sb_exist()
|
2023-08-25 15:13:00 -07:00 |
|
tangxifan
|
55e5f738ce
|
[core] code format
|
2023-08-25 11:58:15 -07:00 |
|
tangxifan
|
92f92658c9
|
[core] remove useless errors
|
2023-08-25 11:53:49 -07:00 |
|
tangxifan
|
a6d43beaca
|
[core] now tile verilog writer supports relative paths
|
2023-08-21 22:25:52 -07:00 |
|
tangxifan
|
66cc375996
|
[core] remove debugging messages
|
2023-08-18 22:08:47 -07:00 |
|
tangxifan
|
19d4d9a16d
|
[core] code format
|
2023-08-18 21:05:26 -07:00 |
|
tangxifan
|
fc523bed32
|
[core] fixed some bugs in spotting the correct pin index of given subtiles
|
2023-08-18 21:04:37 -07:00 |
|
tangxifan
|
3d8f76269a
|
[core] fixed a bug when io is in the center of 3x3 fabric
|
2023-08-18 12:42:15 -07:00 |
|
tangxifan
|
e9fd22790d
|
[core] fixed a bug where pass thru cb blocks are not connected in tiles
|
2023-08-17 15:26:32 -07:00 |
|
tangxifan
|
399f087c50
|
[core] code format
|
2023-08-17 13:54:31 -07:00 |
|
tangxifan
|
414f7379c6
|
[core] fixed some bugs in debugging messages
|
2023-08-17 13:52:21 -07:00 |
chungshien
|
aabbd330b3
|
Address follow up from PR 1259 (1)
|
2023-08-11 08:06:57 -07:00 |
|
chungshien
|
6c0df8da20
|
Address follow up from PR 1259
|
2023-08-11 07:59:53 -07:00 |
|
tangxifan
|
788e3c17a9
|
[core] format
|
2023-08-08 23:02:20 -07:00 |
|
tangxifan
|
1c8c4fedbb
|
[core] fix memory leak
|
2023-08-08 23:01:52 -07:00 |
|
tangxifan
|
ff6fa1e90c
|
[core] fix memory leak
|
2023-08-08 22:41:43 -07:00 |
|
tangxifan
|
94d80a9b7c
|
[core] code format
|
2023-08-08 16:28:56 -07:00 |
|
tangxifan
|
867da98d3f
|
[core] update to use latest api from vpr upstream
|
2023-08-08 16:28:19 -07:00 |
|
tangxifan
|
bb945b2816
|
Merge branch 'master' into openfpga-issue-1256
|
2023-08-07 13:49:19 -07:00 |
|
tangxifan
|
4d37421735
|
[core] fixed a bug on loading subkey to support fabric keys
|
2023-08-07 10:40:22 -07:00 |
|
tangxifan
|
18acb39fad
|
[core] fixed a bug where heterogeneous fabric may fail
|
2023-08-06 22:12:32 -07:00 |
|
tangxifan
|
26c8b5146c
|
[core] fixed a bug where release build will fail
|
2023-08-06 21:44:15 -07:00 |
|
tangxifan
|
c5b1918e47
|
[core] fixed a critical bug which causes reg test failures when group_config_block is off
|
2023-08-06 13:11:17 -07:00 |
|
tangxifan
|
beee2369c9
|
[core] fixed a bug
|
2023-08-05 22:06:17 -07:00 |
|
tangxifan
|
a1f8b3c441
|
[core] fixed a bug on bitstream generator on supporting group_config_block
|
2023-08-05 21:58:03 -07:00 |
|
tangxifan
|
68f07d6fc9
|
[core] code format
|
2023-08-05 20:53:58 -07:00 |
|
tangxifan
|
2aab94cd6c
|
[core] syntax
|
2023-08-05 14:11:57 -07:00 |
|
tangxifan
|
22816a7ed4
|
[core] syntax
|
2023-08-05 14:04:57 -07:00 |
|
tangxifan
|
f4d7ad2bd1
|
[core] trying to fix the bug on instance naming so that bitstream generation can work
|
2023-08-05 13:38:51 -07:00 |
|
tangxifan
|
9a23dc7bff
|
[core] fixed some bugs which causes architecture bitstream generation failed when supporting group_config_block
|
2023-08-04 21:20:21 -07:00 |
|
tangxifan
|
7d8d686f74
|
[core] add status codes to build grid modules
|
2023-08-04 16:52:43 -07:00 |
|
tangxifan
|
bb9cf6dbcb
|
[core] fixed a critical bug which causes undriven nets on config bus in group config block
|
2023-08-04 16:45:15 -07:00 |
|
tangxifan
|
64c0839e30
|
[core] now verilog writer supports memory group modules
|
2023-08-04 16:11:33 -07:00 |
|
tangxifan
|
a0f81a5bf2
|
[core] now verilog generator can output feedthrough memory module to files
|
2023-08-04 13:34:38 -07:00 |