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OpenFPGA
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3911 Commits

Author SHA1 Message Date
komaljaved-rs 6d11dc275d
Update ci_test.yml 2021-07-01 16:01:38 +05:00
komaljaved-rs 4b8e178947
Update ci_test.yml 2021-07-01 15:44:59 +05:00
komaljaved-rs 2469f25ef4 updated submodule 2021-07-01 15:14:59 +05:00
komaljaved-rs 7a703659e7 Merge branch 'master' of github.com:RapidSilicon/OpenFPGA_RS 2021-07-01 15:08:26 +05:00
komaljaved-rs 6559f71082 added ci_scripts 2021-07-01 15:07:37 +05:00
komaljaved-rs 1e81dd897f
Update ci_test.yml 2021-07-01 14:47:59 +05:00
komaljaved-rs cbb4b32f7f
Rename openfpga.yml to ci_test.yml 2021-07-01 14:45:38 +05:00
komaljaved-rs 4b6b0273ba
Create openfpga.yml 2021-07-01 14:44:48 +05:00
komaljaved-rs a08de86000
Update build.yml 2021-06-30 14:58:13 +05:00
tangxifan 322238f431
Merge pull request #348 from lnis-uofu/testbench_flag 
Deprecate pre-processing flags ``define_simulation.v`` and enable testbench generation without self checking
 2021-06-29 21:02:05 -06:00
tangxifan 9eeec05a1f [Test] Bug fix 2021-06-29 19:55:07 -06:00
tangxifan f32ffb6d61 [Test] Bug fix 2021-06-29 18:51:28 -06:00
tangxifan 56b0428eba [Misc] Bug fix 2021-06-29 18:48:19 -06:00
tangxifan c6089385b0 [Misc] Bug fix 2021-06-29 18:34:41 -06:00
tangxifan 5f5a03f17f [Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches 2021-06-29 18:28:38 -06:00
tangxifan 2c1692e6dc [Test] Bug fix 2021-06-29 17:54:25 -06:00
tangxifan 4fb34642ca [Script] Add a new example script for global tile clock running full testbench 2021-06-29 17:53:56 -06:00
tangxifan 9655bc35cb [Script] Bug fix due to the full testbench generation changes 2021-06-29 17:04:19 -06:00
tangxifan b5df1f9aeb [Tool] Bug fix for redundant endif in netlists 2021-06-29 17:02:16 -06:00
tangxifan b83eef47b4 [Tool] Bug fix for testbench generation without self checking codes 2021-06-29 16:27:29 -06:00
tangxifan cbea4a3cb6 [Test] Add the test cases to regression test 2021-06-29 16:08:22 -06:00
tangxifan 30c2f597f2 [Test] Added two cases to validate testbench generation without self checking 2021-06-29 16:06:15 -06:00
tangxifan 20faf82e64 [Script] Rename example script 2021-06-29 16:02:35 -06:00
tangxifan 01391fd81e [Script] Added example scripts that use OpenFPGA to generate testbenches without self checking features 2021-06-29 15:56:33 -06:00
tangxifan 7119075253 [Script] Remove the post-processing on ``define_simulation.v`` since it is deprecated 2021-06-29 15:52:42 -06:00
tangxifan 6a260cadbf [Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose 2021-06-29 15:42:23 -06:00
tangxifan ac9046b7d2 [Doc] Remove ``define_simulation.v`` since it is no longer needed. 2021-06-29 15:38:35 -06:00
tangxifan 7ac7de789e [Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes 2021-06-29 15:26:40 -06:00
tangxifan 77dddaeb39 [Tool] Remove the preprocessing flags ``FORMAL_SIMULATION`` and ``FORMAL_VERIFICAITON`` because now ``write_testbench`` command can be called many times to generate different versions 2021-06-29 14:26:33 -06:00
tangxifan d0670e64d4
Merge pull request #347 from lnis-uofu/testbench_force 
Use ``force`` in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL
 2021-06-29 13:43:29 -06:00
tangxifan a3208b332b [Tool] Use 'force' in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL 2021-06-29 11:50:53 -06:00
tangxifan 75a12e55de [HDL] Remove the instrusive signal initialization in the configuration flip-flop HDL codes 2021-06-29 11:40:22 -06:00
tangxifan 36764b8180
Merge pull request #345 from lnis-uofu/testbench_cleanup 
Remove the hardcoded factor when computing simulation timing
 2021-06-29 10:55:13 -06:00
tangxifan dfe1db996a [Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time 2021-06-29 09:56:04 -06:00
tangxifan 74148ec491
Merge pull request #343 from lnis-uofu/preconfig_wrapper 
Bug fix in Preconfigured Fabric Wrapper Generator
 2021-06-27 21:44:56 -06:00
tangxifan 403190a051
Merge branch 'master' into preconfig_wrapper 2021-06-27 20:05:36 -06:00
tangxifan b4c587f10b [Test] Added the new test cases to regression tests 2021-06-27 19:58:15 -06:00
tangxifan 6f0600e17f [Test] Added two test cases for generating preconfigured fabric wrapper in different styles 2021-06-27 19:56:01 -06:00
tangxifan 4a623bec79 [Script] Add example openfpga shell script to generate preconfigured fabric wrapper 2021-06-27 19:55:40 -06:00
tangxifan 87446a14c3 [Tool] Bug fix for the option ``--embed_bitstream none`` 2021-06-27 19:45:06 -06:00
tangxifan 873b6c4d36
Merge pull request #342 from lnis-uofu/preconfig_wrapper 
New option ``--embed_bitstream`` for Preconfigured fabric wrapper in place of ``--support_icarus_simulator``
 2021-06-25 17:39:56 -06:00
tangxifan 30027b8c15 [Doc] Update doc to deprecate anything related to '--support_icarus_simulator' and '--include_signal_init' 2021-06-25 15:27:15 -06:00
tangxifan 991062e9bf [Tool] Bug fix 2021-06-25 15:22:42 -06:00
tangxifan fae5e1dfdf [Script] Upgrade openfpga shell script with the new option '--embed_bitstream' 2021-06-25 15:16:37 -06:00
tangxifan 11d0283771 [Doc] Remove option '--support_icarus_simulator'. Add option '--embed_bitstream' 2021-06-25 15:11:12 -06:00
tangxifan 90163fab6c [Tool] Replace option '--support_icarus_simulator' with a new one '--preload_bitstream <string>' 2021-06-25 15:06:07 -06:00
tangxifan 1b6e1e5516
Merge pull request #341 from lnis-uofu/sim_info 
Update Simulation Exchangeable Information Writer
 2021-06-25 11:42:44 -06:00
tangxifan 507f5ee54c [Doc] Update documentation about time unit support in writing simulation file 2021-06-25 10:34:43 -06:00
tangxifan 2bb514c51a [Tool] Support time unit in writing simulation information file 2021-06-25 10:33:29 -06:00
tangxifan 8e2ba718d0 [Doc] update documentation on the new option '--testbench_type' 2021-06-25 10:16:48 -06:00