tangxifan
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696d4a9522
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remove useless channel wire module generation
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2019-11-05 16:10:00 -07:00 |
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tangxifan
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a308a13d7c
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use prefix instead of lib_name when building modules, then use lib_name for standard cell modules
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2019-11-05 15:41:59 -07:00 |
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tangxifan
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2fbb88d25b
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remove legacy codes
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2019-11-05 13:52:42 -07:00 |
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tangxifan
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66047e4a45
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refactoring Verilog simulation flag generations
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2019-11-05 13:45:11 -07:00 |
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tangxifan
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13f2d33d37
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refactored fpga_define.v generation
Please enter the commit message for your changes. Lines starting
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2019-11-05 12:41:43 -07:00 |
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tangxifan
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8ef9e994d8
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rename source files to be what they are actually doing
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2019-11-05 12:18:23 -07:00 |
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tangxifan
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aaaf7a0d19
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remove legacy codes in writing include netlists
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2019-11-04 21:06:14 -07:00 |
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tangxifan
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ebab0e91ef
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refactored include netlist writer
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2019-11-04 20:55:30 -07:00 |
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tangxifan
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5d507ae8ee
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bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!!
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2019-11-04 18:05:50 -07:00 |
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tangxifan
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69bc858e62
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bring autocheck top testbench back to simulation deck, start testing
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2019-11-04 15:35:04 -07:00 |
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tangxifan
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3274a49779
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fine tuning top testbench and getting ready for testing
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2019-11-04 12:08:36 -07:00 |
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tangxifan
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d7bbae76a4
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adding stimuli to benchmark inputs in top-level testbench
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2019-11-03 20:20:14 -07:00 |
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tangxifan
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3e9968d2f0
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keep refactoring top-level testbench with auto-check features
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2019-11-03 18:59:54 -07:00 |
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tangxifan
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1fb29df1e2
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cleaning verilog file lines
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2019-11-03 17:58:18 -07:00 |
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tangxifan
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0ec465d4e1
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refactoring auto-check top Verilog testbench
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2019-11-03 17:41:29 -07:00 |
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tangxifan
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dc241e6c03
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add explicit port mapping support in testbenches; remove dangling ports in benchmarks
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2019-11-02 23:03:47 -06:00 |
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tangxifan
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05a830de1b
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bring ini writer for formality scripts back
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2019-11-02 18:56:54 -06:00 |
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tangxifan
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c681726124
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try to enlarge write buffers in ini writer, but these codes should be fully reworked
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2019-11-02 18:33:05 -06:00 |
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tangxifan
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3ad2a93539
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start bring back ini writer bit by bit
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2019-11-02 18:20:25 -06:00 |
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tangxifan
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644ca4f0a4
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add vpr test run in Travis
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2019-11-02 17:49:22 -06:00 |
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tangxifan
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cb74d120e7
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shadow ini writer to help debugging
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2019-11-02 17:31:05 -06:00 |
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tangxifan
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fc164abd49
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remove unused variable in sim info writer
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2019-11-02 16:35:32 -06:00 |
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tangxifan
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0852ef33c3
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remove caching for deps
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2019-11-02 16:30:01 -06:00 |
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tangxifan
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e1a7a2895a
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simulation ini file name can be customizable
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2019-11-02 09:59:34 -06:00 |
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tangxifan
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d5d7450ce7
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make simulation ini writing as an option
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2019-11-02 09:46:12 -06:00 |
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tangxifan
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c3db880599
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adding explicit file path to simulation info writer
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2019-11-02 09:21:02 -06:00 |
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tangxifan
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358e9892ac
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reduce some error message to warnings
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2019-11-02 00:09:13 -06:00 |
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tangxifan
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5bae8fecde
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add debugging mode to see why travis failed
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2019-11-01 23:26:08 -06:00 |
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tangxifan
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495000c649
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recover caching for libs
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2019-11-01 21:37:17 -06:00 |
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tangxifan
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17f816effd
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try to uncache libini
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2019-11-01 21:26:22 -06:00 |
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tangxifan
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e9ed64c926
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try to let cmake identify libini
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2019-11-01 21:17:35 -06:00 |
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tangxifan
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f811ddc62a
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Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-11-01 20:52:45 -06:00 |
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tangxifan
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f70f387f9f
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minor tuning on ini compilation
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2019-11-01 20:51:49 -06:00 |
Ganesh Gore
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a880802803
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Bug Fix: Corrected read VPR stat filename
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2019-11-01 20:51:05 -06:00 |
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tangxifan
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a9c02cd2a5
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fix errors in travis
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2019-11-01 20:32:40 -06:00 |
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tangxifan
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550df19ee2
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use a stable cmake now
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2019-11-01 20:26:29 -06:00 |
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tangxifan
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3669a47d3b
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reworked the ini writer
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2019-11-01 20:25:01 -06:00 |
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tangxifan
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dab66b8be7
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start adding auto check cpp files
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2019-11-01 19:49:50 -06:00 |
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tangxifan
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e2b042c61c
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Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-11-01 18:27:27 -06:00 |
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Ganesh Gore
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370a5ed408
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Bug Fix: shifter ff.v include path to tcl script
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2019-11-01 18:22:40 -06:00 |
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Ganesh Gore
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595d2d3070
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Simple argument shuffle
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2019-11-01 18:21:26 -06:00 |
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Ganesh Gore
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27005d6640
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Added Modelsim Python Script
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2019-11-01 18:20:40 -06:00 |
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Ganesh Gore
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a0512e40b1
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Created intermidiate file for modelsim simulation
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2019-11-01 18:20:00 -06:00 |
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tangxifan
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4d4ef1113d
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give up iverilog on travis
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2019-11-01 17:53:50 -06:00 |
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tangxifan
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1d78725d4d
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add installation
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2019-11-01 17:48:17 -06:00 |
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tangxifan
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9a37b66d53
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move installation to a script
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2019-11-01 17:39:30 -06:00 |
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tangxifan
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161664f253
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try to comfort iverilog package extraction
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2019-11-01 17:24:06 -06:00 |
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tangxifan
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2dc3a4eb1f
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fixing bugs in iVerilog installation
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2019-11-01 17:03:21 -06:00 |
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tangxifan
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5332588e82
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retrying travis installation of iVerilog 10.3
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2019-11-01 16:36:29 -06:00 |
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tangxifan
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3ae841b80f
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start refactoring auto-check top testbench generation
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2019-11-01 16:33:12 -06:00 |