tangxifan
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f558405887
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ported verilog testbench generator online. Split from fabric generator. Testing to be done
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2020-02-27 12:33:09 -07:00 |
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tangxifan
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b3796b0818
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build io location map
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2020-02-26 19:58:18 -07:00 |
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tangxifan
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25e0583636
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add io location map data structure and start porting verilog testbench generator
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2020-02-26 17:10:57 -07:00 |
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tangxifan
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a26d31b87f
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make write bitstream online
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2020-02-26 11:09:23 -07:00 |
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tangxifan
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4024ed63cb
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add truth table build up for physical LUTs
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2020-02-25 22:39:42 -07:00 |
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tangxifan
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8e9660b816
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add mapped block fast look-up as placement annotation
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2020-02-24 16:09:29 -07:00 |
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tangxifan
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2d17395e13
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start integrating fpga_bitstream. Bring data structures online
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2020-02-22 23:04:42 -07:00 |
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tangxifan
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4abaef14b5
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bug fixed in pb_pin fix-up. This is due to A CRITICAL BUG IN PHYSICAL_TILE PIN MAPPING!!!
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2020-02-20 20:50:59 -07:00 |
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tangxifan
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3e07d7d5e0
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finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset
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2020-02-20 20:26:20 -07:00 |
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tangxifan
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fdb27c5a6b
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move lb_rr_graph construction to repack command
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2020-02-20 13:24:34 -07:00 |
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tangxifan
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409b3f6896
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add lb_rr_graph builder for the refactored version
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2020-02-17 21:11:56 -07:00 |
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tangxifan
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8e97443410
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start working on repack
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2020-02-17 17:57:43 -07:00 |
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tangxifan
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62e4f14e30
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add lb_rr_graph to device annotation
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2020-02-17 17:26:27 -07:00 |
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tangxifan
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6c69b52ded
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Add missing file
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2020-02-17 17:11:29 -07:00 |
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tangxifan
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e37ac8a098
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add grid module Verilog writer
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2020-02-16 16:04:41 -07:00 |
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tangxifan
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c6c3ef71f3
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adapt all the Verilog submodule writers and bring it onlien
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2020-02-16 13:35:18 -07:00 |
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tangxifan
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bf54be3d00
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add option data structure for FPGA Verilog
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2020-02-15 21:39:47 -07:00 |
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tangxifan
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da79ef687c
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add missing files
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2020-02-15 20:54:37 -07:00 |
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tangxifan
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8b0df8632c
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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tangxifan
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539f13720a
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tile direct supports inter-column/inter-row direct connections
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2020-02-15 13:42:53 -07:00 |
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tangxifan
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213c611c0b
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add tile direct builder
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2020-02-14 22:21:32 -07:00 |
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tangxifan
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afe8278670
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put routing module builder online
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2020-02-13 17:35:29 -07:00 |
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tangxifan
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89086ed080
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add verbose output to build grid module
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2020-02-13 15:38:26 -07:00 |
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tangxifan
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072965cd64
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make grid module builder online; basic support on physical tiles
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2020-02-13 15:27:16 -07:00 |
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tangxifan
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895d5b5a0a
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add utils for grid module builder
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2020-02-12 20:25:05 -07:00 |
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tangxifan
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fddd3c9463
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add mux module builder
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2020-02-12 19:45:14 -07:00 |
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tangxifan
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f11832b8cf
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start integrating module graph builder
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2020-02-12 17:53:23 -07:00 |
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tangxifan
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13fadd0f91
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move compact routing hierarchy to build_fabric command
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2020-02-12 15:49:47 -07:00 |
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tangxifan
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c78d3e9af1
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add mux library builder
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2020-02-12 14:58:23 -07:00 |
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tangxifan
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a736e09c29
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add rr_switch binding in link openfpga arch command
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2020-02-12 10:52:20 -07:00 |
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tangxifan
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a31d6c6d1e
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rename pb_type annotation to device annotation
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2020-02-12 09:52:18 -07:00 |
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tangxifan
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175bef014a
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add compact_routing hierarchy command
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2020-02-11 17:40:37 -07:00 |
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tangxifan
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1372f748f1
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put GSB builder online
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2020-02-11 16:37:14 -07:00 |
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tangxifan
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3d7eff64b9
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bug fixed for lut truth table fixup. Results look good
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2020-02-06 17:47:25 -07:00 |
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tangxifan
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ed9e038845
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add functionality of LUT truth table fix-up
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2020-02-06 17:14:29 -07:00 |
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tangxifan
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99f5a86b49
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bug fixed for routing annotation and routing net fix-up
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2020-02-06 12:54:55 -07:00 |
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tangxifan
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dad204674b
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done an initial version of clustering net fix-up based on routing results. Debugging on the way
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2020-02-05 21:50:52 -07:00 |
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tangxifan
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75c3507acf
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add verbose output option for openfpga linking architecture
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2020-01-31 11:36:58 -07:00 |
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tangxifan
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d62c9fe86f
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adding pb_graph_node annotation
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2020-01-30 16:40:13 -07:00 |
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tangxifan
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e48ab8cb44
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move annotation source files to a separated folder
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2020-01-30 13:37:41 -07:00 |
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tangxifan
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f28ca3ffd0
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add more echo to log
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2020-01-29 18:58:57 -07:00 |
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tangxifan
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87f1ca1151
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add naming fix-up report generation
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2020-01-29 18:56:47 -07:00 |
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tangxifan
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2dc4c26257
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add naming fix-up
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2020-01-29 17:49:33 -07:00 |
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tangxifan
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8c86c0af04
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add check netlist naming conflict command and functions
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2020-01-29 16:23:41 -07:00 |
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tangxifan
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d2c47693f6
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add check codes for mode bits annotation to pb_types and clean up utils source files
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2020-01-29 14:29:00 -07:00 |
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tangxifan
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a4381563bc
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move check codes to separated source files
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2020-01-29 13:47:59 -07:00 |
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tangxifan
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b67358d2c5
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add check codes for physical pb_type circuit model annotation
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2020-01-29 12:56:49 -07:00 |
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tangxifan
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a722438fa3
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add mode bits binding to pb_type annotation
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2020-01-29 12:27:55 -07:00 |
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tangxifan
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61b487eb75
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show more information in the log file
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2020-01-29 11:29:41 -07:00 |
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tangxifan
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399ba8d648
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add pb type port mapping to circuit model ports
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2020-01-29 11:24:14 -07:00 |
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tangxifan
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cf3c5b5c42
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add circuit model type checking for physical pb_type annotation
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2020-01-29 10:41:02 -07:00 |
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tangxifan
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8a7a4dc48e
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add physical type annotation for interconnects and inference
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2020-01-28 21:59:10 -07:00 |
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tangxifan
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bb7fa2af77
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add pb interconnect binding to circuit model
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2020-01-28 17:04:10 -07:00 |
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tangxifan
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1651c9ca18
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add binding between physical pb_type and circuit models
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2020-01-28 16:03:02 -07:00 |
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tangxifan
|
a4a84ca35b
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add check codes for physical pb_type and port annotation
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2020-01-28 15:27:00 -07:00 |
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tangxifan
|
5d9850c2eb
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move pb_type annotation to independent source files as they are getting large
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2020-01-28 15:13:14 -07:00 |
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tangxifan
|
fdcc04cca8
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add physical pb_type inference
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2020-01-28 14:55:47 -07:00 |
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tangxifan
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caeb0bfff8
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add physical pb_type binding for explicit annotations
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2020-01-28 14:27:35 -07:00 |
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tangxifan
|
82f71e82e8
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add check codes for physical mode annotation for pb_types
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2020-01-27 21:15:32 -07:00 |
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tangxifan
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f99dd4c261
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debugged pb_type physical mode annotation
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2020-01-27 20:40:18 -07:00 |
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tangxifan
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b8c504f574
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Do not allow vpr to free everything when it is done. So that we can have access to their device data
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2020-01-27 19:49:05 -07:00 |
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tangxifan
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df056f5d70
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openfpga shell will stay in interactive mode after executing a script
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2020-01-27 17:56:24 -07:00 |
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tangxifan
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5ecb771673
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debugging the annotation to physical mode of pb_types
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2020-01-27 17:43:22 -07:00 |
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tangxifan
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a6fbbce33e
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start developing the openfpga arch binding to vpr
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2020-01-27 15:31:12 -07:00 |
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tangxifan
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5039af2c2f
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update title page
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2020-01-24 17:00:53 -07:00 |
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tangxifan
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a7a1fe8a74
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simplify openfpga title page and add command dependency on read_arch and write_arch
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2020-01-24 16:57:14 -07:00 |
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tangxifan
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655f84b00e
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add write_openfpga_arch command to openfpga shell
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2020-01-23 20:58:15 -07:00 |
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tangxifan
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a03f8aa346
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add profiling for read arch
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2020-01-23 20:12:30 -07:00 |
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tangxifan
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cdb3b6de46
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add read_openfpga_arch to OpenFPGA shell
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2020-01-23 19:10:53 -07:00 |
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tangxifan
|
3cb16a2279
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move basic commands to separated CXX files
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2020-01-23 14:42:49 -07:00 |
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tangxifan
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ba207ee5a5
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start split workload from the main.cpp in openfpga
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2020-01-23 13:24:35 -07:00 |